WO2002051011A2

WO2002051011A2 - Circuit for configuring a programmable logic device

Info

Publication number: WO2002051011A2
Application number: PCT/GB2001/005603
Authority: WO
Inventors: Mel Albert Gerard Long
Original assignee: Ubinetics Limited
Priority date: 2000-12-20
Filing date: 2001-12-18
Publication date: 2002-06-27
Also published as: GB2370396A; AU2002222255A1; GB0031058D0; WO2002051011A3

Abstract

Processor (14) reconfigures FPGA (12) via connector (18) using data from a removable configuration memory (16). Since memory (16) is removable, it can be substituted by a different memory containing different configuration data which is then instantly available to processor (14) for reconfiguring the FPGA (12).

Description

CONFIGURING PROGRAMMABLE DEVICES

The invention relates to programmable logic devices, and to their configuration. Generally speaking, a programmable logic device (PLD) is a device comprising several processing elements which can be configured to perform a selected processing task. A field programmable gate array (FPGA) is an example of a programmable logic device.

The processing elements and/or the interconnections between the processing elements of a PLD need to be configured to perform a selected function. Large scale PLDs tend to be based on volatile memory and therefore configuration data needs to be stored externally. Typically, apparatus containing a PLD also comprises a non-voltatile memory from which configuration data can be loaded into the PLD. The configuration data can be extracted from the memory by the PLD itself or by a processor.

It is an object of the invention to enhance the process of configuring a PLD.

According to one aspect, the invention provides apparatus comprising a programmable logic device and means for connecting removably to the apparatus a configuration memory for providing information for configuring the programmable logic device.

The invention provides the advantage that the configuration memory can be replaced easily with a memory of a different size. This facilitates the use of a very large configuration data set (corresponding to a highly complex configuration or a configuration for a relatively large PLD) or the storage of multiple sets of configuration data. Another advantage of the invention is that, prior to being connected to the apparatus, a configuration memory can be preprogrammed with a desired configuration data set with the result that the configuration data is immediately available upon connection of the configuration memory with the apparatus, i.e., the delay involved in loading the configuration data set into the configuration memory is avoided by the end-user of the PLD. For example, several interchangeable memories could be provided, each storing a different set of configuration data, each set of configuration data being effective to configure the programmable logic device for a different task. Optionally, the configuration memory is non-volatile. Advantageously, the configuration memory can then be programmed with a set of configuration data, disconnected from the programming equipment, moved to the apparatus containing the programmable logic device, and then connected to the apparatus to make the configuration data available for reprogramming the PLD.

The invention also extends to the case where the apparatus comprises several PLDs, each configurable by data obtained via the connecting means from a removable storage device.

The invention also relates to the case where the apparatus comprises a memory removably connected to the connecting means for configuring the (or each) PLD.

In one embodiment, the, or each, PLD is a FPGA.

By way of example only, an embodiment of the invention will now be described, with reference to the accompanying figure which illustrates a processing system comprising a FPGA.

The processing system 10 of Figure 1 comprises a FPGA 12 whose processing elements are configurable to allow the FPGA 12 to perform various processing tasks. Once configured, the FPGA 12 receives processing data from processor 14. The FPGA 12 operates on the processing data received from the data processor 14 and returns the resulting output data to processor 14.

The FPGA 12 is configured and reconfigured under the control of processor 14, which performs the configuration process in accordance with configuration data retrieved from a configuration memory 16. The configuration memory 16 is a non- volatile memory, meaning that it will hold data in a stable state whilst disconnected from uploading or downloading apparatus. The configuration memory 16 is connected to processor 14 via connector 18. Connector 18 is such that the configuration memory 16 is removably connectable thereto. This means that the configuration memory 16 can be removed and replaced with a different configuration memory. This allows for the connection of configuration memories containing different sets of configuration data to the processor 14 in a manner such that their configuration data is immediately available for use in reconfiguring FPGA 12. Furthermore, a configuration memory of a desired size can be connected to connector 18, which means that the site of the memory employed can be tailored to the amount of configuration data to be stored.

When the processor 14 is required to reconfigure the FPGA 12 to perform a different processing role, it reads the desired set of configuration data from configuration memory 16 via connector 18 and uses the set of configuration data in the reconfiguration of the FPGA, tlie reconfiguration being achieved in a known manner.

The configuration memory 16 can store configuration data in a compressed format with the advantage that the data can then be stored in a smaller memory area, enabling a reduction in the configuration memory size.

Claims

1. Apparatus comprising a programmable logic device and means for connecting removably to the apparatus a configuration memory for providing information for configuring the programmable logic device.

2. Apparatus according to claim 1, wherein the programmable logic device is a field programmable gate array.

3. Apparatus according to claim 1 or 2 wherein the configuration memory is non- volatile.

4. Apparatus according to any one of claims 1 to 3, further comprising a memory removably connected to the connecting means for configuring the programmably logic device.

5. A reconfigurable programmable logic device removably connectable to a configuration memory, substantially as hereinbefore described with reference to the accompanying Figure.