WO2002048861A2

WO2002048861A2 - Method of initiating a digital component

Info

Publication number: WO2002048861A2
Application number: PCT/GB2001/005568
Authority: WO
Inventors: Philip Eade
Original assignee: Psion Digital Limited
Priority date: 2000-12-14
Filing date: 2001-12-14
Publication date: 2002-06-20
Also published as: GB0129970D0; WO2002048861A3; GB2372603A

Abstract

A method of initiating a digital component comprises (i) powering up the digital component and a synchronous memory device attached to the digital component; and also (ii) preventing the digital component from reading an initial instruction set from the synchronous memory device until the configuration of the synchronous memory device matches, or is likely to match, the configuration of the digital component.

Description

METHOD OF INITIATING A DIGITAL COMPONENT

BACKGROUND TO THE INVENTION

1. Field of the Invention

This invention relates to initiating or "booting up" a digital component. More specifically, it relates to the process of initiating a digital component in which one step involves the synchronous transfer of an initial instruction sequence to the component. The invention is usable across a range of different digital components, including but not limited to microprocessors, micro-controllers, System On Chip (SoC) devices, DSPs, synchronous memory devices, synchronous read only memory (SROM) and/ or synchronous flash memory.

2. Description of the Prior Art

When a microprocessor is initiated (where the term 'initiated' refers to the microprocessor being powered up, booted or simply switched on) it must be able to run programs immediately. However, the environment in which the microprocessor may be placed is uncertain. Therefore, the microprocessor is usually set up so that its basic running parameters are set to the slowest or most conservative values possible, so as to ensure that it will run correctly in any likely environment. The first task for the microprocessor is usually to reset the device parameters to values optimised for the specific environment in which it finds itself; it does this by loading an initial instruction set. This procedure is usually carried out by loading to the microprocessor the initial instruction set from an associated or attached memory device. At approximately the same time as power is supplied to the microprocessor a READ command is sent to the memory device to transmit the initial instruction set to the microprocessor. This READ command is usually (but not necessarily) issued by the controller (which may be part of the microprocessor).

At present, this arrangement normally has an asynchronous interface between the memory device and the microprocessor. What this means is that the microprocessor does not expect the instructions to be sent from the memory in a time interval or clock rate that is matched to the microprocessor, but rather the microprocessor initially waits a period of time before commencing operation so as to allow for the complete delivery of the initial instruction set from the memory device. The advantage of this methodology is that the microprocessor can usually be guaranteed to have received the complete initial instruction set, even if the memory device transmitting it to the microprocessor is quite slow, and correct boot up can therefore be guaranteed. The disadvantage is that the duration of the boot up process can become quite long. Once the initial instruction set is received it can then reduce the microprocessor waiting period to a more appropriate setting for faster execution.

When a microprocessor is attached to a memory device that has a synchronous interface, a different problem arises. Synchronous devices will return the data to the requesting controller after a given number of clock cycles. It is therefore necessary that the microprocessor that will receive the initial instruction set be configured to expect the data from the memory device on the same clock cycle that the memory device will assert it. However, not all synchronous memory devices default to the same settings when they are first powered up. This makes it impossible to have a microprocessor that can boot up with any type of synchronous memory device attached to it. Rather prior art microprocessors can only boot from a synchronous memory device that has the same default clock settings as its own default values.

SUMMARY OF THE INVENTION In a first aspect of the present invention, there is provided a method of initiating a digital component, comprising the following steps:

(i) powering up the digital component and a synchronous memory device attached to the digital component;

(ii) preventing the digital component from reading an initial instruction set from the synchronous memory device until the configuration of the synchronous memory device matches, or is likely to match, the configuration of the digital component.

In an implementation, to guarantee correctly reading the data from any synchronous memory device to an associated microprocessor, a state machine configures the attached synchronous memory device to the same control parameters (e.g. clock settings) as the microprocessor's default values before a controller (which is usually part of the microprocessor) attempts to request that any data from the memory device be sent to the microprocessor. This ensures that data will be returned on the correct cycle when the controller requests the first instruction for the microprocessor.

One benefit flowing from this arrangement is that more data instructions can be transmitted from the memory device to the microprocessor than can be transmitted using asynchronous memory. Another is increased flexibility in selecting memory devices to work with a specific microprocessor.

The state machine operates once power has been applied to the device containing the microprocessor and the microprocessor's clock has stabilised. The state machine prevents the microprocessor from starting to run, by applying a hold signal to it keeping it in the RESET state. The state machine then issues commands to the memory device, configuring the control parameters in the memory device to be the same as the default parameters of the microprocessor device. After a certain number of clock cycles, the memory device should be correctly configured and the state machine ceases the hold signal to the microprocessor releasing it from its RESET state. The controller will then issue a READ command or commands to the synchronous memory device and because the memory device has been set to the same clock cycle as the microprocessor, the memory device will assert the data following the READ command in the correct cycle for the microprocessor.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described with reference to the accompanying drawings. Figure 1 is a schematic of a SoC (system on a chip) implementation of the present invention, showing its relationship to various possible external memory devices.

Figure 2 is a drawing showing the steps by which a microprocessor using a synchronous memory device according to the invention, and a state machine, is initialised (booted).

Figure 3 is a flowchart showing the steps by which a microprocessor using an asynchronous

memory device as the source for its initial instruction set is initialised (booted). DETAILED DESCRIPTION OF THE PREFERRED IMPLEMENTATION

The invention will be described with reference to a new device designed by Psion Computers Limited of Great Britain that has been named Ηalla", which is a microprocessor System On Chip, a schematic of which is shown as Figure 1. Halla has a processor core 1 and synchronous memory controller 2 and asynchronous memory controller 3 and may boot (begin running code) either from a read only memory (ROM) device 4 (which can be synchronous or asynchronous) or any of synchronous memory devices 5, 6 or 7. Three dedicated boot selection pins determine which type of memory device it will boot from and the data width of that externally attached memory device. The particular microprocessor within Halla is referred to as the ARM920T™ processor and is based on a 16/32 bit embedded reduced instruction set (RISC) cached processor macrocell core developed by ARM Limited of the United Kingdom as part of a family of processors referred to as the ARM9™ Thumb® series. Development kits, including development boards for this processor are available from ARM Limited and further detailed information is available from the ARM website at arm.com.

If it is to boot from a synchronous memory device, a number of default parameters are set within Halla's synchronous memory controller 2 according to the type of external synchronous memory device that is attached. The synchronous memory device may be a synchronous flash device with a CAS (Column Access) cycle of 3 (i.e. the number of clock cycles from asserting a location before data is ready to be read from the memory (on read mode)) and Burst Length of 4 (i.e the number of words to be read out of the device after expiry of a CAS cycle) or a synchronous ROM device with a RAS (Row Access) cycle of 2, CAS cycle of 5 and Burst length of 4, etc. This is again determined by the three dedicated boot selection pins. These settings guarantee booting from any device at a clock speed of up to 100MHz.

When power is first applied to Halla, the state machine (physically resident in the external synchronous memory controller 2) applies a voltage to the RESET leads of the ARM920T microprocessor of Halla. This and subsequent process steps are illustrated in Figures 2 and 3. The state machine then issues 10 NOP commands (No Operation Commands - each NOP defines a clock cycle) to the synchronous memory device to initialise it, putting it into a known state. This is followed by the Load Mode Register command to configure the external synchronous memory device control parameters. The Load Mode Register command makes the memory cognisant of which clock cycles to use to properly construe incoming signals and on which clock cycles it needs to output data and is therefore key to implementing the invention on this architecture.

Three further NOP commands are then issued to ensure that the control word is properly utilised, after which the voltage to the RESET leads of the microprocessor core is switched off, and the microprocessor core thereby released from RESET. Having been released from RESET, the processor core requests data instructions via the synchronous memory controller 2 sending a

READ command to the synchronous external memory device. The synchronous external memory device, operating in sync with the microprocessor, then loads the initial instruction set to the microprocessor. The Halla device as set forth in Figure 1. has an address bus with address lines A[26:0] (i.e., there are 27 address lines numbers A26 through 0). The synchronous address bus (SYA[15:0]) is multiplexed onto Address lines A[17:2] (i.e. lines in the range 2 to 17 are shared). When setting the MODE Register within a synchronous device, the command word is placed on the address Unes as shown below dependant upon whether a Synchronous ROM or SDRAM or Synchronous Flash is attached. Once the MRS (a special instruction needed to precede a Load Mode Register Command) and InitiaHse bits have been appropriately set, the address of subsequent read instructions on the internal lines will be output on external lines SYA[13:0] respectively as the Synchronous Mode command. Hence the actual Read Address specifies the Command Word. The four MS address bits, N, will determine which memory bank this is directed to. Thus, for example, if booting from SROM or SFLASH then N is 0x0.

nb RFU = Reserve for Future

Table 1

The tables below show the standard codings for CAS, RAS, Burst Type, Write Burst Lengthand BL settings. From these the necessary addresses can be calculated.

Table 2

Table 3

Note that for SDRAM and SFlash, the RAS setting is ignored by the device, i.e. it is not a number of clock cycles but a specified wait time. However, this controller must specify a number of clocks for RAS which is less than or equal to the specified RAS time.

Table 4 The following are examples of the Read addresses that must be asserted to set up the following parameters on a 32 bit wide external device. SROM default READ Address:- 0xN001,8400 (This sets RAS=2, CAS=5, Sequential, BL=4) If using a 16 bit wide external bus then the following addresses must be used. SROM default READ Address:- 0xN000,C400 (This sets RAS=2, CAS=5, Sequential, BL=8)

The Synchronous Memory control engine 2 arbitrates between the access requests from the two data ports (the main AHB bus and LCD AHB interfaces, where AHN is the name of an internal data bus in the proprietary AMBA® architecture), and generates an efficient sequence of commands, to issue to the Synchronous Memory devices to transfer the requested data.

Following power on, every Synchronous Memory device in the system must be initialised before it can be used to ensure that the Controller and external devices have the same settings. If the system is booting up using a Synchronous ROM (on nSDCS3) then a short configuration sequence (10 NOPS + Load Mode Register + 3 NOPS) will be activated before releasing the

ARM920T™ processor from RESET. This ensures that a known configuration (RAS=2,

CAS=5, and Burst Length=4) is set whatever device may be attached as different Synchronous

ROMs default to different Burst Lengths. A similar automatic boot up sequence will be initiated when booting from Synchronous Flash, (WBL=1, CAS=3, Burst Length=4).

Table 5

The following power-up sequence is executed by an internal state machine after power on reset: power is applied to the circuit with inputs CKE (Clock Enable) and DQM pulled high so that they rise with the supply NDD and VDDQ. Following power-up, the processor is held in the reset state whilst the clock runs. The Command pins are put in the NOP condition for 10 cycles by setting the Initialise and MRS bits to 1,1 respectively, whilst the SROM device is clocked. The default settings are written to the Mode register by setting the Initialise and MRS bits to 0,1 respectively and reading the appropriate address (see Table 5 above). After 3 clock cycles from the mode register set cycle, the device is ready for power-up, all data outputs will be in a high impedance state. The processor is released from the reset state.

Claims

1. A method of initiating a digital component comprising the following steps:

2. The method of Claim 1 in which a state machine is used to prevent the digital component from reading the initial instruction set from the synchronous memory device until the configuration of the synchronous memory device matches, or is likely to match, the configuration of the digital component.

3. The method of Claim 2 in which, in order for the configuration of the synchronous memory device to match, or be likely to match, the configuration of the digital component then the clock settings of the synchronous memory device must match the default clock settings of the digital component.

4. The method of Claim 2 in which the state machine prevents the digital component from reading the initial instruction set by placing or maintaining the digital component in a reset state.

5. The method of Claim 4 in which the state machine releases the digital component from its reset state after the synchronous memory device has performed a predefined number of clock cycles sufficient to ensure that it is in synchronisation with the digital component.

6. The method of Claim 5 in which a Load Mode Register command is sent to the synchronous memory device to make the configuration of that device match the configuration of the digital component.

7. A digital component adapted to be initiated in accordance with the method of any preceding method Claim.