WO2002037565A3 - Method of connecting conductors on different levels of a microelectronic device and associated apparatus - Google Patents

Method of connecting conductors on different levels of a microelectronic device and associated apparatus Download PDF

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Publication number
WO2002037565A3
WO2002037565A3 PCT/US2001/045250 US0145250W WO0237565A3 WO 2002037565 A3 WO2002037565 A3 WO 2002037565A3 US 0145250 W US0145250 W US 0145250W WO 0237565 A3 WO0237565 A3 WO 0237565A3
Authority
WO
WIPO (PCT)
Prior art keywords
metallic layer
layer
dielectric layer
microelectronic device
via metal
Prior art date
Application number
PCT/US2001/045250
Other languages
French (fr)
Other versions
WO2002037565A2 (en
Inventor
Sundeep N Nangalia
Robert L Wood
Philip Alan Deane
Bruce William Dudley
Original Assignee
Mcnc
Sundeep N Nangalia
Robert L Wood
Philip Alan Deane
Bruce William Dudley
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mcnc, Sundeep N Nangalia, Robert L Wood, Philip Alan Deane, Bruce William Dudley filed Critical Mcnc
Priority to AU2002220022A priority Critical patent/AU2002220022A1/en
Publication of WO2002037565A2 publication Critical patent/WO2002037565A2/en
Publication of WO2002037565A3 publication Critical patent/WO2002037565A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of electrically connecting conductors on different levels of a microelectronic device is provided. A dielectric layer is deposited over a first metallic layer and a via is then formed in the dielectric layer extending through the dielectric layer. A via metal is then deposited in the via such that the via is in electrical contact with the first metallic layer. A second metallic layer is then deposited over the via metal such that the second metallic layer is in electrical contact with the via metal. The via metal thereby forms an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer. The dielectric layer thereby forms a stencil for deposition of the via metal and an interlevel dielectric separating the first metallic layer from the second metallic layer, while also functioning as a structural substrate for the microelectronic device. A method according to the present invention is useful, for example, to connect a fine pitch conductor on one side of the dielectric layer to a coarse pitch conductor on the opposing side. An associated apparatus is also provided which may also include a microelectronic circuit electrically connected to at least one of the first metallic layer and the second metallic layer.
PCT/US2001/045250 2000-11-06 2001-11-01 Method of connecting conductors on different levels of a microelectronic device and associated apparatus WO2002037565A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002220022A AU2002220022A1 (en) 2000-11-06 2001-11-01 Method of connecting conductors on different levels of a microelectronic device and associated apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70723300A 2000-11-06 2000-11-06
US09/707,233 2000-11-06

Publications (2)

Publication Number Publication Date
WO2002037565A2 WO2002037565A2 (en) 2002-05-10
WO2002037565A3 true WO2002037565A3 (en) 2003-04-24

Family

ID=24840885

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/045250 WO2002037565A2 (en) 2000-11-06 2001-11-01 Method of connecting conductors on different levels of a microelectronic device and associated apparatus

Country Status (2)

Country Link
AU (1) AU2002220022A1 (en)
WO (1) WO2002037565A2 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5116459A (en) * 1991-03-06 1992-05-26 International Business Machines Corporation Processes for electrically conductive decals filled with organic insulator material
EP0501357A1 (en) * 1991-02-25 1992-09-02 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same
US5300402A (en) * 1988-12-30 1994-04-05 International Business Machines Corporation Composition for photo imaging
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
US5699613A (en) * 1995-09-25 1997-12-23 International Business Machines Corporation Fine dimension stacked vias for a multiple layer circuit board structure
WO1999005717A1 (en) * 1997-07-22 1999-02-04 Commissariat A L'energie Atomique Method for making an anisotropic conductive coating with conductive inserts
US5882532A (en) * 1996-05-31 1999-03-16 Hewlett-Packard Company Fabrication of single-crystal silicon structures using sacrificial-layer wafer bonding
JPH11163022A (en) * 1997-11-28 1999-06-18 Sony Corp Semiconductor and manufacture of the same and electronic equipment

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300402A (en) * 1988-12-30 1994-04-05 International Business Machines Corporation Composition for photo imaging
EP0501357A1 (en) * 1991-02-25 1992-09-02 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same
US5116459A (en) * 1991-03-06 1992-05-26 International Business Machines Corporation Processes for electrically conductive decals filled with organic insulator material
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
US5699613A (en) * 1995-09-25 1997-12-23 International Business Machines Corporation Fine dimension stacked vias for a multiple layer circuit board structure
US5882532A (en) * 1996-05-31 1999-03-16 Hewlett-Packard Company Fabrication of single-crystal silicon structures using sacrificial-layer wafer bonding
WO1999005717A1 (en) * 1997-07-22 1999-02-04 Commissariat A L'energie Atomique Method for making an anisotropic conductive coating with conductive inserts
JPH11163022A (en) * 1997-11-28 1999-06-18 Sony Corp Semiconductor and manufacture of the same and electronic equipment
US20010005050A1 (en) * 1997-11-28 2001-06-28 Kenji Ohsawa Semiconductor device, method making the same, and electronic device using the same

Also Published As

Publication number Publication date
WO2002037565A2 (en) 2002-05-10
AU2002220022A1 (en) 2002-05-15

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