WO2002007216B1 - Fabrication of electronic circuit elements - Google Patents

Fabrication of electronic circuit elements

Info

Publication number
WO2002007216B1
WO2002007216B1 PCT/US2001/022091 US0122091W WO0207216B1 WO 2002007216 B1 WO2002007216 B1 WO 2002007216B1 US 0122091 W US0122091 W US 0122091W WO 0207216 B1 WO0207216 B1 WO 0207216B1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
data line
electrode
thin
silicon layer
Prior art date
Application number
PCT/US2001/022091
Other languages
French (fr)
Other versions
WO2002007216A3 (en
WO2002007216A2 (en
Inventor
Peter T Kazlas
Michael G Hack
Paul S Drzaic
Guy M Danner
Karl R Amudson
Original Assignee
E Ink Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by E Ink Corp filed Critical E Ink Corp
Priority to AU2002222969A priority Critical patent/AU2002222969A1/en
Publication of WO2002007216A2 publication Critical patent/WO2002007216A2/en
Publication of WO2002007216A3 publication Critical patent/WO2002007216A3/en
Publication of WO2002007216B1 publication Critical patent/WO2002007216B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A thin-film transistor array comprises at least first and second transistors. Each of the first and second transistors include a shared silicon layer, i.e., an active layer. The shared semiconductor layer extends continuously between the first and second transistors, and includes a concentration of dopant that increases a resistivity of the semiconductor layer and reduces a leakage current through the semiconductor layer while permitting functioning of the transistor array.

Claims

60
AMENDED CLAIMS
[received by the International Bureau on 24 April 2002 (24.04.02); new claims 36-65 added; remaining claims unchanged (6 pages)] 36. A thin-film transistor array comprising at least first and second transistors, each of the first and second transistors comprising: a shared silicon layer having a thickness less than 40nm and extending continuously between the first and second transistors; a source electrode in direct contact with the silicon layer; a drain electrode spaced from the source electrode and in direct contact with the silicon layer; and a gate electrode disposed adjacent to the silicon layer . 37. The thin-film transistor array of claim 1 wherein the silicon layer consists of unpatterned silicon. 38. The thin-film transistor array of claim 2 wherein the silicon layer consists of amorphous silicon. 39. The thin-film transistor array of claim 1 wherein the silicon layer is undoped. 40. The thin-film transistor array of claim 1 wherein the first transistor is a bottom gate transistor. 41. The thin-film transistor array of claim 1 wherein the first transistor is a top gate transistor. 42. The thin-film transistor array of claim 1, the first transistor further comprising a first pixel electrode of an electronic display, the first pixel electrode in communication with the source electrode of the first transistor, and the drain electrode of the first transistor is in communication with a first data line of the electronic display. 61
43. The thin-film transistor array of claim 7 wherein a distance between the first pixel electrode and the first data line is selected to provide an acceptable leakage current between the first pixel electrode and the first data line. 44. The thin-film transistor array of claim 7 wherein a distance between the first transistor and the second transistor is selected to provide an acceptable leakage current between the first data line and the second data line. 45. The thin-film transistor. array of claim 9 wherein at least one of the first data line, the second data line, the first transistor and the first pixel electrode have a geometry selected to provide an acceptable leakage between the first data line and the second data line. 46. An electronic display comprising: a display medium; a first pixel electrode and a second pixel electrode provided adjacent to the display medium; and a first thin-film transistor and a second thin-film transistor in respective electrical communication with the first pixel electrode and the second pixel electrode, and comprising a shared continuous amorphous silicon layer that has a thickness less than 40nm and provides channels for the first thin- film transistor and the second thin-film transistor. 47. The electronic display of claim 11 wherein the display medium is electrophoretiσ . 48. The electronic display of claim 12 wherein the electrophoretic medium comprises at least one type of 62
particle and a suspending fluid. 49. The electronic display of claim 12 wherein the electrophoretic medium is encapsulated. 50. The electronic display of claim 11 further comprising a light blocking layer provided adjacent to the silicon layer. 51. The electronic display of claim 11 further comprising a first data line in communication with the first transistor and a second data line in communication with the second transistor, wherein a distance between the first transistor and the second transistor is selected to provide an acceptable leakage between the first data line and the second data line. 52. The electronic display of claim 16 wherein a distance between the first pixel electrode and the first data line is selected to provide an acceptable leakage between the first pixel electrode and the first data line. 53. The electronic display of claim 11 wherein the first transistor comprises a gate electrode, a source electrode and a drain electrode and the gate electrode and one of the source electrode and the drain electrode form a capacitor. 54. A method of manufacturing an array of thin-film transistors comprising at least a first transistor and a second transistor, the method comprising the steps of: providing a substrate; forming adjacent to the substrate an unpatterned silicon layer having a thickness less than 40nm; forming at least one patterned drain electrode for each of the transistors, the drain electrodes in direct contact with the unpatterned silicon layer; forming at least one patterned source electrode for each of the transistors, the source electrodes in direct contact with the unpatterned silicon layer; and forming at least one gate electrode for each of the transistors, the gate electrode disposed adjacent to the unpatterned silicon layer. 55. The method of claim 19 further comprising the step of selecting a spacing between the first transistor and the second transistor to provide an acceptable leakage current between the first transistor and the second transistor. 56. The method of claim 19 further comprising the step of forming a dielectric layer adjacent to the at least one gate electrode . 57. The method of claim 19 wherein the step of providing a substrate comprises unwinding the substrate from a first roll and winding the substrate onto a second roll. 58. The method of claim 21 wherein the steps of forming the dielectric layer, forming the unpatterned silicon layer and forming the source and drain electrodes occur at least partially during one visit of the substrate inside a single deposition chamber. 59. The method of claim 19 further comprising the steps of: providing a first pixel • electrode of an electronic display in communication with the source electrode of 64
the first transistor; and providing a first data line of the electronic display in communication with the drain electrode of the first transistor. 60. The method of claim 24 further comprising the steps of: providing a second pixel electrode of an electronic display in communication with the source electrode of the second transistor; providing a second data line of the electronic display in communication with the drain electrode of the second transistor; and selecting a geometry of at least one of: (i) the first data line; (ii) the second data line; (iii) the first transistor and (iv) the first pixel electrode, to provide an acceptable leakage current between the first data line and the second data line. 61. The method of claim 24 further comprising the step of selecting a distance between the first pixel electrode and the first data line to provide an acceptable leakage between the first pixel electrode and the first data line. 62. The method of claim 24 further comprising the steps of : providing a second pixel electrode of an electronic display in communication with the source electrode of the second transistor; providing a second data line of the electronic display in communication with the drain electrode of the second transistor; and selecting at least one of: (i) a distance between the source electrode of the first transistor and the drain electrode of the first transistor; (ii) a channel width of the first transistor; (iii) a dimension of the first pixel electrode; (iv) a distance between the first data line and the first transistor and (v) a distance 65
between the first pixel electrode and the second data line, to provide an acceptable leakage current between the first data line and the second data line. 63. The method of claim 19 wherein the step of forming the unpatterned silicon layer comprises forming an amorphous silicon film. 64. The method of claim 28 wherein the step of forming the unpatterned silicon layer comprises forming an intrinsic amorphous silicon film. 65. The method of claim 19 wherein the steps of forming include mask steps consisting of a first mask step and a second mask step, wherein the step of forming at least one gate electrode comprises the first mask step and the steps of forming at least one patterned drain electrode and forming at least one patterned source electrode share the second mask step.
PCT/US2001/022091 2000-07-14 2001-07-13 Fabrication of electronic circuit elements WO2002007216A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002222969A AU2002222969A1 (en) 2000-07-14 2001-07-13 Fabrication of electronic circuit elements

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US21849000P 2000-07-14 2000-07-14
US60/218,490 2000-07-14
US09/904,109 2001-07-12

Publications (3)

Publication Number Publication Date
WO2002007216A2 WO2002007216A2 (en) 2002-01-24
WO2002007216A3 WO2002007216A3 (en) 2002-05-10
WO2002007216B1 true WO2002007216B1 (en) 2002-07-25

Family

ID=22815333

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/022091 WO2002007216A2 (en) 2000-07-14 2001-07-13 Fabrication of electronic circuit elements

Country Status (3)

Country Link
US (2) US6683333B2 (en)
AU (1) AU2002222969A1 (en)
WO (1) WO2002007216A2 (en)

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