WO2002005341A1 - Method of manufacturing power silicon transistor - Google Patents

Method of manufacturing power silicon transistor Download PDF

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Publication number
WO2002005341A1
WO2002005341A1 PCT/AM2001/000002 AM0100002W WO0205341A1 WO 2002005341 A1 WO2002005341 A1 WO 2002005341A1 AM 0100002 W AM0100002 W AM 0100002W WO 0205341 A1 WO0205341 A1 WO 0205341A1
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WO
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Prior art keywords
substrate
silicon
layer
doped
manufacturing
Prior art date
Application number
PCT/AM2001/000002
Other languages
French (fr)
Inventor
Gagik Ayvazyan
Armen Shaboyan
Original Assignee
Gagik Ayvazyan
Armen Shaboyan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gagik Ayvazyan, Armen Shaboyan filed Critical Gagik Ayvazyan
Priority to AU2001228168A priority Critical patent/AU2001228168A1/en
Publication of WO2002005341A1 publication Critical patent/WO2002005341A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66295—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors

Definitions

  • the present invention relates to power semiconductor techniques and may be used for manufacturing of power silicon transistors.
  • power silicon transistors are manufactured on the base of silicon structure with N - N + collector junction, P "1" base and N + emitter regions.
  • the forming of their base and emitter regions is realized by successive high temperature ( 1 150 -1220°C) diffusion of acceptor and donor impurity into a comparatively higher depth (respectively 10 -15 and 35-45 ⁇ m).
  • Typical impurities employed are preferabl) aluminum, boron and gallium as acceptor one, and phosphorus - as donor one.
  • N + layer simultaneously is doped by the impurity with "compensating" atomic radius (for example, phosphorus and germanium). Germanium compensates for the atomic radius mismatch and also decreases of mechanical stress and dislocation on the interface of N - N + structures.
  • "compensating" atomic radius for example, phosphorus and germanium. Germanium compensates for the atomic radius mismatch and also decreases of mechanical stress and dislocation on the interface of N - N + structures.
  • the disadvantage of this method is high density of diffusion-induced crystallographic defects into active regions of transistors. As a result electrophysical parameters of transistor structures is impaired.
  • the other disadvantage of method is the low capability of transistors to second-breakdown, which is stipulated by an abrupt doping profile of N - N " collector junction, as it described in V. A. Belikov, V.A. Rudsky. and V.V. Togatov. Investigation of the impact of N - N junction doping " profile on capability of power transistors to second-breakdown // Electrotechnika, 7, 1991, p. 61 (in Russian). Provision of graded profile by creating of buffer epitaxial layer on the interface of N - N + collector junction, reduced the method productivity. This has been described in US Patent 5872028. 9/1996, Method of forming power semiconductor devices with controllable buffer. J.Yedinak et al.
  • N + epitaxial layer prolonged (10-14 hours) and high temperature (1200-1250°C) treatment of N - N + structures is carried out. It is supposed that there is an auto-doped of donor impurity from highly doped N ⁇ epitaxial layer to lightly doped N " silicon substrate. As a result is provided graded doping profile of N - N collector junction and therefore is increased the capability of transistors to second- breakdown.
  • the disadvantage of this method is availability of additional prolonged and high temperature treatment and high density of diffusion-induced defects (dislocations, dislocation networks, precipitates, dislocation half-loops, misfit dislocations etc.). As a result electrophysical parameters of transistor structures are impaired (for example, is decreased lifetime of minority charge carrier). Disclosure of Invention
  • the object of this invention is the improvement of electrophysical parameters of transistor structures and increase of the method productivity.
  • the porous silicon layer with the density of 1.4 + 1.6 g/sm J and depth of 10-15 ⁇ m is formed on the backside of N " silicon substrate by anodic etching before growing of the epitaxial layer.
  • PS layers are anodicly produced on the silicon samples in an electrolyte containing hydrofluoric acid. Such technology is described in Y.S. Tsou, Y. Xiao, and CA. Moore. Porous silicon. World Sci. Publ., NY. 1994, 412 p.
  • the density and depth of PS layer is proportional to the concentration of the electrolyte, current density, anodic voltage and time.
  • the high diffusion rate of impurities in PS provided necessary graded doping profile of N - N collector junction during comparative short time and low temperature treatment (for example, in process of forming P + base and N + emitter regions).
  • the auto-doped of donor impurity from highly- doped N + epitaxial layer to lightly doped N " silicon substrate can be fully combined with the above-mentioned processing. In this case there is no need to carry out additional prolonged and high temperature treatment, that will result in the increase of the method productivity. It is significant that the formation process of PS does not requiring much time and energy expenditures.
  • PS layer depth h 10-15 ⁇ m, are necessary and sufficient for providing the graded doping profile of N - N + collector junction in the process of forming base and emitter regions. This is described in V. A. Belikov, V.A. Ruds y. and V.V. Togatov. Investigation of the impact of N - N + junction doping profile on capability of power transistors to second-breakdown // Electrotechnika, 7, 1991, p. 61 (in Russian). Brief Description of Drawings
  • FIGS. 1-5 are schematic sectional view for explaining the steps of a method manufacturing of a power silicon transistor in accordance with our invention. Best Mode for Carrying Out the Invention
  • the substrate 11 of lightly doped N " -type silicon semiconductor material typically 400 ⁇ m thick, having a resistivity 60 Om.cm and a number of defects 12 within crystalline lattice is provided.
  • the substrate is provided with flat, smooth opposing top and back surfaces.
  • the PS layer 21 was formed on the backside of N " silicon substrate by anodic etching using an electrolyte containing hydrofluoric acid.
  • the substrate is first inserted within a suitable holding device and then immersed within the electrolyte. During immersion the substrate acts as an anode and a conductive member, which is likewise inserted within the electrolyte but is not readily dissoluble therein acts as a cathode.
  • anodic voltage is applied there between a reaction takes place causing gradual deep pore formation on the side wafer exposed to the electrolyte.
  • anodic etching was realized on the holding device for anodic treatment with the help of potentiostat.
  • Solution of 48% hydrofluoric acid and ethyleneglycol in proportion 1 :3 as an electrolyte was used.
  • the amperemeter and voltmeter of the potentiostat ensured the regime of anodic etching, and consequently the required density and the depth of PS layer.
  • FIG. 3 the growth of high-doped N + layer 31 on the PS layer was implemented on the vertical reactor of epitaxial setup.
  • the thickness of epitaxial layer was 180 ⁇ m, and a resistivity - 0.01 Om cm.
  • the total thickness of substrate 41 was 300 ⁇ m after one-sided lapping and polishing of the substrate. Then follow conventional steps for forming an active device within the substrate 41.
  • the P + base 51 was formed at temperature of 1220°C by successive diffusion of gallium and boron, and N + emitter 52 - by diffusion of phosphorus at the temperature of 1150°C.
  • the final depth of base region was 43.0 ⁇ 3.0 ⁇ m, and 15.0 ⁇ 0.5 ⁇ m for emitter region.
  • contacts are made to the emitter, base and collector regions. Typically, contacts to the emitter and base regions are made from the top surface and to the collector region from the back surface.
  • the lifetime of minority charge carriers was controlled in the manufacturing process of power transistor structures and the assessments of operating parameters of finished transistors was carried out.
  • the lifetime of minority charge carriers was independent from the depth of PS layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Weting (AREA)

Abstract

The present invention relates to power semiconductor techniques and may be used for manufacturing of power silicon transistors. The method comprises steps providing the lightly doped N- silicon substrate, formation the porous silicon layer on the backside of substrate by anodic etching, and growing of the highly doped N+ epitaxial layer on the porous silicon layer.

Description

METHOD OF MANUFACTURING POWER SILICON TRANSISTOR
Technical Field
The present invention relates to power semiconductor techniques and may be used for manufacturing of power silicon transistors. Background Art
In accordance with conventional prior art techniques power silicon transistors are manufactured on the base of silicon structure with N - N+ collector junction, P"1" base and N+ emitter regions. For providing optimal dynamic and static parameters of transistors, the forming of their base and emitter regions is realized by successive high temperature ( 1 150 -1220°C) diffusion of acceptor and donor impurity into a comparatively higher depth (respectively 10 -15 and 35-45 μm). Typical impurities employed are preferabl) aluminum, boron and gallium as acceptor one, and phosphorus - as donor one.
There is a method of manufacturing of power silicon transistor, which includes making of silicon N - N+ structures by growing epitaxial layer on silicon substrate, forming P " base and N+ emitter regions by successive diffusion of acceptor and donor impurity. This has been described in US Patent 5553566, 9/1996, Method of eliminating dislocations and lowering lattice strain for highly doped N+ substrates, H. Chiou et al.
According in this method N+ layer simultaneously is doped by the impurity with "compensating" atomic radius (for example, phosphorus and germanium). Germanium compensates for the atomic radius mismatch and also decreases of mechanical stress and dislocation on the interface of N - N+ structures.
The disadvantage of this method is high density of diffusion-induced crystallographic defects into active regions of transistors. As a result electrophysical parameters of transistor structures is impaired. The other disadvantage of method is the low capability of transistors to second-breakdown, which is stipulated by an abrupt doping profile of N - N " collector junction, as it described in V. A. Belikov, V.A. Rudsky. and V.V. Togatov. Investigation of the impact of N - N junction doping" profile on capability of power transistors to second-breakdown // Electrotechnika, 7, 1991, p. 61 (in Russian). Provision of graded profile by creating of buffer epitaxial layer on the interface of N - N + collector junction, reduced the method productivity. This has been described in US Patent 5872028. 9/1996, Method of forming power semiconductor devices with controllable buffer. J.Yedinak et al.
One previously known method of manufacturing power silicon transistors was taught by A.A.Bogomyakow, J. N. Duchenko and V.A. Potapchuk, in SU Patent 1 1 18237, which was issued on May 30, 1983 (in Russian). This method includes providing of the lightly doped Ν" silicon substrate having a top and back surface, growing of the highly doped Ν~ epitaxial layer on the backside of N" silicon substrate, one-sided lapping and polishing of the substrate, forming P base and N+ emitter regions by successive diffusion acceptor and donor impurities from the top surface side of the substrate.
According to the present invention, after growing of N+ epitaxial layer prolonged (10-14 hours) and high temperature (1200-1250°C) treatment of N - N+ structures is carried out. It is supposed that there is an auto-doped of donor impurity from highly doped N~ epitaxial layer to lightly doped N" silicon substrate. As a result is provided graded doping profile of N - N collector junction and therefore is increased the capability of transistors to second- breakdown.
The disadvantage of this method is availability of additional prolonged and high temperature treatment and high density of diffusion-induced defects (dislocations, dislocation networks, precipitates, dislocation half-loops, misfit dislocations etc.). As a result electrophysical parameters of transistor structures are impaired (for example, is decreased lifetime of minority charge carrier). Disclosure of Invention
Therefore, the object of this invention is the improvement of electrophysical parameters of transistor structures and increase of the method productivity.
According to the present invention, as differentiated from the patent by A.A.Bogomyakow, et al., the porous silicon layer with the density of 1.4 + 1.6 g/smJ and depth of 10-15 μm is formed on the backside of N" silicon substrate by anodic etching before growing of the epitaxial layer.
Invention is explained as follows. Porous silicon (PS) layers are anodicly produced on the silicon samples in an electrolyte containing hydrofluoric acid. Such technology is described in Y.S. Tsou, Y. Xiao, and CA. Moore. Porous silicon. World Sci. Publ., NY. 1994, 412 p. The density and depth of PS layer is proportional to the concentration of the electrolyte, current density, anodic voltage and time. The high diffusion rate of impurities in PS provided necessary graded doping profile of N - N collector junction during comparative short time and low temperature treatment (for example, in process of forming P+ base and N+ emitter regions). Therefore, having the necessary density and depth of PS layer, the auto-doped of donor impurity from highly- doped N+ epitaxial layer to lightly doped N" silicon substrate can be fully combined with the above-mentioned processing. In this case there is no need to carry out additional prolonged and high temperature treatment, that will result in the increase of the method productivity. It is significant that the formation process of PS does not requiring much time and energy expenditures.
Furthermore, during of thermo-diffusion treatment penetration and accumulation of initial and diffusion-induced defects take place in the PS layer (defects, gettering), as it described in RU Patent 2120682, 4/1997, Method of producing silicon substrate, V. Skupov et al. (in Russian). As a result, the density of crystallographic defects in the active regions of transistors is decreasing that leads to the improvement of their electrophysical parameters.
The proposed meanings of density of PS layer p = 1.4 ÷ 1.6 g/sm3 have the following grounds. The auto-doped rate of donor impurity and the efficiency of gettering sharply is decreased when p > 1.6 g/sm . Large mechanical stress can spring up in the PS layer in the case of p < 1.4 g/sm3, which in turn are cause of generating additional crystallographic defects. This has been described in an article by Ayvazyan G.E. Anisotropic warpage of wafers with anodized porous silicon layers//Phys. Stat. Sol. (a), 175, N2, R7-R8, 1999.
The proposed meanings of PS layer depth h = 10-15 μm, are necessary and sufficient for providing the graded doping profile of N - N+ collector junction in the process of forming base and emitter regions. This is described in V. A. Belikov, V.A. Ruds y. and V.V. Togatov. Investigation of the impact of N - N + junction doping profile on capability of power transistors to second-breakdown // Electrotechnika, 7, 1991, p. 61 (in Russian). Brief Description of Drawings
The foregoing, and other objects, features and advantages of the invention will be apparent from the following, more particular description of the preferred embodiments, as illustrated in the accompanying drawing, wherein:
FIGS. 1-5 are schematic sectional view for explaining the steps of a method manufacturing of a power silicon transistor in accordance with our invention. Best Mode for Carrying Out the Invention
Referring now to the drawing there is disclosed method manufacturing of a power silicon transistor in accordance with the teachings of the present invention. In FIG. 1 the substrate 11 of lightly doped N"-type silicon semiconductor material, typically 400 μm thick, having a resistivity 60 Om.cm and a number of defects 12 within crystalline lattice is provided. The substrate is provided with flat, smooth opposing top and back surfaces.
The manufacture of transistor structures on one group of substrates was carried out by a known method and on the other group by a present invention.
The manufacture of transistor structures by a present invention was carried out as follows. As shown in FIG. 2, the PS layer 21 was formed on the backside of N" silicon substrate by anodic etching using an electrolyte containing hydrofluoric acid. Typically the substrate is first inserted within a suitable holding device and then immersed within the electrolyte. During immersion the substrate acts as an anode and a conductive member, which is likewise inserted within the electrolyte but is not readily dissoluble therein acts as a cathode. When anodic voltage is applied there between a reaction takes place causing gradual deep pore formation on the side wafer exposed to the electrolyte.
In the present example anodic etching was realized on the holding device for anodic treatment with the help of potentiostat. Solution of 48% hydrofluoric acid and ethyleneglycol in proportion 1 :3 as an electrolyte was used. The amperemeter and voltmeter of the potentiostat ensured the regime of anodic etching, and consequently the required density and the depth of PS layer.
In the next operation, FIG. 3, the growth of high-doped N+ layer 31 on the PS layer was implemented on the vertical reactor of epitaxial setup. The thickness of epitaxial layer was 180 μm, and a resistivity - 0.01 Om cm.
As shown in FIG. 4, the total thickness of substrate 41 was 300 μm after one-sided lapping and polishing of the substrate. Then follow conventional steps for forming an active device within the substrate 41.
In the next operation, FIG. 5, the P+ base 51 was formed at temperature of 1220°C by successive diffusion of gallium and boron, and N+ emitter 52 - by diffusion of phosphorus at the temperature of 1150°C. The final depth of base region was 43.0 ± 3.0 μm, and 15.0 ± 0.5 μm for emitter region. There was a simultaneous the auto-doped of donor impurity from highly doped N+ epitaxial layer to lightly doped N" silicon substrate and gettering of initial and diffusion-induced defects in N PS layer. In subsequent operations (not shown), contacts are made to the emitter, base and collector regions. Typically, contacts to the emitter and base regions are made from the top surface and to the collector region from the back surface.
The lifetime of minority charge carriers was controlled in the manufacturing process of power transistor structures and the assessments of operating parameters of finished transistors was carried out. The lifetime of minority charge carriers was less than 10 μs in case p < 1.4 g/sm3 and p > 1.6 g/sm3, and 15-45 μs in case p = 1.4÷1.6 g/cm3. The lifetime of minority charge carriers was independent from the depth of PS layer.
The maximum second-breakdown voltage of transistor was observed in depth h = 10-1 5 μm of the PS layer. The decreasing of depth led to the voltage reduction. The second- breakdown voltage remained unchanged at h >15 μm.
The assessments of operating parameters of transistors, manufactured in different ways evidenced that the proposed method enables to increase voltage of collector emitter and second-breakdown voltage of devices 1.2-1.3 times. Furthermore, productivity will be increased, since prolonged and high temperature treatment are replaced with the formation of PS layer not requiring much time and energy expenditures.
Thus far a specific method for manufacturing of a power silicon transistor using an N - N+ structure has been described. It will be appreciated, however, that the teachings of the present invention may be put to use when making other type devices. Numerous changes can be made without parting from the spirit and scope of the invention.

Claims

C L A I M S
A method of manufacturing of power silicon transistors comprises the steps of: providing a lightly doped N" silicon substrate having a top and back surface; •forming a porous silicon layer with the density of 1.4 + 1.6 g/sm3 and depth of 10- 15μm on the backside of N" silicon substrate by anodic etching; growing of a highly doped N+ epitaxial layer on the porous silicon layer; one-sided lapping and polishing of substrate: forming a P+ base and N+ emitter regions by successive diffusion of acceptor and donor impurities from the top surface side of substrate.
PCT/AM2001/000002 2000-07-10 2001-01-10 Method of manufacturing power silicon transistor WO2002005341A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100017067A1 (en) * 2007-01-29 2010-01-21 Josef Kolatschek Method and control unit for triggering passenger protection means
US9415712B2 (en) 2008-12-21 2016-08-16 Gentherm Gmbh Ventilation system
US9440567B2 (en) 2005-08-19 2016-09-13 Gentherm Gmbh Automotive vehicle seat insert

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3929529A (en) * 1974-12-09 1975-12-30 Ibm Method for gettering contaminants in monocrystalline silicon
SU1827143A3 (en) * 1991-04-18 1996-06-27 Товарищество с ограниченной ответственностью "КМК" Method of manufacture of power silicon transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3929529A (en) * 1974-12-09 1975-12-30 Ibm Method for gettering contaminants in monocrystalline silicon
SU1827143A3 (en) * 1991-04-18 1996-06-27 Товарищество с ограниченной ответственностью "КМК" Method of manufacture of power silicon transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9440567B2 (en) 2005-08-19 2016-09-13 Gentherm Gmbh Automotive vehicle seat insert
US20100017067A1 (en) * 2007-01-29 2010-01-21 Josef Kolatschek Method and control unit for triggering passenger protection means
US9415712B2 (en) 2008-12-21 2016-08-16 Gentherm Gmbh Ventilation system

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