WO2001089122A3 - Method and system for distributed clock failure protection in a packet switched network - Google Patents

Method and system for distributed clock failure protection in a packet switched network Download PDF

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Publication number
WO2001089122A3
WO2001089122A3 PCT/US2001/016238 US0116238W WO0189122A3 WO 2001089122 A3 WO2001089122 A3 WO 2001089122A3 US 0116238 W US0116238 W US 0116238W WO 0189122 A3 WO0189122 A3 WO 0189122A3
Authority
WO
WIPO (PCT)
Prior art keywords
clocking information
network device
failure protection
hardware
failure
Prior art date
Application number
PCT/US2001/016238
Other languages
French (fr)
Other versions
WO2001089122A2 (en
Inventor
Daniel Bernier
Deborah Edin
Stewart Kenly
Original Assignee
Enterasys Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Enterasys Networks Inc filed Critical Enterasys Networks Inc
Priority to AU2001263303A priority Critical patent/AU2001263303A1/en
Publication of WO2001089122A2 publication Critical patent/WO2001089122A2/en
Publication of WO2001089122A3 publication Critical patent/WO2001089122A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node

Abstract

Protection from a distributed clock failure in a packet switched network device involves monitoring primary clocking information that is received from an input port of the network device, distributing the clocking information to an output port for use in synchronous transmissions, and supplying backup clocking information from within the packet switched network device to the output port if the primary clocking information fails. In an embodiment, the integrity of the primary clocking information is directly monitored in hardware and the backup clocking information is provided by a local clock source that is located within the network device. If a failure in the primary clocking information is detected, the backup clocking information is supplied to the output port from the local clock source. Because the integrity of the primary clocking information is monitored in hardware and because the clock switching is hardware triggered, a clock failure can be identified and corrected in a relatively short period of time, thereby minimizing packet loss during clock failures. In an embodiment, the hardware based failure protection mechanism provides failure protection on a single switch module. In an embodiment, the hardware based failure protection mechanism provides failure protection to a network device that includes multiple switch modules. In an embodiment, a firmware based failure protection mechanism can be programmed to provide a secondary clock from sources other than a local clock source.
PCT/US2001/016238 2000-05-18 2001-05-18 Method and system for distributed clock failure protection in a packet switched network WO2001089122A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001263303A AU2001263303A1 (en) 2000-05-18 2001-05-18 Method and system for distributed clock failure protection in a packet switched network

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/573,327 US6754171B1 (en) 2000-05-18 2000-05-18 Method and system for distributed clock failure protection in a packet switched network
US09/573,327 2000-05-18

Publications (2)

Publication Number Publication Date
WO2001089122A2 WO2001089122A2 (en) 2001-11-22
WO2001089122A3 true WO2001089122A3 (en) 2003-08-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/016238 WO2001089122A2 (en) 2000-05-18 2001-05-18 Method and system for distributed clock failure protection in a packet switched network

Country Status (3)

Country Link
US (1) US6754171B1 (en)
AU (1) AU2001263303A1 (en)
WO (1) WO2001089122A2 (en)

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US8155091B2 (en) * 2003-08-15 2012-04-10 Thomson Licensing Broadcast router with multiple expansion capabilities
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US7362739B2 (en) * 2004-06-22 2008-04-22 Intel Corporation Methods and apparatuses for detecting clock failure and establishing an alternate clock lane
US7562247B2 (en) * 2006-05-16 2009-07-14 International Business Machines Corporation Providing independent clock failover for scalable blade servers
US20080046774A1 (en) * 2006-08-15 2008-02-21 Tyan Computer Corporation Blade Clustering System with SMP Capability and Redundant Clock Distribution Architecture Thereof
US7899894B2 (en) * 2006-08-30 2011-03-01 International Business Machines Corporation Coordinated timing network configuration parameter update procedure
US9112626B2 (en) * 2007-01-31 2015-08-18 International Business Machines Corporation Employing configuration information to determine the role of a server in a coordinated timing network
US8738792B2 (en) * 2007-01-31 2014-05-27 International Business Machines Corporation Server time protocol messages and methods
US7689718B2 (en) 2007-01-31 2010-03-30 International Business Machines Corporation Channel subsystem server time protocol commands and system therefor
US7823004B2 (en) * 2007-08-01 2010-10-26 Hewlett-Packard Development Company, L.P. Clock source selection for modular computer system as a function of modulo difference
US8332680B2 (en) * 2007-08-13 2012-12-11 Rambus Inc. Methods and systems for operating memory in two modes
JP4982304B2 (en) * 2007-09-04 2012-07-25 株式会社日立製作所 Storage system that understands the occurrence of power failure
US20090109840A1 (en) * 2007-10-31 2009-04-30 Hallse Brian L Fault-resistant digital-content-stream AV packet switch
US8416811B2 (en) * 2008-04-10 2013-04-09 International Business Machines Corporation Coordinated timing network having servers of different capabilities
US7925916B2 (en) 2008-04-10 2011-04-12 International Business Machines Corporation Failsafe recovery facility in a coordinated timing network
US7873862B2 (en) * 2008-10-21 2011-01-18 International Business Machines Corporation Maintaining a primary time server as the current time server in response to failure of time code receivers of the primary time server
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US9608751B2 (en) * 2015-03-18 2017-03-28 Accedian Networks Inc. Simplified synchronized Ethernet implementation

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Publication number Publication date
AU2001263303A1 (en) 2001-11-26
US6754171B1 (en) 2004-06-22
WO2001089122A2 (en) 2001-11-22

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