WO2001086812A3 - Fpga lookup table with high speed read decoder - Google Patents
Fpga lookup table with high speed read decoder Download PDFInfo
- Publication number
- WO2001086812A3 WO2001086812A3 PCT/US2001/011308 US0111308W WO0186812A3 WO 2001086812 A3 WO2001086812 A3 WO 2001086812A3 US 0111308 W US0111308 W US 0111308W WO 0186812 A3 WO0186812 A3 WO 0186812A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- lut
- decoder
- lookup table
- read decoder
- high speed
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01924792A EP1287615B1 (en) | 2000-05-05 | 2001-04-06 | Fpga lookup table with high speed read decoder |
DE60131078T DE60131078T2 (en) | 2000-05-05 | 2001-04-06 | FOLLOW-UP TABLE FOR A USER PROGRAMMABLE GATE FIELD WITH A QUICK READ ENCODER |
CA2411650A CA2411650C (en) | 2000-05-05 | 2001-04-06 | Fpga lookup table with high speed read decoder |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/566,052 US6529040B1 (en) | 2000-05-05 | 2000-05-05 | FPGA lookup table with speed read decoder |
US09/566,052 | 2000-05-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001086812A2 WO2001086812A2 (en) | 2001-11-15 |
WO2001086812A3 true WO2001086812A3 (en) | 2002-06-27 |
Family
ID=24261267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/011308 WO2001086812A2 (en) | 2000-05-05 | 2001-04-06 | Fpga lookup table with high speed read decoder |
Country Status (5)
Country | Link |
---|---|
US (2) | US6529040B1 (en) |
EP (2) | EP1287615B1 (en) |
CA (2) | CA2411650C (en) |
DE (2) | DE60131078T2 (en) |
WO (1) | WO2001086812A2 (en) |
Families Citing this family (120)
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FR2729528A1 (en) * | 1995-01-13 | 1996-07-19 | Suisse Electronique Microtech | Digital multiplexer circuit e.g. for clock control system |
JPH0983348A (en) * | 1995-09-14 | 1997-03-28 | Hitachi Ltd | Variable logic circuit |
KR0173955B1 (en) * | 1996-02-01 | 1999-04-01 | 김광호 | Energy-saving pass transistor logic circuit and full adder using the same |
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JP3701781B2 (en) * | 1997-11-28 | 2005-10-05 | 株式会社ルネサステクノロジ | Logic circuit and its creation method |
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2000
- 2000-05-05 US US09/566,052 patent/US6529040B1/en not_active Expired - Lifetime
-
2001
- 2001-04-06 WO PCT/US2001/011308 patent/WO2001086812A2/en active IP Right Grant
- 2001-04-06 EP EP01924792A patent/EP1287615B1/en not_active Expired - Lifetime
- 2001-04-06 DE DE60131078T patent/DE60131078T2/en not_active Expired - Lifetime
- 2001-04-06 DE DE60136974T patent/DE60136974D1/en not_active Expired - Lifetime
- 2001-04-06 CA CA2411650A patent/CA2411650C/en not_active Expired - Lifetime
- 2001-04-06 CA CA2676132A patent/CA2676132C/en not_active Expired - Lifetime
- 2001-04-06 EP EP04017938A patent/EP1489745B1/en not_active Expired - Lifetime
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2002
- 2002-11-15 US US10/295,713 patent/US6621296B2/en not_active Expired - Lifetime
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US5889413A (en) * | 1996-11-22 | 1999-03-30 | Xilinx, Inc. | Lookup tables which double as shift registers |
US5764564A (en) * | 1997-03-11 | 1998-06-09 | Xilinx, Inc. | Write-assisted memory cell and method of operating same |
Also Published As
Publication number | Publication date |
---|---|
EP1489745B1 (en) | 2008-12-10 |
CA2676132A1 (en) | 2001-11-15 |
US20030071653A1 (en) | 2003-04-17 |
CA2411650C (en) | 2012-11-27 |
EP1287615A2 (en) | 2003-03-05 |
EP1489745A2 (en) | 2004-12-22 |
WO2001086812A2 (en) | 2001-11-15 |
EP1287615B1 (en) | 2007-10-24 |
DE60131078T2 (en) | 2008-08-07 |
US6621296B2 (en) | 2003-09-16 |
DE60131078D1 (en) | 2007-12-06 |
CA2676132C (en) | 2012-01-03 |
DE60136974D1 (en) | 2009-01-22 |
CA2411650A1 (en) | 2001-11-15 |
EP1489745A3 (en) | 2006-06-28 |
US6529040B1 (en) | 2003-03-04 |
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