WO2001035283A3 - System for performing parallel circuit simulation in a high level description language - Google Patents

Abstract

HDL circuit designs are simulated in parallel by running multiple instances of a stand alone HDL simulation program. Each instance simulates a sub-block of a larger HDL design within a test bench, and the separate test benches communicate port values and clock synchronization information to create a parallel simulation of the larger HDL design. Preferably software parses the HDL description the larger circuit so it can determine and then display the hierarchy of sub-blocks within that design. A user can then select which sub-blocks are to be separately simulated. The system then parses the HDL description of each such sub-block to find its input and output ports. The system generates a test bench to drive the simulation of each separately simulated sub-block. Each such test bench includes internal ports corresponding to, and connected to, the external ports of its sub-block, and instructions for communicating the values of those ports and clock synchronization information with the simulation of other sub-blocks. Each such test bench can have two parts, a test bench written in HDL; and a non-HDL parallelization program. These two parts can communicate port values and synchronization information using an language interface, such as FLI or PLI. The parallelization code of different simulations can communicate with each other through a master program which synchronizes the operation of all the simulations. In many embodiments the simulation program is a serial VHDL or Verilog simulation program purchased from one vendor and the parallelization code is obtained from a separate source.