WO2001016741A3 - Semaphore control of shared-memory - Google Patents

Semaphore control of shared-memory Download PDF

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Publication number
WO2001016741A3
WO2001016741A3 PCT/US2000/024217 US0024217W WO0116741A3 WO 2001016741 A3 WO2001016741 A3 WO 2001016741A3 US 0024217 W US0024217 W US 0024217W WO 0116741 A3 WO0116741 A3 WO 0116741A3
Authority
WO
WIPO (PCT)
Prior art keywords
shared
processing nodes
shared memory
pointer
systems
Prior art date
Application number
PCT/US2000/024217
Other languages
French (fr)
Other versions
WO2001016741A2 (en
Inventor
Lynn Parker West
Karlon K West
Original Assignee
Times N Systems Inc
Lynn Parker West
Karlon K West
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Times N Systems Inc, Lynn Parker West, Karlon K West filed Critical Times N Systems Inc
Priority to CA002382927A priority Critical patent/CA2382927A1/en
Priority to AU69497/00A priority patent/AU6949700A/en
Priority to EP00957948A priority patent/EP1214651A2/en
Publication of WO2001016741A2 publication Critical patent/WO2001016741A2/en
Publication of WO2001016741A3 publication Critical patent/WO2001016741A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/457—Communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/52—Indexing scheme relating to G06F9/52
    • G06F2209/523—Mode

Abstract

Methods, systems and devices are described for semaphore control of a shared-memory cluster. A method, includes writing at least one pointer to a semaphore region of a shared memory region that is coupled to a plurality of processing nodes. The at least one pointer points to at least one of the plurality of processing nodes, the at least one pointer i) indicating that a portion of the shared memory node is dedicated to reading by the at least one of the plurality of processing nodes and ii) protecting access to the portion of the shared memory node until the portion of the shared memory node has been read by the at least one of the plurality of processing nodes. The methods, systems and devices provide advantages because the speed and scalability of parallel processor systems is enhanced.
PCT/US2000/024217 1999-08-31 2000-08-31 Semaphore control of shared-memory WO2001016741A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002382927A CA2382927A1 (en) 1999-08-31 2000-08-31 Semaphore control of shared-memory
AU69497/00A AU6949700A (en) 1999-08-31 2000-08-31 Semaphore control of shared-memory
EP00957948A EP1214651A2 (en) 1999-08-31 2000-08-31 Semaphore control of shared-memory

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US15215199P 1999-08-31 1999-08-31
US60/152,151 1999-08-31
US60/220,794 2000-07-25
US22074800P 2000-07-26 2000-07-26
US22097400P 2000-07-26 2000-07-26
US60/220,748 2000-07-26

Publications (2)

Publication Number Publication Date
WO2001016741A2 WO2001016741A2 (en) 2001-03-08
WO2001016741A3 true WO2001016741A3 (en) 2001-09-20

Family

ID=27387201

Family Applications (9)

Application Number Title Priority Date Filing Date
PCT/US2000/024147 WO2001016737A2 (en) 1999-08-31 2000-08-31 Cache-coherent shared-memory cluster
PCT/US2000/024039 WO2001016760A1 (en) 1999-08-31 2000-08-31 Switchable shared-memory cluster
PCT/US2000/024150 WO2001016738A2 (en) 1999-08-31 2000-08-31 Efficient page ownership control
PCT/US2000/024298 WO2001016743A2 (en) 1999-08-31 2000-08-31 Shared memory disk
PCT/US2000/024217 WO2001016741A2 (en) 1999-08-31 2000-08-31 Semaphore control of shared-memory
PCT/US2000/024329 WO2001016750A2 (en) 1999-08-31 2000-08-31 High-availability, shared-memory cluster
PCT/US2000/024248 WO2001016742A2 (en) 1999-08-31 2000-08-31 Network shared memory
PCT/US2000/024216 WO2001016761A2 (en) 1999-08-31 2000-08-31 Efficient page allocation
PCT/US2000/024210 WO2001016740A2 (en) 1999-08-31 2000-08-31 Efficient event waiting

Family Applications Before (4)

Application Number Title Priority Date Filing Date
PCT/US2000/024147 WO2001016737A2 (en) 1999-08-31 2000-08-31 Cache-coherent shared-memory cluster
PCT/US2000/024039 WO2001016760A1 (en) 1999-08-31 2000-08-31 Switchable shared-memory cluster
PCT/US2000/024150 WO2001016738A2 (en) 1999-08-31 2000-08-31 Efficient page ownership control
PCT/US2000/024298 WO2001016743A2 (en) 1999-08-31 2000-08-31 Shared memory disk

Family Applications After (4)

Application Number Title Priority Date Filing Date
PCT/US2000/024329 WO2001016750A2 (en) 1999-08-31 2000-08-31 High-availability, shared-memory cluster
PCT/US2000/024248 WO2001016742A2 (en) 1999-08-31 2000-08-31 Network shared memory
PCT/US2000/024216 WO2001016761A2 (en) 1999-08-31 2000-08-31 Efficient page allocation
PCT/US2000/024210 WO2001016740A2 (en) 1999-08-31 2000-08-31 Efficient event waiting

Country Status (4)

Country Link
EP (3) EP1214651A2 (en)
AU (9) AU7108300A (en)
CA (3) CA2382927A1 (en)
WO (9) WO2001016737A2 (en)

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KR20040017301A (en) * 2001-07-13 2004-02-26 코닌클리케 필립스 일렉트로닉스 엔.브이. Method of running a media application and a media system with job control
US6999998B2 (en) 2001-10-04 2006-02-14 Hewlett-Packard Development Company, L.P. Shared memory coupling of network infrastructure devices
US6920485B2 (en) 2001-10-04 2005-07-19 Hewlett-Packard Development Company, L.P. Packet processing in shared memory multi-computer systems
US7254745B2 (en) 2002-10-03 2007-08-07 International Business Machines Corporation Diagnostic probe management in data processing systems
JP2008046969A (en) * 2006-08-18 2008-02-28 Fujitsu Ltd Access monitoring method and device for shared memory
US7685381B2 (en) 2007-03-01 2010-03-23 International Business Machines Corporation Employing a data structure of readily accessible units of memory to facilitate memory access
US7899663B2 (en) 2007-03-30 2011-03-01 International Business Machines Corporation Providing memory consistency in an emulated processing environment
US9442780B2 (en) * 2011-07-19 2016-09-13 Qualcomm Incorporated Synchronization of shader operation
US9064437B2 (en) 2012-12-07 2015-06-23 Intel Corporation Memory based semaphores
WO2014190486A1 (en) * 2013-05-28 2014-12-04 华为技术有限公司 Method and system for supporting resource isolation under multi-core architecture

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US4725946A (en) * 1985-06-27 1988-02-16 Honeywell Information Systems Inc. P and V instructions for semaphore architecture in a multiprogramming/multiprocessing environment
US5367690A (en) * 1991-02-14 1994-11-22 Cray Research, Inc. Multiprocessing system using indirect addressing to access respective local semaphore registers bits for setting the bit or branching if the bit is set
EP0769740A1 (en) * 1995-10-17 1997-04-23 International Business Machines Corporation Inter-object communication

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Also Published As

Publication number Publication date
WO2001016761A2 (en) 2001-03-08
AU7113600A (en) 2001-03-26
WO2001016761A3 (en) 2001-12-27
AU7110000A (en) 2001-03-26
WO2001016741A2 (en) 2001-03-08
WO2001016738A9 (en) 2002-09-12
EP1214653A2 (en) 2002-06-19
EP1214652A2 (en) 2002-06-19
CA2382728A1 (en) 2001-03-08
WO2001016742A2 (en) 2001-03-08
AU7108300A (en) 2001-03-26
WO2001016738A3 (en) 2001-10-04
WO2001016743A3 (en) 2001-08-09
AU6949700A (en) 2001-03-26
WO2001016760A1 (en) 2001-03-08
WO2001016743A2 (en) 2001-03-08
WO2001016742A3 (en) 2001-09-20
WO2001016750A2 (en) 2001-03-08
CA2382927A1 (en) 2001-03-08
WO2001016740A3 (en) 2001-12-27
WO2001016750A3 (en) 2002-01-17
WO2001016737A2 (en) 2001-03-08
WO2001016738A2 (en) 2001-03-08
WO2001016738A8 (en) 2001-05-03
WO2001016740A2 (en) 2001-03-08
AU7100700A (en) 2001-03-26
CA2382929A1 (en) 2001-03-08
AU7112100A (en) 2001-03-26
WO2001016737A3 (en) 2001-11-08
AU6949600A (en) 2001-03-26
WO2001016743A8 (en) 2001-10-18
EP1214651A2 (en) 2002-06-19
AU7474200A (en) 2001-03-26
AU7108500A (en) 2001-03-26

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