WO2001013247A2 - System and method for address broadcast synchronization using a plurality of switches - Google Patents
System and method for address broadcast synchronization using a plurality of switches Download PDFInfo
- Publication number
- WO2001013247A2 WO2001013247A2 PCT/US2000/022563 US0022563W WO0113247A2 WO 2001013247 A2 WO2001013247 A2 WO 2001013247A2 US 0022563 W US0022563 W US 0022563W WO 0113247 A2 WO0113247 A2 WO 0113247A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- switch
- address
- request
- sources
- wherem
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17375—One dimensional, e.g. linear array, ring
Definitions
- N > 4 One problem with building an address network m hardware for large systems (N > 4) is that one needs a very large pm count ASIC (Application Specific Integrated Circuit) to accommodate all address-ms and address- outs for all cacheable devices to mamtain address synchronization
- ASIC Application Specific Integrated Circuit
- Fig 1 is a block diagram of a computer system including two switches, switch 110A and switch 110B.
- the computer system mcludes CPUs 115A-115H, mput and output devices (I O) 120A-120D, and memones 125A-125D.
- Data signals beginning with a P have a processor 115 as a destmation, and data signals beginning with an I/O have an I/O device 120 as a destination
- Switches 110A and HOB are shown receiving mput from vanous groupmgs of the processors 115 and the I/O devices 120.
- the switches 110A and HOB are also shown outputtmg signals to vanous ones of the processors 115, the I/O devices 120, and to the memories 125
- P7_req and I/02_req and I/03_req Switch HOB outputs address signals P4-P7, I/02-I/03, and M2-M3
- Each mcommg address P4-P7 and I/02-I 03 is received mto an mput FIFO 205G-205L
- the address requests that correspond to the addresses received m the mput FIFOs 205G-205L are received at a request arbiter 215B
- the request arbiter 215B is a round-robm arbiter, although any other means of arbitration may be used as desired for choosmg requests received by request arbiter 215B
- the request arbiter 215B controls the selection at input MUX 210B with regard to the output of the mput FIFOs 205G-205L
- the selected address request is output as SWl_req to delay cucuit 235B
- Switch HOB is also coupled to receive the address request SW0_req from switch 110A, as well as address output signal 220A Signal 220A is received at incoming FIFO 230B As shown, broadcast FIFO 225B and incoming FIFO 230B each output data to output MUX 245B, broadcast FIFO 225B as ' 1 ' (one) and incoming FIFO 230B as '0' (zero) Address request SWl_req is delayed for a period of time m delay circuit 235B before being provided to broadcast arbiter 240B The period of tune of the delay may be a predetermined period of time.
- MUXes 245 will select ' 1 ' and the next granted will be switch HOB (step 330) It is noted that broadcast arbiter
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE60002094T DE60002094D1 (en) | 1999-08-16 | 2000-08-16 | SYSTEM AND METHOD FOR ADDRESS BROADCAST SYNCHRONIZATION WITH A NUMBER OF SWITCHES |
AU69118/00A AU6911800A (en) | 1999-08-16 | 2000-08-16 | System and method for address broadcast synchronization using a plurality of switches |
EP00957512A EP1208440B1 (en) | 1999-08-16 | 2000-08-16 | System and method for address broadcast synchronization using a plurality of switches |
AT00957512T ATE237156T1 (en) | 1999-08-16 | 2000-08-16 | SYSTEM AND METHOD FOR ADDRESS BROADCAST SYNCHRONIZATION USING A PLURALITY OF SWITCHES |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/374,639 US6567885B1 (en) | 1999-08-16 | 1999-08-16 | System and method for address broadcast synchronization using a plurality of switches |
US09/374,639 | 1999-08-16 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2001013247A2 true WO2001013247A2 (en) | 2001-02-22 |
WO2001013247A3 WO2001013247A3 (en) | 2001-08-30 |
WO2001013247A9 WO2001013247A9 (en) | 2001-09-20 |
Family
ID=23477631
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/022563 WO2001013247A2 (en) | 1999-08-16 | 2000-08-16 | System and method for address broadcast synchronization using a plurality of switches |
Country Status (6)
Country | Link |
---|---|
US (2) | US6567885B1 (en) |
EP (1) | EP1208440B1 (en) |
AT (1) | ATE237156T1 (en) |
AU (1) | AU6911800A (en) |
DE (1) | DE60002094D1 (en) |
WO (1) | WO2001013247A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6877056B2 (en) * | 2002-06-28 | 2005-04-05 | Sun Microsystems, Inc. | System with arbitration scheme supporting virtual address networks and having split ownership and access right coherence mechanism |
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US6567885B1 (en) * | 1999-08-16 | 2003-05-20 | Sun Microsystems, Inc. | System and method for address broadcast synchronization using a plurality of switches |
US6813267B1 (en) * | 2000-09-11 | 2004-11-02 | Sun Microsystems, Inc. | Tunable broadcast/point-to-point packet arbitration |
US6889343B2 (en) * | 2001-03-19 | 2005-05-03 | Sun Microsystems, Inc. | Method and apparatus for verifying consistency between a first address repeater and a second address repeater |
US20020133652A1 (en) * | 2001-03-19 | 2002-09-19 | Tai Quan | Apparatus for avoiding starvation in hierarchical computer systems that prioritize transactions |
US6826643B2 (en) * | 2001-03-19 | 2004-11-30 | Sun Microsystems, Inc. | Method of synchronizing arbiters within a hierarchical computer system |
US6877055B2 (en) | 2001-03-19 | 2005-04-05 | Sun Microsystems, Inc. | Method and apparatus for efficiently broadcasting transactions between a first address repeater and a second address repeater |
US6950893B2 (en) * | 2001-03-22 | 2005-09-27 | I-Bus Corporation | Hybrid switching architecture |
US7376811B2 (en) * | 2001-11-06 | 2008-05-20 | Netxen, Inc. | Method and apparatus for performing computations and operations on data using data steering |
US7548957B1 (en) | 2002-05-07 | 2009-06-16 | Oracle International Corporation | Method and mechanism for a portal website architecture |
US7277924B1 (en) * | 2002-05-07 | 2007-10-02 | Oracle International Corporation | Method and mechanism for a portal website architecture |
JP3770203B2 (en) * | 2002-05-21 | 2006-04-26 | 日本電気株式会社 | Crossbar acceleration method and crossbar acceleration method |
GB2409306A (en) * | 2003-12-20 | 2005-06-22 | Autodesk Canada Inc | Data processing network with switchable storage |
US7451231B2 (en) * | 2005-02-10 | 2008-11-11 | International Business Machines Corporation | Data processing system, method and interconnect fabric for synchronized communication in a data processing system |
US20060176890A1 (en) * | 2005-02-10 | 2006-08-10 | International Business Machines Corporation | Data processing system, method and interconnect fabric for improved communication in a data processing system |
WO2007029053A1 (en) * | 2005-09-09 | 2007-03-15 | Freescale Semiconductor, Inc. | Interconnect and a method for designing an interconnect |
JP5270077B2 (en) * | 2006-08-18 | 2013-08-21 | 富士通株式会社 | Arbitration circuit, crossbar, request selection method, and information processing apparatus |
US8082381B2 (en) * | 2008-09-02 | 2011-12-20 | Nvidia Corporation | Connecting a plurality of peripherals |
US8103803B2 (en) * | 2008-11-21 | 2012-01-24 | Nvidia Corporation | Communication between a processor and a controller |
US8610732B2 (en) * | 2008-12-11 | 2013-12-17 | Nvidia Corporation | System and method for video memory usage for general system application |
US8677074B2 (en) * | 2008-12-15 | 2014-03-18 | Nvidia Corporation | Shared memory access techniques |
US8984206B2 (en) * | 2012-10-31 | 2015-03-17 | International Business Machines Corporation | Weightage-based scheduling for hierarchical switching fabrics |
US8902899B2 (en) | 2013-02-08 | 2014-12-02 | International Business Machines Corporation | Input buffered switching device including bypass logic |
US9311207B1 (en) * | 2013-09-12 | 2016-04-12 | Emc Corporation | Data storage system optimizations in a multi-tiered environment |
US9467396B2 (en) | 2014-04-11 | 2016-10-11 | International Business Machines Corporation | Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US5166926A (en) * | 1990-12-18 | 1992-11-24 | Bell Communications Research, Inc. | Packet address look-ahead technique for use in implementing a high speed packet switch |
US5513369A (en) * | 1991-08-05 | 1996-04-30 | Ncr Corporation | Star coupler device including means for connecting multiple star couplers together in a cascaded relationship |
Family Cites Families (7)
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US4398176A (en) | 1980-08-15 | 1983-08-09 | Environmental Research Institute Of Michigan | Image analyzer with common data/instruction bus |
US5179552A (en) * | 1990-11-26 | 1993-01-12 | Bell Communications Research, Inc. | Crosspoint matrix switching element for a packet switch |
US5613071A (en) | 1995-07-14 | 1997-03-18 | Intel Corporation | Method and apparatus for providing remote memory access in a distributed memory multiprocessor system |
US5862357A (en) | 1996-07-02 | 1999-01-19 | Sun Microsystems, Inc. | Hierarchical SMP computer system |
US6483844B1 (en) * | 1999-05-13 | 2002-11-19 | Advanced Micro Devices, Inc. | Apparatus and method for sharing an external memory between multiple network switches |
US6567885B1 (en) * | 1999-08-16 | 2003-05-20 | Sun Microsystems, Inc. | System and method for address broadcast synchronization using a plurality of switches |
US7020146B2 (en) * | 2001-08-30 | 2006-03-28 | Sun Microsystems, Inc. | Broadcast arbitration in a multi-domain device |
-
1999
- 1999-08-16 US US09/374,639 patent/US6567885B1/en not_active Expired - Lifetime
-
2000
- 2000-08-16 AT AT00957512T patent/ATE237156T1/en not_active IP Right Cessation
- 2000-08-16 DE DE60002094T patent/DE60002094D1/en not_active Expired - Lifetime
- 2000-08-16 EP EP00957512A patent/EP1208440B1/en not_active Expired - Lifetime
- 2000-08-16 WO PCT/US2000/022563 patent/WO2001013247A2/en active IP Right Grant
- 2000-08-16 AU AU69118/00A patent/AU6911800A/en not_active Abandoned
-
2003
- 2003-04-02 US US10/405,876 patent/US6678784B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5166926A (en) * | 1990-12-18 | 1992-11-24 | Bell Communications Research, Inc. | Packet address look-ahead technique for use in implementing a high speed packet switch |
US5513369A (en) * | 1991-08-05 | 1996-04-30 | Ncr Corporation | Star coupler device including means for connecting multiple star couplers together in a cascaded relationship |
Non-Patent Citations (1)
Title |
---|
M. JACUNSKI, P. SADAYAPPAN, D. K. PANDA: "All to all broadcast on switch-based clusters of workstations" DEPARTMENT OF COMPUTER AND INFORMATION SCIENCE, [Online] October 1998 (1998-10), pages 1-18, XP002161065 Ohio state university, Colombus Retrieved from the Internet: <URL:ohiostate.edu/~jacunski...ipps_full.p s> [retrieved on 2001-02-21] * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6877056B2 (en) * | 2002-06-28 | 2005-04-05 | Sun Microsystems, Inc. | System with arbitration scheme supporting virtual address networks and having split ownership and access right coherence mechanism |
Also Published As
Publication number | Publication date |
---|---|
AU6911800A (en) | 2001-03-13 |
US6567885B1 (en) | 2003-05-20 |
US6678784B2 (en) | 2004-01-13 |
EP1208440A2 (en) | 2002-05-29 |
DE60002094D1 (en) | 2003-05-15 |
ATE237156T1 (en) | 2003-04-15 |
EP1208440B1 (en) | 2003-04-09 |
WO2001013247A9 (en) | 2001-09-20 |
US20030191879A1 (en) | 2003-10-09 |
WO2001013247A3 (en) | 2001-08-30 |
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