WO2000075796A1 - Isolated high-speed communication bus - Google Patents

Isolated high-speed communication bus Download PDF

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Publication number
WO2000075796A1
WO2000075796A1 PCT/EP2000/004927 EP0004927W WO0075796A1 WO 2000075796 A1 WO2000075796 A1 WO 2000075796A1 EP 0004927 W EP0004927 W EP 0004927W WO 0075796 A1 WO0075796 A1 WO 0075796A1
Authority
WO
WIPO (PCT)
Prior art keywords
isolation device
transmission
line
connector
isolation
Prior art date
Application number
PCT/EP2000/004927
Other languages
French (fr)
Inventor
Marc S. Walker
Barry Albright
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP00936831A priority Critical patent/EP1101169A1/en
Priority to JP2001501999A priority patent/JP2004500616A/en
Priority to KR1020017001686A priority patent/KR20010072347A/en
Publication of WO2000075796A1 publication Critical patent/WO2000075796A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/648—Protective earth or shield arrangements on coupling devices, e.g. anti-static shielding  
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Isolation components (320, 420) are connected directly between a communications bus (180) and a connector (110a-z) that connects plug-in modules (200) to the common bus, to minimize the capacitive loading on the communications bus. In one embodiment of this invention, a diode (320) is placed between the communications bus (180) and the connector (110), thereby isolating the communications bus from the capacitance of the connector and associated wiring when the diode is in the off condition. In a preferred embodiment of the invention, an isolation transistor (420) is placed between the communications bus (180) and the connector (110), and is configured to present a small and consistent collector capacitance to the communications bus in both an on and off condition. By providing a known capacitance at known points on the transmission line forming the communications bus, conventional compensation techniques can be employed to minimize or eliminate the effects of these capacitances. The techniques present herein may be applied to both unidirectional and bi-directional bus communications.

Description

Isolated high-speed communication bus.
1. Field of the Invention
This invention relates to the field of electronic systems, and in particular to high-speed communication buses that commonly connect plug-in modules.
2. Description of Related Art
Modular systems commonly use an interconnection board or ribbon cable to interconnect the modules comprising the system. A bus structure is often provided for modular systems, so that each module that is plugged into the interconnection board or cable is provided access as required to a signal path that is common to other modules.
FIG. 1 illustrates an example interconnect board/cable 100 comprising a plurality of input connectors 1 lOa-l lOz and an output connector 120. For ease of reference, the term "interconnect board" will be used hereinafter to refer to either a rigid circuit board, a flexible cable, or any other configuration for interconnecting plug-in modules. As illustrated by the interconnection traces 180, in a typical modular system, each pin of each input connector 1 lOa-z is connected in common with a corresponding pin of each other input connector 1 lOa-z. Commonly, the output connector 120 also has corresponding pins to each of the pins of the input connectors 1 lOa-z, as illustrated in FIG. 1, although differing pinouts between input and output connectors may be used. FIG. 2 illustrates an example circuit diagram corresponding to a typical use of an interconnection board 100. Illustrated in FIG. 2 are plug-in modules (PIMs) 200a-z. At high frequencies, the trace 180 acts as a transmission line, and can amount to a significant portion of a signal wavelength, or multiple wavelengths. For ease of reference, a trace 180 that communicates high-frequency signals is termed herein as a transmission-line 180. Termination resistors 231, 232 are provided at the end of each transmission-line 180, and each module 200a-z is configured to be isolated from the transmission-line 180 except when communicating information, to reduce signal reflections and to minimize signal distortions. Each PIM 200 contains an isolation transistor 210 that isolates each module 200 from the interconnect board 100. Not illustrated, each module 200 comprises circuitry to produce the signal Vin 201, which is either an information signal that is communicated to the output module 250 via the transmission-line 180, or a bias signal that isolates the module 200 from the transmission-line 180. Only one transmission-line 180 is illustrated in FIG. 2; each transmission-line 180 corresponding to a different pin of each module 200 could be configured as illustrated in FIG. 2. Some traces, such as power and ground traces that do not communicate high-speed signals, would not have corresponding isolation transistors 210 on each module 200.
As is common in the art, only one input module 200 typically communicates via a communications transmission-line 180 at one time, and the isolation transistor 210 on each module disconnects each of the non-communicating modules 200 while the currently- selected module 200 transmits its information Vin 201 via the transmission-line 180 to the output module 250 that is connected via the connector 120. As would be evident to one of ordinary skill in the art, if the output module 250 is contained on the same circuit board, such as a "mother-board", that contains the input connectors 1 lOa-z, a connector 120 is not used. The non-communicating modules 200 bias the signal 201 to the isolation transistor 210 to prevent any current flow from the transmission-line 180 to or from the non-communicating module 200. In some applications, multiple modules 200 may communicate simultaneously via the transmission-line 180, and in these applications, the communicating modules 200 each bias the isolation transistor 210 to a conducting state to communicate their information signals 201. Although the conventional isolation scheme illustrated in FIG. 2 is effective for isolating most of the components of the modules 200 from the transmission-line 180, it does not, however, isolate the wiring and the connectors 1 lOa-z between the transmission- line 180 and each module 200a-z. Each of the connectors 1 lOa-z and the associated wiring add a capacitance in parallel to the transmission-line 180 at each connection point. This sudden change, or discontinuity, in impedance causes reflections to signals coming from either side of the discontinuity. A portion of the signal will propagate past the discontinuity, but a portion of the signal will be reflected back toward its source, the currently communicating module 200. The original and reflected signals then encounter discontinuities at other connectors, thereby causing further reflections. These reflections add to the original, desired, signal on the transmission-line 180 and cause the desired signal to be distorted when it is received at the output module 250. This problem can be further compounded when improperly designed modules 200 are plugged into the interconnect board. If the isolation transistor is placed on the module 200 such that it is located at a significant distance from the connection 1 lOa-z, it will form a "stub" on the transmission-line 180, and will appear as additional capacitance to signals traveling on the transmission-line 180. The additional capacitance of this stub may or may not affect the communication of signals from the mis- designed module 200 that contains this additional capacitance, but will generally distort the signals from each of the other modules 200. In like manner, the connection point of this stub at the transmission-line partitions the transmission-line 180 into two sections, and the shorter section will appear as a stub to a signal coming from the mis-designed module 200, thereby introducing a distortion to such a signal. These distortions are often extremely difficult to diagnose and eliminate, because of the particular cause-and-effect relationships between the introduction of a stub and its subsequent effect on signals that are otherwise independent of the stub.
It is an object of this invention to improve the signal quality of signals that are transmitted from plug-in modules to an output processor via a common bus. It is a further object of this invention to provide an interconnection scheme that has minimal dependence upon the design of the plug-in modules.
These objects and others are achieved by providing isolation components that are connected directly to a common bus, before the connectors that are used to accept plug-in modules to the common bus. In one embodiment of this invention, a diode is placed between the transmission-line and the connector, to isolate the transmission line from the capacitance of the connector and associated wiring when the diode is in the off condition. In a preferred embodiment of the invention, an isolation transistor is placed between the transmission line and the connector, and is configured to eliminate the stub caused by the connector, and thereby present a small and consistent collector capacitance to the transmission line in both an on and off condition, and a high impedance to the transmission line in the off condition and in a non-saturated on condition. By providing a known capacitance at known points on the transmission line, conventional compensation techniques can be employed to minimize or eliminate the effects of these capacitances. The techniques presented herein may be applied to both unidirectional and bi-directional bus communications.
The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein: FIG. 1 illustrates an example prior art interconnection board/cable for accommodating plug- in modules.
FIG. 2 illustrates an example circuit diagram associated with a prior art interconnection board/cable for accommodating plug-in modules. FIG. 3 illustrates an example circuit diagram of an interconnection board/cable with isolation diodes in accordance with this invention.
FIG. 4 illustrates an example circuit diagram of an interconnection board/cable with isolation transistors in accordance with this invention.
FIG. 5 illustrates an example circuit diagram of an interconnection board/cable with bi-directional isolation transistors in accordance with this invention.
Throughout the drawings, the same reference numerals indicate similar or corresponding features or functions.
FIG. 3 illustrates an example circuit diagram of an interconnection board/cable with isolation diodes 320a-z in accordance with this invention. Each isolation diode 320a-z is connected between the transmission-line 180 and the corresponding connector 11 Oa-z. When the Vin 201 signal of each non-communicating module 200 biases the transistor 210 to an off state, the diode 320 is also biased to an off state, and the capacitance of the connector 110 and any associated wiring to the isolation transistor 210 is isolated from the transmission-line 180. This isolation minimizes the distortions caused by discontinuities along the transmission-line 180 by minimizing the capacitance associated with each non- communicating module 200. It does not, however, minimize the capacitance associated with the communicating module or modules 200. This capacitance can have adverse affects on the quality of the transmitted signal, and, because each module 200 may exhibit a different capacitance when communicating, conventional transmission-line distortion-minimization techniques will have differing effects, depending upon the capacitance of the particular module 200.
FIG. 4 illustrates an example circuit diagram of an interconnection board/cable with isolation transistors 420 that isolate both the communicating and non-communicating modules 200' in accordance with this invention. In the example of FIG. 4, the isolation transistor 420 is placed between the transmission-line 180 and the connector 110, and provides a collector capacitance to the transmission-line 180 that is substantially less than the capacitance of the connector 110 and associated wiring, and substantially independent of whether the transistor 420 is conducting or non-conducting. Also, by providing the isolation transistor 420 on the interconnect board 400, the connector 110 and its associated wiring do not appear as a stub to the transmission-line 180. That is, the characteristics of the transmission-line 180 is substantially independent of the capacitance of the connector 110 and associated wiring, including the wiring of each module 200'. Because the capacitance of each connection to the transmission-line 180 will be of lower capacitance, and a consistent capacitance, conventional transmission-line distortion-minimization techniques can be employed effectively, without regard to the specific design of each module 200'. In a preferred embodiment, a resistor 440 is placed between the base of the transistor 420 and ground for stability.
Note that because the isolation transistor 420 provides the isolation that the isolation transistor 210 provides in a conventional system configuration, the modules 200' in this embodiment need not contain the isolation transistor 210. The isolation provided by the transistor 420 on the interconnect board 400 also reduces the design constraints and transmission-line considerations in the design of each module 200', thereby potentially reducing the design and testing costs associated with each module 200'. Note also that the collector output of the transistor 420 presents a high impedance to the transmission-line 180 when it is off, and when it is on but not saturated. This high impedance allows two or more transistors 420 to be turned on at the same time, and allows signals to be combined on the transmission-line 180. In a preferred embodiment, the collector output impedance is at least ten times the impedance of the transmission-line 180, and modules that are not actively communicating signals bias the corresponding transistor 420 to an off, non-conducting, state. FIG. 5 illustrates an example circuit diagram of an interconnection board/cable 500 with bi-directional isolation transistors 420, 520 in accordance with this invention. The example modules 550 are configured to provide input signals Vin 201 , and to receive output signals Vout 505. The isolation transistor 420 provides the input isolation discussed above, and the isolation transistor 520 forms a receiver that provides a low capacitance load to the transmission line 180.
The foregoing merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are thus within its spirit and scope. For example, the connectors 110 may be configured to contain the appropriate isolation devices 320, 420, 520 within their housings. Also, an interconnect board may be configured to provide connectors that receive both the example input-only modules 200 and 200', as well as the bi-direction modules 550. In like manner, although the invention has been presented using a single transmission-line per signal, differential signaling may also be employed, wherein two transmission lines are operated in opposition to each other, for improved noise immunity. Although the example embodiments are illustrated with bipolar transistors and diodes, other switching devices, including field effect transistors, can also be used, provided that they can be configured to present a high impedance to the transmission-line when placed in the non-conducting mode. Other system configuration and optimization features will be evident to one of ordinary skill in the art in view of this disclosure, and are included within the scope of the following claims.

Claims

CLAIMS:
1. An interconnect board comprising:
- one or more transmission lines for communicating high-frequency signals, and
- a plurality of connectors that are each configured to receive a plug- in module, each connector of the plurality of connectors having one or more pins that are operably coupled to the one or more transmission lines via an isolation device, wherein each isolation device is configured to provide a low-capacitance load to the one or more transmission lines when the isolation device is in a non-conducting state.
2. The interconnect board of claim 1 , wherein each isolation device is further configured to provide a low-capacitance load to the one or more transmission lines when the isolation device is in a conducting state.
3. The interconnect board of claim 1, wherein the isolation device comprises a semiconductor device that is biased to the non-conducting state by an input signal received from the plug-in module.
4. The interconnect board of claim 1 , wherein each isolation device is further configured to provide a high-impedance load to the one or more transmission lines when the isolation device is in a non-conducting state.
5. The interconnect board of claim 4, wherein each isolation device is further configured to provide a high-impedance load to the one or more transmission lines when the isolation device is in a non-saturated conducting state.
6. The interconnect board of claim 1, wherein each isolation device includes:
- a bipolar transistor having a base, a collector, and an emitter, and
- a resistor that couples the base to a reference potential; and - the collector and emitter form a switch path between a corresponding transmission line of the one or more transmission lines and a corresponding pin of the one of more pins of the connector.
7. A communications system comprising: - an interconnection board that includes at least one transmission line, a plurality of connectors, and a plurality of isolation devices that are configured to operably couple the at least one transmission-line to each connector of the plurality of connectors when in a first state, and operably de-couple the at least one transmission-line to each connector of the plurality of connectors when in a second state; and
- a plurality of plug-in modules that are configured to communicate information via the at least one transmission line when connected to corresponding connectors of the plurality of connectors.
8. The communications system of claim 7, wherein each isolation device of the plurality of isolation devices is configured to provide a low-capacitance load to the at least one transmission line when the isolation device is in the second state.
9. The communications system of claim 8, wherein each isolation device is further configured to provide a low-capacitance load to the at least one transmission line when the isolation device is in the first state.
10. The communications system of claim 7, wherein each isolation device of the plurality of isolation devices comprises a semiconductor device that is biased to the first state and the second state by an input signal received from the plug-in module.
11. The communications system of claim 7, wherein each isolation device is further configured to provide a high-impedance load to the at least one transmission line when the isolation device is in a non-conducting state.
12. The communications system of claim 11 , wherein each isolation device is further configured to provide a high-impedance load to the at least one transmission line when the isolation device is in a non-saturated conducting state.
13. The communications system of claim 11 , wherein each isolation device includes:
- a bipolar transistor having a base, a collector, and an emitter, and
- a resistor that couples the base to a reference potential; and the collector and emitter of each isolation device are configured to: - operably couple the at least one transmission-line to a corresponding pin of a corresponding connector of the plurality of connectors when the transistor is biased to the first state, and
- operably de-couple the at least one transmission-line from the corresponding pin when the transistor is biased to the second state.
PCT/EP2000/004927 1999-06-08 2000-05-29 Isolated high-speed communication bus WO2000075796A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00936831A EP1101169A1 (en) 1999-06-08 2000-05-29 Isolated high-speed communication bus
JP2001501999A JP2004500616A (en) 1999-06-08 2000-05-29 Insulated high-speed communication bus
KR1020017001686A KR20010072347A (en) 1999-06-08 2000-05-29 Isolated high-speed communication bus

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13817699P 1999-06-08 1999-06-08
US60/138,176 1999-06-08
US53168800A 2000-03-20 2000-03-20
US09/531,688 2000-03-20

Publications (1)

Publication Number Publication Date
WO2000075796A1 true WO2000075796A1 (en) 2000-12-14

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PCT/EP2000/004927 WO2000075796A1 (en) 1999-06-08 2000-05-29 Isolated high-speed communication bus

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JP (1) JP2004500616A (en)
KR (1) KR20010072347A (en)
WO (1) WO2000075796A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1383052A1 (en) * 2002-07-15 2004-01-21 Infineon Technologies AG Memory system
US7188204B2 (en) * 2001-12-19 2007-03-06 Infineon Technologies Ag Memory unit and branched command/address bus architecture between a memory register and a plurality of memory units
US7675325B2 (en) 2008-05-02 2010-03-09 Alcatel Lucent GTL backplane bus with improved reliability

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656471A (en) * 1984-01-26 1987-04-07 Siemens Aktiengesellschaft Circuit arrangement for connecting a subscriber to a bus line via switch means under which prevents disabling of the bus line in the event of driver failure
US4697858A (en) * 1986-02-07 1987-10-06 National Semiconductor Corporation Active bus backplane
US5754060A (en) * 1992-01-31 1998-05-19 Nguyen; Trung Electronic system including high performance backplane driver/receiver circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656471A (en) * 1984-01-26 1987-04-07 Siemens Aktiengesellschaft Circuit arrangement for connecting a subscriber to a bus line via switch means under which prevents disabling of the bus line in the event of driver failure
US4697858A (en) * 1986-02-07 1987-10-06 National Semiconductor Corporation Active bus backplane
US5754060A (en) * 1992-01-31 1998-05-19 Nguyen; Trung Electronic system including high performance backplane driver/receiver circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7188204B2 (en) * 2001-12-19 2007-03-06 Infineon Technologies Ag Memory unit and branched command/address bus architecture between a memory register and a plurality of memory units
EP1383052A1 (en) * 2002-07-15 2004-01-21 Infineon Technologies AG Memory system
US6856554B2 (en) 2002-07-15 2005-02-15 Infineon Technologies Ag Memory system
US7675325B2 (en) 2008-05-02 2010-03-09 Alcatel Lucent GTL backplane bus with improved reliability

Also Published As

Publication number Publication date
EP1101169A1 (en) 2001-05-23
JP2004500616A (en) 2004-01-08
KR20010072347A (en) 2001-07-31

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