WO2000041239A1

WO2000041239A1 - Chip package including peltier cooling

Info

Publication number: WO2000041239A1
Application number: PCT/US1999/008292
Authority: WO
Inventors: Howard Hsu
Original assignee: Howard Hsu
Priority date: 1998-12-31
Filing date: 1999-04-15
Publication date: 2000-07-13

Abstract

An apparatus is shown for cooling a semiconductor device (221) using a Peltier cooler situated around a semiconductor device (221) within a package. The described cooling method is especially useful for cooling a semiconductor device within a BGA (Ball Grid Array) package using a multi-stage Peltier device. A multi-stage Peltier device or multiple singe Peltier devices are provided within a package, with the Peltier devices surrounding the semiconductor chip (221). When electrical connections (239) are made to the chip (221) by bump bonding, it is preferred that the chip (221) is mounted with its backside on a plate (211) connected to the cooling terminal of the semiconductor chip (221). When the chip (221) is mounted in a face down or flip chip (321) configuration, it is preferred that the semiconductor chip (221) is cooled by withdrawing heat from the semiconductor chip (221) through the leads connected to the circuits within the semiconductor device (221). Either of these configurations can be used in providing a package that is mounted on a board using a ball grid array configuration. By passing current through multiple stages of Peltier devices or by using plural Peltier devices in combination, a significant amount of heat, e.g., up to 12W, can be efficiently removed from the semiconductor device (221) within the package.

Description

Chip Package Including Peltier Cooling

Related Application

This application claims priority from R.O.C. patent application Serial No. 87107062, filed on May 7, 1998, which application is hereby incorporated by reference.

Background of the Invention

Field of the Invention

The present invention relates to a package for a semiconductor device where the package is capable of removing heat from the packaged semiconductor device. The invention especially relates to a BGA (Ball Grid Array) package including a semiconductor device coupled to a Peltier device within the package that cools the semiconductor device.

Description of the Related Art Advancements in semiconductor fabrication technology allow production of higher density semiconductor chips that need to dissipate greater amounts of heat because the larger number of devices within such a chip generate more heat. Modern semiconductor chips also tend to operate at increasingly higher clock frequencies, which also increase the heat generation within the chip. The increased heat generated by higher density chip construction and higher operating frequencies requires that increased amounts of heat be exhausted from the chips. To ensure that semiconductor chips operate reliably, the increased heat generated is removed, preferably to maintain the operating temperature of the chip at nominal operating temperatures. Providing sufficient cooling to semiconductor devices to ensure that the semiconductor devices operate within a desired or nominal temperature range has been and remains a major concern in the semiconductor industry.

The task of cooling semiconductor chips is made more difficult by the practice of encapsulating semiconductor chips within plastic or other materials to protect the semiconductor chips from both physical and environmental damage. Encapsulation tends to keep heat within the package. Consequently, the semiconductor chip is mounted on a heat sink such as a metallic sheet to transfer the heat generated by the semiconductor chip through the encapsulating material and to exhaust the heat outside of the package. The heat removed from the chip by the heat sink is typically exhausted by the heat sink into the air or into a larger cooling reservoir. Sometimes, a heat sink is provided with fins or connected to a finned structure to make the process of exhausting heat into the air more efficient. Other times, an electric fan is used with a simple or a finned heat sink, with the fan circulating air by the heat sink to speed the cooling process. However, the amount of heat that can be passively exhausted through a heat sink is limited, even when an electric fan is used to make the cooling process more efficient. When the heat generated within the semiconductor device cannot be adequately dissipated into the air, the temperature of the semiconductor chip rises. Operation at elevated temperatures degrades the performance of semiconductor devices, for example, causing processors to generated errors more frequently.

Traditional cooling methods including heat-sinking methods may not work adequately with modern semiconductor devices that include high-density integrated circuits and that operate at high frequencies. The heat dissipated using traditional cooling methods can be inadequate for some semiconductor devices. For example, the traditional cooling methods may be limited to about seven Watts of cooling power, while a modern semiconductor chip may generate heat at a sustained rate in excess of seven Watts. A particular difficulty arises when using packaging techniques particularly well suited to high-density devices. Such high-density packaging techniques may include, for example, flip chip mounting and ball grid array packaging. These types of packages are in some cases not readily compatible with the use of heat sinking as a cooling method. Packaging techniques such as ball grid array packaging emphasize connecting pads on the face of a semiconductor chip to the contacts within the package. It is not easy to provide a heat sink mounted to the backside of the semiconductor chip under these conditions without unacceptable risk of damaging the chip.

It is therefore an object of the present invention to provide an improved apparatus for packaging semiconductor devices and providing cooling to semiconductor devices mounted within packages. Summary of the Preferred Embodiments

The present invention relates to a package for a semiconductor chip or like device where the package includes an integral Peltier cooler. Preferred embodiments of the present invention are particularly applicable to modern semiconductor devices that generate high levels of heat. In certain particularly preferred embodiments, a Peltier cooler may be provided around a semiconductor chip to provide compact active cooling for the chip while not increasing or only marginally increasing the size of the package. Aspects of the present invention find particular application in packaging semiconductor devices within a BGA (Ball Grid Array) package where heat is withdrawn from the packaged chip primarily through the leads of the semiconductor device. Most preferably, embodiments of the invention include multiple Peltier devices or a multi-stage Peltier device adjacent to or around the semiconductor chip. By passing current through the multiple Peltier devices or through a multi-stage Peltier device, a significant amount of heat, e.g., up to 12W, can be dissipated efficiently.

In a further aspect of a preferred embodiment of the invention, the amount of heat removed, i.e., the cooling power, is adjusted in accordance with the operating voltage of the device and so, approximately, the heat generated by the semiconductor device. Another aspect of the invention provides a package with a plurality of Peltier devices arranged to define a cooling surface and a heated surface. The Peltier devices are arranged adjacent a cavity, where the cavity is adapted to hold a semiconductor device in thermal communication with the cooling surface. The cavity is provided in a manner whereby electrical connections can be made between a semiconductor device within the cavity and the package. A first Peltier connection to one of the Peltier devices receives an electrical current from a power source and a second Peltier connection to another one of the Peltier devices returns the electrical current to the power source. Electrical couplings between the Peltier devices are provided so that the electrical current passes from the first Peltier connection to the second Peltier connection through a plurality of the Peltier devices, wherein passage of the electrical current cools the cooling surface.

The invention will be best understood from the following description when read in conjunction with the accompanying drawings. Brief Description of the Drawings

FIG. 1 schematically illustrates aspects of Peltier cooling for semiconductor devices as is preferred in accordance with aspects of the present invention.

FIGS. 2a, 2b, and 2c respectively show a cross section, a side, and a partial perspective view of a packaged semiconductor device surrounded by a Peltier cooling device where the package provides a BGA (Ball Grid Array) for connecting the package to a wiring board and where the connections to the semiconductor device are provided through wire bonding.

FIGS. 3a, 3b, and 3c respectively show a cross section, a side, and a partial perspective view of a packaged semiconductor device surrounded by a Peltier cooling device where the package provides a BGA (Ball Grid Array) for connecting the package to a wiring board and where the connections to a flip-chip semiconductor chip are provided through a ball grid array.

Detailed Description of the Preferred Embodiments The present invention relates to an apparatus for removing heat from a semiconductor chip within a package. In particularly preferred embodiments of the invention, the package incorporates a Peltier cooling device, preferably laterally adjacent to the semiconductor chip, more preferably substantially surrounding the semiconductor chip and most preferably completely surrounding the semiconductor chip. The high levels of cooling power provided in the small footprint package of preferred embodiments of the present invention facilitate the use of this package with packaging technologies that are sometimes considered difficult to cool. For example, it can be difficult to reliably provide heat sinking to chips in BGA (Ball Grid Array) packages. The use of the in-package cooling provided by preferred embodiments of the present invention allows a semiconductor chip to be cooled adequately even when the package provides for BGA connections. Electrical connections between the semiconductor chip and the package may be made using wire bonds or by a ball grid array interfacing with the chip, with acceptable levels of cooling being provided to the semiconductor chip. Aspects of the present invention are particularly well suited for high density, high speed semiconductor circuits such as digital signal processors, microprocessors, microcontrollers, and high density or other high performance memories. Depending on the particular configuration, aspects of the present invention may find application to multi-chip modules, although it will be apparent from the following discussion that aspects of the invention will be most advantageously applied to single chip packages. This discussion and the claims refer to a device or chip or to a semiconductor chip or device. These terms are intended to broadly encompass devices that produce heat, are of such a small scale as to require sophisticated connections like wire bonds or ball grid arrays, and which are typically encapsulated or otherwise protected from physical contact or environmental factors such as moisture.

Some aspects of the invention might be practiced with various cooling devices. The illustrated preferred embodiments described here contemplate the use of active cooling as provided by the particular form of solid-state refrigerator using the Peltier effect to achieve cooling. Peltier coolers are observed to provide desirable levels of cooling to semiconductor devices within packages. Peltier coolers can be configured according to the present invention to provide cooling while still maintaining a small footprint for the semiconductor device in combination with the package. Preferred embodiments of the present invention may use multiple Peltier devices or might use multi-stage Peltier devices. The multiple or multi-stage Peltier devices are arranged around the semiconductor chip so as to preferably surround the chip on at least two sides, more preferably on three sides and most preferably to laterally surround the chip on four sides. Pairs of N and P type Peltier devices are installed in a package (e.g., a BGA package) to surround and cool the semiconductor chip. The N and P type Peltier devices are positioned side by side and electrically driven in series to remove heat from the semiconductor device coupled to the Peltier device. By passing current through multiple Peltier device pairs, a significant amount of heat, e.g., up to 12W, can be dissipated efficiently.

FIG. 1 shows schematically a basic structure of a Peltier cooler that might be used to cool a semiconductor device. The FIG. 1 device utilizes the Peltier effect that can be achieved between a semiconductor and a metal. Cooling is achieved in this device by flowing current through positive lead 112 and out the ground lead 113. At the right of FIG. 1 is an N-type semiconductor element 114 and at the left of FIG. 1 is a P type semiconductor element 115. These Peltier elements and the other Peltier elements discussed herein might be, for example, silicon doped to a high level. A lower metal to N-type semiconductor interface 116 and an upper N- type semiconductor to metal interface 118 are provided on opposite surfaces of the N-type Peltier element 114. A lower P-type semiconductor to metal interface 117 and an upper metal to P-type semiconductor interface 118 are provided on opposite surfaces of the P-type Peltier element 115. Conductor 121 spans between the two semiconductor elements 114, 115 and provides a cool surface to which a semiconductor device could be mounted. Metal contacts 122 and 123 connect to the power terminals for the illustrated electric circuit and are also the high temperature terminals for the illustrated Peltier devices. The base (shown but not numbered) is electrically insulating, and preferably couples the hot terminals to a cooling reservoir.

In operation, electric current flows from a power source (not shown) through lead 112 into conductor 122, through the metal-semiconductor junction 116, through the N-type semiconductor, through the semiconductor to metal junction 118, and into the conductive plates 121. Due to the Peltier effect, heat is transferred from the second junction 118 to the first junction 116 of the N type Peltier device 114, i.e., in a direction opposite of the current flow. Thus, interface 116 between the conductive member 122 and the N-type Peltier device 114 is heated and the interface 118 is cooled. The current then flows from the conductive member 121 through the metal to P-type semiconductor interface 119, through the P-type Peltier device 115, through the semiconductor to metal junction 117, through conductive member 123 and out through a ground (current return) lead 113. Due to the use of a P type instead of an N type Peltier device and because of the reversed direction of current flow, cooling again occurs at the thermal interface 119 to the conductive member 121 as heat is transferred to its second thermal interface 117. Accordingly, if a semiconductor chip(s) is thermally coupled to the first conductive member 121, heat from the semiconductor chip(s) can be removed and exhausted through the conductors 122 and 123. Due to the structure of the FIG. 1 assembly, multiple ones of the illustrated assemblies can be electrically connected in series to increase the heat transfer from an upper conductive surface to conductors 122, 123 arrayed on a lower surface. Such assemblies can be formed laterally surrounding a semiconductor device to improve the ability of the Peltier cooler to remove heat from the semiconductor in a compact configuration. In such a configuration, the semiconductor device being cooled is mounted to the underside of the upper conductor that is cooled by the Peltier elements. FIGS. 2a, 2b and 2c show views of a more practical and more preferred implementation of the cooling structure of FIG. 1. The structure of FIGS. 2a, 2b, and 2c packs more densely the P-type and N-type component semiconductor devices of the embodiment of FIG. 1. The dense structure illustrated in the views of FIG. 2 increases the cooling power provided to the semiconductor chip (die 221) of FIGS. 2a, 2b and 2c. FIG. 2a shows in cross-section a BGA package including a heat sink 211 extending on one surface of the package. Typically, the heat sink is an inexpensive, highly conductive metal such as aluminum or copper. An insulating layer 213, preferably a good electrical insulator while also a good thermal conductor, is provided on the surface of the heat sink to which the semiconductor device is to be mounted. In the illustrated package, the insulator 213 is provided on the lower surface of the heat sink 211. A substrate 214, which might be a ceramic or resin header, is mounted to the insulator 213 and a semiconductor chip or device 221 is connected to the substrate 214 by thermally conductive epoxy 215. Connections to the semiconductor chip 221 are provided by wire bonding leads 239 from the bonding pads on the semiconductor chip to bonding pads on the lower face of the package adjacent the central cavity. The semiconductor chip 221 is sealed within the central cavity by an encapsulation 217.

FIG. 2a shows a cutaway view of a ball grid array (BGA) package including a Peltier cooling assembly showing the cavity and the semiconductor chip 221 mounted within the cavity. FIG. 2b shows a front side view of the assembly. FIG. 2c shows in perspective view the package including the Peltier cooling assembly forming a rectangular structure (for example, a square) around the central cavity which holds the semiconductor chip 221. In preferred aspects of the illustrated embodiment of the present invention, the Peltier cooling assembly comprises alternating N-type (e.g., devices 224, 226, 228, and 230) and P-type (225, 227, 229, and 231) semiconductor elements of Peltier devices like those discussed above with respect to FIG. 1. Conductors are provided for the various N-type and P-type Peltier elements to form a conduction path as shown in FIG. 2c, which causes the heat sink 211 to uniformly be a cool surface and causes the lower portions of the Peltier elements to heat. The heat generated by the chip is at least partially exhausted through the ball connectors of the package and to the electrical traces to which the ball conductors are connected when the chip is mounted for use on, for example, a circuit board.

Note that the conductors at the base of the package generally are not electrically connected to the bonding balls of the package. The exception to this is that particularly preferred embodiments of the invention connect the power supply Vcc a d ground supply Nss voltages for the chip to the positive 233 and ground 238 terminals of the Peltier cooler, respectively. The remaining bonding balls are most preferably thermally coupled to the adjacent Peltier elements, but are generally not electrically connected to those elements.

Input conductor 233 is provided at the base of the first Ν-type semiconductor element 224 and serves as the positive terminal of the multi-element Peltier device. As shown in FIG. 2b, bonding ball 222 is connected to the plate 233. Connecting conductors are provided to establish the desired current path through the array of semiconductors, with a shorting conductive plate on the upper surfaces of Ν-type element 224 and of P-type element 225. A conductive plate couples the bottom surfaces of P-type element 225 and Ν-type element 226, the top surfaces of Ν-type element 226 and P-type element 227, and the bottom surfaces of P-type element 227 and Ν-type element 228. A conductive plate is provided connecting the upper surfaces of Ν-type element 228 and P-type element 229, and other conductors are provided as appropriate to achieve the conduction path illustrated in FIG. 2c.

This series connection of distinct Peltier elements is used to cause heat to flow (to be pumped) by the Peltier devices from the heat sink 211 to the lower surface of the package and out through the bonding balls of the package. The semiconductor chip 221 is thus cooled through its thermal contact with the heat sink 211 at a significantly higher rate and with significantly higher cooling power than is possible using more conventional passive cooling techniques. This allows the illustrated BGA package to be used with semiconductor chips that generate large amounts of heat without the performance of the semiconductor devices within the chip to experience heating and the consequent performance degradation. In embodiments of the present invention, heat of up to 12W generated by the semiconductor chip 221 can be efficiently removed allowing continuous high performance operation without damage or malfunction of the chip.

In an additional feature of the invention, the amount of cooling and the associated power consumption to achieve this cooling can be tailored to the operating or power supply voltages of the semiconductor chip. For example, in some systems the power supply voltage can be altered, i.e., decreased, to decrease power consumption of the semiconductor device. When this occurs, less cooling will be needed. Alternately, a given package might be useful for a number of different chips because the heat generated by different chips varies with the power supply voltages supplied to the different chips. Therefore, if the same or a corresponding decreased power supply voltage 222 is supplied to the cooling assembly of the present invention, it will decrease its cooling and power assumption accordingly. In other environments, the clock supplied to the semiconductor device can be decreased (throttled back) to reduce the semiconductor's power consumption. Accordingly, the voltage 222 supplied to the cooling assembly can be decreased consistent with the supplied clock frequency. Circuitry (not shown) to provide this decreased voltage 222 can be formed as a portion of the semiconductor chip or elsewhere in a system.

In another embodiment shown in FIGS 3a-3c, a semiconductor chip 321 is provided with flip chip connections and is mounted on a lower surface of a cavity. The semiconductor chip is mounted via a ball grid array (BGA) to a substrate providing leads that connect the chips BGA connections to the BGA bonding balls of the package. Preferably, the substrate is electrically insulative but thermally conductive so that heat can flow from the semiconductor chip both through the electrical conductors or traces within the substrate but also through the substrate itself. Heat is exhausted in the embodiment of FIGS. 3a-3c through the heat sink 311. Thus, the direction of heat flow in the FIG. 3 package needs to be reversed from that described in reference to the package of FIG 2. Accordingly, current is flowed through the assembly of Peltier elements so that lower junctions of the Peltier devices are cooled and the upper junctions heat.

As the individual elements of the FIG. 3 embodiment are similar to the similarly numbered elements of the FIG. 2 embodiment, the direction of current flow through the series of N-type and P-type Peltier elements is altered from that provided in the FIG. 2 embodiment. This is effected by providing different positive and ground connection to the series of Peltier elements and by providing different shorting electrical conductors between adjacent N-type and P-type Peltier elements. In the embodiment of FIGS. 3a-3c, a positive voltage Vcc 322 is provided through a conductor 334 at the bottom of the N-type Peltier device 324 at the beginning of the series of NP Peltier devices. After entering the N type Peltier device 324, Vcc 322 is transmitted through a conductor 332 at the bottom of N type Peltier device 324 and to the bottom of P-type Peltier element 325. Conductor 332 connects to conductor 333 at the bottom of P type Peltier device 325 and current passes through the series of Peltier devices as previously described until it exits through electrode 323 at the bottom of P type Peltier device 331. Due to the direction of current flow, heat is transferred from the lower surface of the package, where the semiconductor 321 is located, to the heat sink 311 where the heat is dissipated into the air. As with the embodiment of FIGS. 2a-2c, it is possible to couple the power supply voltages for the chip and the power supply voltages of the Peltier coolers. This allows the cooling power of the Peltier cooler to be varied with the power supply voltages provided to the semiconductor chip.

The present invention provides an improved apparatus for cooling a semiconductor chip by essentially surrounding the semiconductor device with a series of pairs of Peltier devices. The apparatus of the present invention can be installed internally in the package of a semiconductor device (e.g., in a BGA package). Additionally, the described cooling apparatus provides an increased cooling capability, e.g., to 12W, adjustable in accordance with the heat generated by the semiconductor device. While the present invention has been described with particular emphasis on certain preferred embodiments of the present invention, the present invention is not limited to the particular embodiments described herein. Those of ordinary skill will appreciate that certain modifications and variations might be made to the particular embodiments of the present invention while remaining within the teachings of the present invention. For example, while the use of the present invention in combination with a BGA type semiconductor package has been shown, one of ordinary skill would appreciate its applicability to other types of semiconductor packaging. As such, the scope of the present invention is to be determined by the following claims.

Claims

I claim:

1. A package, comprising: a plurality of Peltier devices arranged to define a cooling surface and a heated surface; the Peltier devices arranged adjacent a cavity, the cavity adapted to hold a semiconductor device in thermal communication with the cooling surface, the cavity provided in a manner whereby electrical connections can be made between a semiconductor device within the cavity and the package; a first Peltier connection to one of the Peltier devices for receiving an electrical current from a power source; a second Peltier connection to another one of the Peltier devices for returning the electrical current to the power source; and electrical couplings between the Peltier devices such that the electrical current passes from the first Peltier connection to the second Peltier connection through a plurality of the Peltier devices, wherein passage of the electrical current cools the cooling surface. the electrical couplings are positioned to direct the electrical current to flow through the N type Peltier devices in a first direction between the first and second surfaces and to direct the electrical current to flow through the P type Peltier devices in an opposite direction and thereby cause heat to be transferred between the first and second surfaces.

2. The package of claim 1 , wherein first and second device power connections are provided for the semiconductor device, the first device power connection is connected to the first Peltier connection and the second device power connection is connected to the second Peltier connection.

3. The package of claim 1 , further comprising ball grid array package connections on a lower surface of the package.

4. The package of claim 3, wherein heat flow out of the package is coupled through the ball grid array.

5. The package of claim 3, wherein the cavity is provided with a mounting surface for accepting a semiconductor device having an array of connections provided on a face of the semiconductor device and wherein the mounting surface is thermally coupled to the cooling surface.

6. The package of claim 5, further comprising a heat sink on an upper surface of the package, the upper surface in an opposite position to the ball grid array package connections.

7. The package of claim 1, further comprising a semiconductor device within the cavity and encapsulation filling the cavity around the semiconductor device.

8. The package of claim 1, further comprising a mounting surface for supporting the semiconductor device wherein the mounting surface is coupled to the cooling surface of the Peltier devices, wherein the electrical couplings are positioned to cause heat to be transferred from the cooling surface to the heated surface of the Peltier devices.

9. The package of claim 1 wherein the first Peltier connection is coupled to a lower surface of an N-type Peltier device and the second Peltier connection is coupled to a lower surface of a Ptype Peltier devices.

10. The package of claim 1 wherein the Peltier devices are arranged in an essentially rectangular pattern to define an essentially rectangular cavity.

11. The package of claim 1 , wherein the Peltier devices surround the cavity.

12. The apparatus of claim 1 wherein the Peltier devices are arranged in an essentially square pattern to define an essentially square cavity.

13. The apparatus of claim 12 comprised of four P type Peltier devices and four N type Peltier devices.

14. A package for a semiconductor device, comprising: a first pair of Peltier devices comprising: an N-type Peltier device defining an upper and a lower surface; a P-type Peltier device defining an upper and a lower surface corresponding to the upper and lower surfaces of the N-type Peltier device; an electrically conductive member for providing an electrical connection between the upper surfaces of the N-and P-type Peltier devices, said conductive member additionally providing a thermally conductive path to remove heat from a semiconductor device; a first electrical connection to the lower surface of the N-type Peltier device for receiving an electrical current from the power source; and a second electrical connection to the lower surface of the P-type Peltier device for returning an electrical current to the power source, wherein in response to electrical current serially passing through the Peltier devices, each of the Peltier devices causes heat to be transferred from the conductive member to the lower surface of each Peltier device.

15. The package of claim 14, comprising a plurality of pairs of Peltier devices arranged to define an inner cavity and wherein the semiconductor device is mounted within the cavity.