WO2000022763A1 - Node control unit of an access node in a synchronous telecommunication system and method for controlling a switchover of clock supply in a telecommunication system - Google Patents
Node control unit of an access node in a synchronous telecommunication system and method for controlling a switchover of clock supply in a telecommunication system Download PDFInfo
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- WO2000022763A1 WO2000022763A1 PCT/EP1998/006477 EP9806477W WO0022763A1 WO 2000022763 A1 WO2000022763 A1 WO 2000022763A1 EP 9806477 W EP9806477 W EP 9806477W WO 0022763 A1 WO0022763 A1 WO 0022763A1
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- 230000001360 synchronised effect Effects 0.000 title claims abstract description 19
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- 102100040837 Galactoside alpha-(1,2)-fucosyltransferase 2 Human genes 0.000 claims abstract description 14
- 101000893710 Homo sapiens Galactoside alpha-(1,2)-fucosyltransferase 2 Proteins 0.000 claims abstract description 14
- 101000882403 Staphylococcus aureus Enterotoxin type C-2 Proteins 0.000 claims abstract description 14
- 101000882406 Staphylococcus aureus Enterotoxin type C-1 Proteins 0.000 claims abstract description 10
- 101000868154 Homo sapiens Son of sevenless homolog 2 Proteins 0.000 claims abstract description 6
- 102100032930 Son of sevenless homolog 2 Human genes 0.000 claims abstract description 6
- 102100032303 26S proteasome non-ATPase regulatory subunit 2 Human genes 0.000 claims description 37
- 101000590272 Homo sapiens 26S proteasome non-ATPase regulatory subunit 2 Proteins 0.000 claims description 37
- 238000012544 monitoring process Methods 0.000 claims description 16
- 230000007547 defect Effects 0.000 claims description 12
- 230000003213 activating effect Effects 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 claims 2
- 238000001514 detection method Methods 0.000 claims 1
- 101100404726 Arabidopsis thaliana NHX7 gene Proteins 0.000 abstract 1
- 108700022176 SOS1 Proteins 0.000 abstract 1
- 101100197320 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RPL35A gene Proteins 0.000 abstract 1
- 102100032929 Son of sevenless homolog 1 Human genes 0.000 abstract 1
- 101150100839 Sos1 gene Proteins 0.000 abstract 1
- 102100026973 Heat shock protein 75 kDa, mitochondrial Human genes 0.000 description 18
- 101710204707 Transforming growth factor-beta receptor-associated protein 1 Proteins 0.000 description 18
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0057—Operations, administration and maintenance [OAM]
- H04J2203/006—Fault tolerance and recovery
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
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Abstract
The invention relates to a node control unit (NCU) in a synchronous telecommunication system to which is associated a second node control unit (NCU). In order to permit a fast switchover from a node clock in a first node control unit to a node clock in the second node control unit, if the working node control unit fails, the node control unit comprises - a hardware block (TRAP) in each node control unit (NCU) for generating control signals according to received failure signals, the hardware blocks (TRAP) being mutually interlinked by control lines (SOS1, SOS2) for informing the inactive node control unit (NCU) to take over and - control lines (A, B) being associated with each node control unit (NCU) for transferring a status information about each node clock (SEC1, SEC2) from said hardware blocks (TRAP) to all tributary units (TU). The invention relates equally to a method for carrying out the switching.
Description
Node control unit of an access node in a synchronous telecommunication system and method for controlling a switchover of clock supply in a telecommunication system
The invention relates to a node control unit forming part of an access node in a synchronous telecommunication system, being selected as a first (master) node control unit for regular clock supply of tributary units, to which is associated a second (slave) node control unit for alternative clock supply of the tributary units, each node control unit including a node clock, a monitoring unit for monitoring different hardware units (e.g. node clock, ASIC, oscillator) and outputting interrupts in case of detected failures in one of the hardware units, a software unit for receiving the interrupts outputted by the monitoring unit and for evaluating whether the interrupts indicate a failure. The invention equally relates to a method for controlling in a telecommunication system a switchover of clock supply.
Synchronized or partly synchronized telecommunication networks like SDH (synchronous digital hierarchy) networks operate at least in parts of the system with completely synchronized transmissions. Sometimes there is even provided a synchronization between different telecommunication networks. Node clocks forming part of node control units of an access node have to take care of the synchronous operating of all elements within the network or networks or within all subsystems. A protection of this synchronous operating is essential for the desired continuous synchronous operation. To this end, to each working (or master) node clock in a first
node control unit (NCU) there is usually associated a second protecting (or slave) node clock in another node control unit, which is designed for and capable of taking over the clocking if necessary.
Fig. 1 shows a known clock distribution system of an access node. Both, a working node control unit NCUl and a protecting node control unit NCU2 consist of a phase locked loop for the synchronous equipment clock (SEC- PLL) , a reference clock (EXT)-PLL and a selector logic, which is only roughly indicated in figure 1. The units have four 2 Mbit/s interfaces operating independently from the node control units, each of the 2 Mbit/s interfaces being usable as a reference for the respective node clock. Additionally, there are provided two reference clock lines RCKL1,RCKL2 for distributing reference clock signals from a receiver unit to the master node control unit NCUl and the slave node control unit NCU2. Furthermore, a first node clock distribution line NCLK1 is reserved for the master node clock and a second node clock distribution line NCLK2 is reserved for the slave node clock. Two tributary units TU1,TU2 are shown, each receiving clocking from the node clock distribution line NCKL1/NCKL2 that is provided with the clock (SEC) of the presently activated node control unit NCU1/NCU2. The tributary units can be, e.g., POTS/ISDN tributary units TU1 or 2M tributary units TU2. System software of the master node control unit NCUl that is responsible for node synchronization continuously selects the best reference in the node for use for the PLLs . During normal operation, the output of the slave node clock is deactivated, but the state of the slave software is regularly updated by the master software.
There are several reasons which can make a switchover between the working node clock of a first node control unit and the protecting node clock of a second node control unit necessary:
The active master unit in which the node clock for the regular supply is located has to be removed from time to time for maintenance purposes. In this case the operator determines the time when a switch from the regular node control unit to the protection node control unit is to be carried out. The protective unit is activated via a service terminal and after that it is possible to remove the old master unit. Thereby, time gaps between deactivation of the first node clock and activation of the second clock can be avoided.
In other cases, though, the time for the switching over cannot be planned beforehand. For example, a master unit may have to be removed from the sub-rack because of some installation failure. Moreover, an internal hardware failure can be detected by the system so that a change of the master unit by an automatic protection switching becomes necessary. Finally, the start of updated software, which is currently usually done through a reset, may cause discontinuity in the system clock signal .
Presently, software based messages are used to initiate a switch over.
The problem of such a software-controlled switching-over is that in case of unpredictable necessities of switching over, quite a time may pass after the first node clock is not functioning any more and before the switching to the second node clock is actually carried out, possibly
leading to severe problems in the synchronization of the system.
It is an object of the invention to provide node control units for access nodes in a telecommunication network and a method permitting a fast switchover from a working node clock in a first node control unit to a protecting node clock in a second node control unit, if an essential element of the working node control unit fails.
This object is achieved by a node control unit according to the preamble, comprising
- a hardware block in each node control unit for generating control signals according to received signals from the software unit and hardware units, the hardware blocks being mutually interlinked by first control lines for informing the presently inactive node control unit to take over the node clock supply from the presently active node control unit and
- further control lines being associated with each node control unit for transferring a status information about each node clock from said hardware blocks to all tributary units.
The object is equally achieved by a method for controlling in a telecommunication system a switchover of clock supply to tributary units from an active node control unit to an inactive node control unit, both capable of supplying a clocking signal, each node control unit comprising a hardware block which are both used for controlling the switchover, comprising the steps of:
- in case of a detected failure in the presently active node control unit, requesting the hardware block of the presently inactive node control unit to take over clock supply from the presently active node control unit by
the hardware block of the presently active node control unit; - informing all connected tributary units by the hardware blocks via control lines that the node clock of the previously inactive node clock unit has to be used as clock source.
The advantage of the access node and the method according to the invention is that they offer a very fast response time in case of a failure of the working clock, thereby minimizing the interruption of the clock supply. The number of control lines on the back-plane is moreover minimized.
The operation of the software is simplified for an access node or a method according to the invention. The software is responsible to ensure that all conditions in the node are fulfilled to move to a "protected waiting mode". After that the hardware is responsible to take care of a switch over if needed. After a switch over, all unnecessary software components of the old master unit are shut down and the necessary software components of the old slave unit, which is now the new master unit, are started.
Preferred embodiments of the invention are apparent from the dependent claims.
The invention is explained in more detail with reference to the drawings of which
Fig. 1 shows a clock distribution system of a known access node;
Fig. 2 shows a preferred embodiment of an implementation of the automatic hardware switching according to the invention;
Fig. 3 shows a flow-chart illustrating the automatic protection switching in a preferred embodiment of the invention;
Fig. 4 shows the state machine of an embodiment of a hardware block according to the invention; and
Fig. 5 shows the slot allocation in an access node sub- rack system.
The clock distribution system of figure 1 has already been described with relation to the state of the art.
Figure 2 shows an access node clock distribution system in a synchronous telecommunication network. It comprises two identical node control units, one of them being designated as master (NCUl) and the other as slave (NCU2) node control unit. Each node control unit comprises a software unit μPl, μP2 which is used also as unit protection manager, a hardware block TRAP1,TRAP2 generating all back-plane control signals, a node clock SEC1,SEC2 of which PLL and reference signals are not shown. Surveying units of node clock functions, ASICs and oscillators are connected to a monitoring unit MU1,MU2 providing an input for the software unit μPl, μP2. Other monitoring units are connected to the software unit μPl, μP2 as well (connection not shown) . The software unit μPl, μP2 has several signal lines (S -EN, FORCE,M/S, GIVE- UP, READ-BACK, DEFECT, SW-RESET) to the hardware block TRAP1,TRAP2. The output of the surveying unit of the power supply is directly connected to an input of the hardware block TRAP1,TRAP2. An output of the hardware block TRAP1,TRAP2 is supplied to driver elements DR1,DR2,
e.g. LVT drivers, inserted at the output of the node clock SEC1,SEC2 and of an additional one-state signal.
Dedicated first control lines SOSl,SOS2 form a connection between the hardware blocks TRAP1 of node control unit NCUl and TRAP2 of node control unit NCU2.
There are provided two node clock lines NCLK1,NCLK2. Node clock line NCLK1 is exclusively used for providing the signal of node clock SEC1 of the master node control unit NCUl. Node clock line NCLK2 is exclusively used for providing the signal of node clock SEC2 of the slave node control unit NCU2. Additionally, there are provided two further control lines A and B carrying information about the status of node clock line NCLK1 and node clock line NCLK2, respectively.
The status of node clock, ASICs and oscillators are monitored by a monitoring unit MU1,MU2 generating interrupts that are passed on to the unit protection manager, the functions of which are realized by the software unit μPl, μP2. According to the received interrupts and other information like manual inputs, the software unit μPl, μP2 outputs control bits to the hardware block TRAP1,TRAP2. To the respective bits transmitted in each connection is assigned the following information:
S -EN
0: switching controlled by hardware diagnostic functions
1: switching controlled by software using FORCE signal
FORCE
0: node clock driver DR1,DR2 active
1: node clock driver DR1,DR2 inactive
M/S
0: the unit is configured as slave unit when protection is initialized 1: the unit is configured as master unit when protection is initialized
GIVE-UP
0: hardware controlled operation enabled
1: hardware controlled operation disabled
DEFECT
0: received interrupt interpreted as message of fatal failure by unit protection manager 1: no failure status detected by unit protection manager
The state of the power supply is passed on directly to the hardware block TRAP1,TRAP2:
HW-RESET
0: hardware reset on, too low operating voltage
1: hardware reset not active, normal operating voltage
Via an additional line, a signal READ-BACK can be transmitted back from the hardware block TRAP1,TRAP2 to the unit protection manager for confirming some input to the hardware block TRAP1,TRAP2, e.g., if the hardware block TRAP1 of the master node control unit NCUl is really set to master or if some failure-information transmitted via DEFECT or HW-RESET bits was received by the hardware block TRAP1.
The signals transmitted via control lines SOSl,SOS2 between the hardware blocks TRAP1,TRAP2 of the two node
control units NCU1,NCU2 can also have two different states. Only the signal from the presently active node control unit (as signal SOS-OUT) to the present stand-by node control unit (as signal SOS-IN) is of relevance.
SOS-IN of slave (identical to SOS-OUT of master)
0: master has detected a fatal failure
1: operation of the master is normal and unit protection manager monitoring is running; no failure information to be delivered to slave
Another signal of importance for the inventive access node is the driver enable signal DR_EN transmitted from the hardware block TRAP1,TRAP2 to the driver of the node clock SEC1,SEC2 for its access to the assigned node clock line NCLK1,NCLK2 and to the driver DR1,DR2 via which a signal is transmitted to control line A in case of node control unit NCUl and to control line B in case of node control unit NCU2. If this signal DR_EN has the value "0" no signal is transmitted to the respective node clock line NCLK1,NCLK2 and to the respective control line A, B. If DR_EN has the value "1" the output of the node clock SEC1,SEC2 is transmitted to the respective node clock line NCLK1, NCLK2 and the control line A, B receives the signal that the assigned node clock line NCLK1, NCLK2 is supplied with the clock signal that is to be used.
Control lines A, B are monitored both within each node control unit NCU1,NCU2 with the possibility to generate an interrupt signal. If both lines are "1" it indicates that both NCUs try to be master NCU. If both lines are "0" it means that the inactive NCU has not made a successful switch-over.
Further connections of the node control units NCU1,NCU2 to the node clock access lines NCLK1,NCLK2 and the control lines A, B are drawn with dotted lines. These illustrate the possibility to use a certain node control unit either for a first node clock access line NCLK1 and a first control line A or alternatively for a second node clock access line NCLK2 and a second control line B so that a flexible implementation is possible.
In addition to the node control units NCU1,NCU2 and clock and control lines NCLK1, NCLK2,A,B, SOSl, SOS2, a tributary unit TU is shown. The tributary unit TU comprises a reference table RT which receives inputs from control lines A and B. The reference table RT is connected to one of the selectable inputs of a selector SELl for selecting between the output of the reference table RT and software based information. Selector SELl is connected to a second selector SEL2 for selecting between an input of signals from node clock line NCLK1 and NCLK2.
The operating of the system is described in the following with reference to figures 2 and 3.
The user has selected a non revertive protection mode and wants to activate the node clock protection by inputting an clock protection activation command. The system software, which is responsible for automatic switching, receives this command and checks, if the general node configuration supports a node clock protection. Moreover, the unit protection manager checks if both node control units NCU1,NCU2 work properly.
The system is now ready to activate the automatic protection mode. It is not yet clear, though, that all conditions needed for giving control to the hardware
block are met. Therefore, the hardware control is first masked by setting the GIVE-UP bit transmitted by each of the unit protection managers to the master and slave hardware block TRAP1,TRAP2 respectively to "1", until the whole status of the protection function is checked. The unit protection manager of the master unit sets the M/S bit to "1" and the unit protection manager of the slave unit sets the M/S bit to "0". This is necessary, because the hardware blocks TRAP1,TRAP2 have different tasks when operating in an active node control unit NCUl or in an protecting node control unit NCU2. The unit protection manager can check additionally that the READ-BACK signal of the master hardware block TRAP1 is "1". This means that there is no protection switching request.
The software units μPl, μP2 both set the GIVE-UP bit to hardware blocks TRAP1,TRAP2 of master and slave units NCU1,NCU2 to "0", signalizing that the software is ready to give up control to the hardware and has moved to an automatic protection state. In this state the unit protection manager of the master unit NCUl monitors and analyzes the incoming interrupts from the hardware. The unit protection manager software has several diagnostic functions to monitor the status of the hardware. Typically, a hardware block generates an interrupt and the unit protection manager filters and verifies the source of the alarm. If the alarm means fatal hardware failure, the unit protection manager can trigger the automatic protection with the DEFECT signal. As long as no fatal failure is detected the unit protection manager transmits a DEFECT bit of "1" to the hardware block TRAP1. As soon as a fatal failure is detected, unit protection manager sets the DEFECT bit to "0".
Another kind of triggering of the automatic switching is taking place in case of a hardware reset as consequence of a power failure or in case of a failure signal as result of some other hardware monitoring. The necessary signal either comes directly from a power monitoring unit with a HW-RESET bit changing from "1" to "0" or from a unit watch-dog circuit or from another fast HW-monitoring circuit. Some voltages, though, are monitored by software, e.g. voltages of +12V.
If the master hardware block TRAPl receives either a DEFECT bit of "0" or a HW-RESET bit of "0" it starts the automatic switching. Additionally, a SW-RESET-signal, which is controlled by a WATCH-DOG and informs about a software failure, can initialize an automatic switching.
The hardware block TRAPl of the master unit NCUl sets the DR_EN bit and the SOS-OUT bit, which previously were both "1", to "0". The bus drivers of the master unit for node clock line NCLK1 and control line A are consequently deactivated, preventing thereby the supply of the clocking signal of node clock SEC1 to node clock line NCLK1 and an "NCLK1 active" signal to control line A. Both NCUs can verify the switch-over status from A and B lines with their monitoring block. The hardware block TRAP2 of the slave unit NCU2 receives the SOS-OUT signal of the master hardware block TRAPl as SOS-IN signal for the slave hardware block TRAP2, and reacts by activating the bus drivers DR2 of the slave unit for node clock line NCLK2 and control line B. Therefore, the node clock SEC2 signal of the slave unit NCU2 is in the following supplied to node clock line NCLK2 and a "NCLK2 active" signal to control line B. The slave hardware block TRAP2 moreover generates an interrupt in order to inform the unit protection manager of the slave node control unit
NCU2 that the clocking signal is now supplied to the tributary units TU by the node clock SEC2 of the slave node control unit NCU2. In case the automatic switching had to be carried out because of a power failure, which constitutes a unit failure as indicated in figure 3, the node synchronization is now supervised by the software of the slave node control unit NCU2, after all necessary functions of the slave node control unit NCU2 have been activated. Otherwise, i.e., in case the automatic switching was caused by a DEFECT bit of "0" indicating a node clock block failure, further node synchronization can either be supervised by the software of the slave node control unit NCU2 or continue to be supervised by the software of the master node control unit NCUl (see figure 3) .
The SOS-IN port of both node clock units NCU1,NCU2 has a monostable function and therefore, additional changes at the SOS-IN pin of the slave hardware block TRAP2 do not have any effect. The monostable function is realized with a monostable flip-flop which is used for generating a "one way" triggering. The monostable flip-flop is set with the GIVE-UP signal and thereby enabled to react to a transition in its input signal once. After triggering, the flip-flop does not follow the input signal until a re-setting of the GIVE-UP signal. The hardware-controlled mode (GIVE-UP=0) is used to activate an inactive node control unit.
The control logic in the hardware blocks TRAPl, TRAP2 generating output signals DR_EN and SOS-OUT depending on the inputted signals can be designed in any suitable manner. One possibility corresponding to the depicted hardware block TRAPl, TRAP2 in figure 2 is described below.
The hardware block TRAPl, TRAP2 of each node control unit NCU1/NCU2 comprises an AND-gate A with inputs for the
DEFECT-signal from the software unit μPl, μP2, for the HW- RESET-signal and possibly for a WATCH DOG-controlled signal. The output of the AND-gate A is supplied to one input of a first OR-gate 01, of which a second input is used for the GIVE-UP-signal .
A first monostable flipflop FF1 receives two input signals, the GIVE-UP signal (R-input) and the SOS-IN signal (S-input) originating from the other hardware block TRAP2, TRAPl. The output of the first flipflop FF1 is used as input of a second OR-gate 02 together with the M/S-signal from the software unit μPl, μP2.
The output of the first OR-gate and the inverted output of the second OR-gate are used as selectable inputs (1- input and 0-input respectively) of a first selector SI. The selecting input of the selector SI is supplied with the M/S-signal. The output of the first selector SI is supplied together with the GIVE-UP signal to S-input and R-input of a second monostable flipflop FF2. A second selector S2 receives as one selectable input (0-input) the output signal of this second flipflop FF2 and as another selectable input (1-input) the FORCE-signal of the software unit μPl, μP2. The selecting input is provided by the SW-EN signal of the software unit μPl, μP2. The output of the second selector S2 is used as DR_EN-signal. The SOS-OUT signal to the hardware block TRAP2, TRAPl in the respective other node control unit NCU2,NCU1 is provided by the output of the first OR-gate 01.
The state machine of the first and the second monostable flipflop FF1,FF2 is shown in figure 4. As can be seen from the diagram, if the present output of the flipflop is "0" and the next incoming bit at the S-input of the flipflop is "0", the output of the flipflop does not change. If, on the other hand, the next incoming bit at the S-input of the flipflop is "1", the output changes to "1" . If the output of the flipflop is "1", it only changes to "0" if both, S-input and R-input, become "0" at the same time.
In case of software control of a necessary switch over, the elements of the hardware block do not have any influence at all. The second selector S2, which provides, apart from the connection to the second hardware block TRAP2, TRAPl, the only output of the hardware block TRAPl, TRAP2, lets pass only the FORCE-signal of the software unit μPl, μP2.
While checking, if hardware control of the switching is possible, continuous GIVE-UP-bits of "1" result in a DR_EN signal of "1" in case of the master node control unit NCUl and of "0" in case of the protecting node control unit NCU2, regardless of detected failures.
In the case of the master node control unit NCUl, after the GIVE-UP bit has been set to "0" by the software unit μPl, μP2, the signals informing about absence or presence of a failure (DEFECT, HW-RESET, SW-RESET) are passed and transformed via AND-gate A, first OR-gate 01, first selector SI, second flipflop FF2 and second selector S2, thereby determining the value of the signal DR_EN which is output by said second selector S2 and is used for
controlling the drivers DR1. If one of the signals DEFECT, HW-RESET or SW-RESET changes from "1" (no failure) to "0" (detected failure) , the output of the second selector S2, i.e., the DR_EN signal, changes from "1" to "0". The output of the first OR-gate, which is "1" as long as no error occurs and "0" as soon as either the DEFECT-signal, the HW-RESET-signal or the SW-RESET-signal becomes "0" as result of some failure, is used as signal SOS-OUT to the hardware block of the protecting node control unit NCUl, informing the protecting unit NCU2 about the current state of the protected unit NCUl.
The hardware block TRAP2 of the protecting node control unit NCU2 does not evaluate failure signals (DEFECT, HW- RESET) , but its SOS-IN signal, which is equal to the SOS- OUT signal of the master node control unit NCUl. The incoming SOS-IN signal is passed and transformed via first flipflop FF1, inverter, first selector SI, second flipflop FF2 and second selector S2, resulting in the appropriate value of the DR_EN signal used for controlling drivers DR2.
The values of signals within the hardware blocks can be monitored at several places. In the shown case, the output of the second flipflop FF2, which is equal to the signal DR_EN in case of hardware control, and the input of the first flipflop, which is equal to the SOS-IN signal, are monitored. A change of the monitored signals leads to an interrupt to the software unit μPl, μP2, thereby giving information, that a switchover has taken place.
The tributary units TU continuously check, whether there is a signal on control line A or control line B. The
reference table RT permits to determine which of the node clock lines NCLK1,NCLK2 has to be used for synchronization. Either this information or information provided by software, depending on the selection by selector SELl, is used to select via selector SEL2, which of the node clock lines NCLK1,NCLK2 is actually to be used by the tributary unit TU.
Figure 5 shows the fixed and the dynamic configuration of the clock and control buses managed by node control units NCU1,NCU2. In an access node sub-rack system a node control unit can be installed in either of the existing slots. More than two node control units may be installed at the same time to the node. Also two node control units and further units with different functionalities like tributary units may be installed in one sub-rack. The system software is responsible for choosing two fixed node control units to work as logical node control units. Usually this fixed configuration is changed only, when units are installed to the sub-rack. The two selected units are configured as master and slave units by the system software. The unit protection manager can activate and deactivate master and slave unit dynamically according to the failure restoration situation in the node .
In figure 5, the sub-rack system comprises 8 buses SOSl SOS2, NCLK1, NCLK2, MFSY1, MFSY2, A and B. Node control units with access to these buses are installed in slot 1 and slot 4, the node control unit in slot 1 being configured as master unit and node control unit in slot 4 being configured as slave unit. Additionally, slot 2 is used for a tributary unit. Slot 3 is not used. In a fixed configuration, a certain slot has to be used for a certain unit. Using a dynamic configuration, on the other
hand, the operator can select freely, which slot is to be used for which unit. The necessary connections to the buses can be provided dynamically. The node control unit of slot 1 is connected bi-directionally to node clock access line NCLK1, to multiframe synchronization frame line MFSY1 and control line A. Furthermore, there is provided a connection from control line B to the unit and from the unit to control line S0S2. These are all connections needed as long as the node control unit is used as working unit. The node control unit inserted in slot 4 only has a bi-directional connection to control line B. Additionally, there is an input from MFSY1, from control line A and SOSl. The units in both slots 1 and 4 may have additional connections from NCLK1 and NCLK2 to the unit for reasons of supervision. The described configuration is only changed, when the presently protecting unit becomes the working unit because of some fatal failure in the presently working unit.
In a fixed configuration it would be necessary to additionally and continuously provide all connections that are needed as soon as the protecting unit becomes the working unit and the former working unit is exchanged by a protecting unit.
Other units inserted in the remaining two slots are connected according to necessity. In figure 5, the used tributary unit has incoming connections from control lines A and B, from node access line NCLK1 (dynamically switched to node access line NCLK2 if the clock supplying unit is changed) and multiframe synchronization frame line MFSY1.
Claims
1. Node control unit (NCUl) forming part of an access node in a synchronous telecommunication system, being selected as a first (master) node control unit (NCUl) for~ regular clock supply of tributary units (TU) , to which is associated a second (slave) node control unit (NCU2) for alternative clock supply of the tributary units (TU) , each node control unit (NCU1,NCU2) including a node clock (SEC1,SEC2), a monitoring unit (MU1,MU2) for monitoring different hardware units (e.g. node clock, ASIC, oscillator) and outputting interrupts in case of detected failures in one of the hardware units, a software unit (μPl, μP2) for receiving the interrupts outputted by the monitoring unit (MU1,MU2) and for evaluating whether the interrupts indicate a failure, c h a r a c t e r i z e d b y
- a hardware block (TRAPl, TRAP2) in each node control unit (NCU1,NCU2) for generating control signals according to received signals from the software unit (μPl, μP2) and hardware units, the hardware blocks (TRAPl, TRAP2) being mutually interlinked by first control lines (SOSl,SOS2) for informing the presently inactive node control unit (NCU2,NCU1) to take over the node clock supply from the presently active node control unit (NCU1,NCU2) and
- further control lines (A, B) being associated with each node control unit (NCU1,NCU2) for transferring a status information about each node clock (SEC1,SEC2) from said hardware blocks (TRAPl, TRAP2) to all tributary units
(TU) .
2. Node control unit (NCU1,NCU2) forming part of an access node in a synchronous telecommunication system according to claim 1, c h a r a c t e r i z e d i n t h a t means (S2,SW-EN) are provided for selecting either a hardware triggered switching or a software triggered switching between two node control units (NCU1,NCU2) .
3. Node control unit (NCU1,NCU2) forming part of an access node in a synchronous telecommunication system according to claim 1 or claim 2, c h a r a c t e r i z e d i n t h a t the monitoring system providing interrupts to the software units (μPl, μP2) has inputs for signals at least from node clock (SEC1,SEC2) or ASIC or oscillator or power supply or control lines (A, B) .
4. Node control unit (NCU1,NCU2) forming part of an access node in a synchronous telecommunication system according to one of the preceding claims, c h a r a c t e r i z e d i n t h a t the hardware block (TRAPl, TRAP2) has input lines originating from the software unit (μPl, μP2), for a signal (SW-EN) indicating whether software or hardware is supposed to be in control, for a signal (FORCE) for controlling node drivers if software has the control, for a signal (M/S) for determining which of the node control units (NCU1,NCU2) is master and which is slave in case of hardware control, a signal (GIVE-UP) for disabling / activating automatic switching and a signal (DEFECT) for indicating a fatal failure determined by software unit (μPl, μP2), and input lines coming from the power supply for a signal (HW-RESET) indicating a hardware reset.
5. Node control unit (NCU1,NCU2) according to one of the preceding claims, c h a r a c t e r i z e d i n t h a t each hardware block (TRAPl, TRAP2) comprises
- a first monostable flipflop (FF1) which is supplied with status-information by the hardware block
(TRAP2, TRAPl) of a second node control unit (NCU2,NCU1) and which is connected via an inverter and a selector (SI) to a second monostable flipflop (FF2) and
- an AND-gate (A) , which is supplied with status- information concerning the state of supervised elements of the access node and which is connected via said selector (SI) to said second monostable flipflop (FF2), and to the first monostable flipflop (FF2) of the hardware block (TRAP2, TRAPl) of said second node control unit (NCU2,NCU1) for forwarding the status information of the supervised elements of the access node, said selector (SI) letting pass the signals coming from the AND-gate (A) in case of a master node control unit (NCUl) and letting pass the signals from the first monostable flipflop (FF1) in case of the slave master node control unit (NCU2), the output of the second monostable flipflop (FF2) enabling or disabling the clock supply of tributary units and activating and deactivating the control lines (A, B).
6. Access node in a synchronous telecommunication system, comprising node control units (NCU1,NCU2) according to one of the preceding claims, c h a r a c t e r i z e d i n t h a t each tributary unit (TU) connected to the access node comprises inputs from control lines (A, B) connected to a reference table (RT) which outputs information about which node clock line (NCLK1,NCLK2) has to be used to a selector (SEL2) via which either signals from the first node clock line (NCLK1) or from the second node clock line (NCLK2) are read and transmitted to the elements of the tributary unit (TU) .
7. Access node in a synchronous telecommunication system, comprising node control units (NCU1,NCU2) according to one of the preceding claims, c h a r a c t e r i z e d b y a sub-rack system including at least four slots in each of which a node control unit (NCU1,NCU2) can be installed, one of the at least two installed node control units (NCU1,NCU2) being selected for regular clock supply and another one (NCU2,NCU1) for alternative clock supply.
8. Method for controlling in a telecommunication system a switchover of clock supply to tributary units (TU) from an active node control unit (NCUl) to an inactive node control unit (NCU2) , both capable of supplying a clocking signal, each node control unit (NCU1,NCU2) comprising a hardware block (TRAPl, TRAP2) which are both used for controlling the switchover, comprising the steps of:
- in case of a detected failure in the presently active node control unit (NCUl), requesting the hardware block
(TRAP2) of the presently inactive node control unit (NCU2) to take over clock supply from the presently active node control unit (NCUl) by the hardware block (TRAPl) of the presently active node control unit (NCUl) ;
- informing all connected tributary units (TU) by the hardware blocks (TRAPl, TRAP2) via control lines (A, B) that the node clock (SEC2) of the previously inactive node clock unit (NCU2) has to be used as clock source.
9. Method for controlling in a telecommunication system a switchover of clock supply according to claim 8, each of the node control units being associated to a node clock access line (NCLKl,NCLK2) , comprising the steps of:
- detection of necessity of a switchover by hardware or software,
- the software unit (μPl) or a power supply monitoring unit of the first node control unit (NCUl) informs the hardware block (TRAPl) of the first node control unit
(NCUl) about a failure,
- the hardware block (TRAPl) of the first node control unit (NCUl) disables the access of the first node control unit (NCUl) to the assigned node clock access line (NCLKl) and informs the software unit (μPl) of the first node control unit (NCUl)
- request to the second node control unit (NCU2) by the first node control unit (NCUl) to take over clock supply;
- the hardware block (TRAP2) of the second node control unit (NCU2) enables the access of the second node control unit (NCU2) to the assigned node clock access line (NCLK2) and informs the software unit (μP2) of the second node control unit (NCU2)
- information of all connected tributary units (TU) via control lines (A, B) accessible by the node clock units (NCU1,NCU2) and the tributary units (TU) that the node clock (SEC2) of the second node clock unit (NCU2) has to be used as clock source;
- switching of the clock supply input of all tributary units (TU) to the node clock access line (NCLK2) connected to the node clock (SEC2) of the second node clock unit (NCU2) .
10. Method according to claim 8 or 9, c h a r a c t e r i z e d b y the following preceding steps:
- transmitting of clock protection activation command from user to the system software,
- system software checks that general node configuration supports node clock protection,
- the software units (μPl, μP2) of the first and the second node control units (NCU1,NCU2) check that both node clock units (NCU1,NCU2) work properly,
- the software units (μPl, μP2) check that there is no protection switching request before HW-controlled operation is launched.
11. Method according to one of the claims 8-10, c h a r a c t e r i z e d i n t h a t the switching back to the first node control unit (NCUl) is carried out by software and can be revertive or non- revertive.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP1998/006477 WO2000022763A1 (en) | 1998-10-13 | 1998-10-13 | Node control unit of an access node in a synchronous telecommunication system and method for controlling a switchover of clock supply in a telecommunication system |
| AU11533/99A AU1153399A (en) | 1998-10-13 | 1998-10-13 | Node control unit of an access node in a synchronous telecommunication system and method for controlling switchover of clock supply in a telecommunication system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP1998/006477 WO2000022763A1 (en) | 1998-10-13 | 1998-10-13 | Node control unit of an access node in a synchronous telecommunication system and method for controlling a switchover of clock supply in a telecommunication system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2000022763A1 true WO2000022763A1 (en) | 2000-04-20 |
Family
ID=8167094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP1998/006477 WO2000022763A1 (en) | 1998-10-13 | 1998-10-13 | Node control unit of an access node in a synchronous telecommunication system and method for controlling a switchover of clock supply in a telecommunication system |
Country Status (2)
| Country | Link |
|---|---|
| AU (1) | AU1153399A (en) |
| WO (1) | WO2000022763A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001089122A2 (en) * | 2000-05-18 | 2001-11-22 | Enterasys Networks, Inc. | Method and system for distributed clock failure protection in a packet switched network |
| EP1217771A2 (en) * | 2000-12-23 | 2002-06-26 | Alcatel | Method, clock supply device and receiver module for synchronization |
| EP1675290A1 (en) * | 2004-12-23 | 2006-06-28 | Alcatel | A redundant synchronous clock distribution system |
| US8442195B2 (en) | 2004-05-27 | 2013-05-14 | Huawei Technologies Co., Ltd. | Method for controlling process of establishing call |
| CN112106033A (en) * | 2018-04-30 | 2020-12-18 | 思睿逻辑国际半导体有限公司 | Communication circuit and control circuit thereof |
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|---|---|---|---|---|
| US5570397A (en) * | 1993-12-23 | 1996-10-29 | Unisys Corporation | Redundant synchronized clock controller |
| US5577075A (en) * | 1991-09-26 | 1996-11-19 | Ipc Information Systems, Inc. | Distributed clocking system |
| US5631931A (en) * | 1993-03-29 | 1997-05-20 | Hitachi, Ltd. | Bus type clock supplying system for providing a clock in a communication system with a plurality of clock bus lines |
| WO1998004064A1 (en) * | 1996-07-19 | 1998-01-29 | Nokia Telecommunications Oy | Master-slave synchronisation |
-
1998
- 1998-10-13 WO PCT/EP1998/006477 patent/WO2000022763A1/en active Application Filing
- 1998-10-13 AU AU11533/99A patent/AU1153399A/en not_active Abandoned
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5577075A (en) * | 1991-09-26 | 1996-11-19 | Ipc Information Systems, Inc. | Distributed clocking system |
| US5631931A (en) * | 1993-03-29 | 1997-05-20 | Hitachi, Ltd. | Bus type clock supplying system for providing a clock in a communication system with a plurality of clock bus lines |
| US5570397A (en) * | 1993-12-23 | 1996-10-29 | Unisys Corporation | Redundant synchronized clock controller |
| WO1998004064A1 (en) * | 1996-07-19 | 1998-01-29 | Nokia Telecommunications Oy | Master-slave synchronisation |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001089122A2 (en) * | 2000-05-18 | 2001-11-22 | Enterasys Networks, Inc. | Method and system for distributed clock failure protection in a packet switched network |
| WO2001089122A3 (en) * | 2000-05-18 | 2003-08-14 | Enterasys Networks Inc | Method and system for distributed clock failure protection in a packet switched network |
| US6754171B1 (en) | 2000-05-18 | 2004-06-22 | Enterasys Networks, Inc. | Method and system for distributed clock failure protection in a packet switched network |
| EP1217771A2 (en) * | 2000-12-23 | 2002-06-26 | Alcatel | Method, clock supply device and receiver module for synchronization |
| EP1217771A3 (en) * | 2000-12-23 | 2004-11-03 | Alcatel | Method, clock supply device and receiver module for synchronization |
| US8442195B2 (en) | 2004-05-27 | 2013-05-14 | Huawei Technologies Co., Ltd. | Method for controlling process of establishing call |
| EP1675290A1 (en) * | 2004-12-23 | 2006-06-28 | Alcatel | A redundant synchronous clock distribution system |
| US7457388B2 (en) | 2004-12-23 | 2008-11-25 | Alcatel | Redundant synchronous clock distribution system |
| CN112106033A (en) * | 2018-04-30 | 2020-12-18 | 思睿逻辑国际半导体有限公司 | Communication circuit and control circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| AU1153399A (en) | 2000-05-01 |
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