WO1999056508A1 - Rigid interconnect device and method of making - Google Patents

Rigid interconnect device and method of making Download PDF

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Publication number
WO1999056508A1
WO1999056508A1 PCT/US1999/009101 US9909101W WO9956508A1 WO 1999056508 A1 WO1999056508 A1 WO 1999056508A1 US 9909101 W US9909101 W US 9909101W WO 9956508 A1 WO9956508 A1 WO 9956508A1
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WO
WIPO (PCT)
Prior art keywords
layer
larc
rigid
interconnect device
hole
Prior art date
Application number
PCT/US1999/009101
Other languages
French (fr)
Inventor
Timothy J. Schmitt
Original Assignee
Compunetics, Inc.
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Filing date
Publication date
Application filed by Compunetics, Inc. filed Critical Compunetics, Inc.
Priority to AU40696/99A priority Critical patent/AU4069699A/en
Publication of WO1999056508A1 publication Critical patent/WO1999056508A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A rigid interconnect device (10) includes a first layer (20) having a first side (14) and a second side (16). The first layer (20) is made of LARC-SI. The second side (16) has electrical circuitry (18). Second layer (24) has a first side (14) and a second side (16). The second layer is made of LARC-SI. The first side (14) of the second layer is in contact with the second side (16) of the first layer. A method for producing this device is also disclosed which includes the step of depositing LARC-SI onto a rigid substrate (12). Then, the LARC-SI is cured to form first layer (20). The first side (14) of this layer is in contact with the rigid substrate (12).

Description

RIGID INTERCONNECT DEVICE AND METHOD OF MAKING
FIELD OF THE INVENTION
The present invention is related to rigid interconnect devices. More specifically, the present invention is related to rigid interconnect devices having at least one dielectric layer of LARC-SI or an aromatic high performance thermoplastic polyimide with a unique combination of physical, mechanical and adhesive properties derived from NASA's LARC-SI product such as Robon, Genymer, etc.
BACKGROUND OF THE INVENTION
More complex rigid interconnect devices have multiple conductive layers, each having circuitry. For each conductive layer to operate properly, each conductive layer must be isolated in a controlled manner from the other conductive layers. This means that a non-conductive or dielectric layer must exist between each of the conductive layers to electrically insulate the electrically conductive layers from each other.
Although the conductive layers need to be isolated from each other, they still must be able to electrically communicate with each other. Communication is typically accomplished with holes containing conductive material with conductive material that extend between conductive layers through the non-conductive (dielectric) layer. Materials that will serve as non-conductive (dielectric) layers always are being sought. Such material needs to be easily workable and applied, drillable, have good electrical characteristics, ease of processing, application, etc., long term reliability, ease of hole formation, to name but a few desired properties for such a non-conductive material. The present invention involves a new type of non-conductive (dielectric) material for the non-conductive layer of rigid interconnect devices, such as the printed circuit board, multi -chip modules, chip scale packages, all chip packages, etc.
SUMMARY OF THE INVENTION
The present invention pertains to a rigid interconnect device. The rigid interconnect device comprises a first layer having a first side and an opposing second side. The first layer is made of LARC-SI and has electrical circuitry. The rigid interconnect device comprises a second layer having a first side and an opposing second side. The second layer is made of LARC-SI. The first side of the second layer is in contact with the second side of the first layer.
The present invention pertains to a method for producing a rigid interconnect device. The method comprises the steps of depositing LARC-SI onto a rigid substrate. Then there is the step of curing the LARC-SI so it forms a first layer having a first side and an opposing second side. The first side of the first layer is in contact with the rigid substrate
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings, the preferred embodiment of the invention and preferred methods of practicing the invention are illustrated in which:
Figure 1 is a schematic representation of a cross sectional view of the rigid interconnect device of the present invention.
DETAILED DESCRIPTION
Referring now to the drawings wherein like reference numerals refer to similar or identical parts throughout the several views, and more specifically to figure 1 thereof, there is shown a rigid interconnect device 10. The rigid interconnect device 10 comprises a first layer 20 having a first side 14 and an opposing second side 16. The first layer 20 is made of LARC-SI. The second side 16 has electrical circuitry 18. The opposing side 16 may also have circuitry. Or they may both not have, or have circuitry. The first layer 20 can be deposited on a rigid substrate 12. The rigid interconnect device 10 comprises a second layer 24 having a first side 14 and an opposing second side 16. The second layer 24 is made of LARC-SI. The first side 14 of the second layer 24 is in contact with the second side 16 of the first layer 20.
LARC-SI is described in U.S. Patent No. 5,639,850; and U.S. patent applications 08/359,752 and 08/527,000 titled "Process for Preparing a Tough, Soluble, Thermoplastic Copolyimide" , "Tough, Soluble, Aromatic Copolyimide" , and "Process for Preparing an Ultra-Thin, Adhesiveless, Multi-Layered Polymer Substrate", respectively, all of which are incorporated by reference herein.
Preferably, the first and second layers have at least one hole 22 extending continuously through them from the second side 16 of the second layer 24 to the first layer 20. Preferably, it will extend just through layer 24 connecting the second side of layer 24 to the second side of layer 20. The hole 22 is plated with metal so the second side 16 of the second layer 24 is in electrical communication with the first side 14 of the first layer 20 and/or the second side of layer 20.
The rigid interconnect device 10 includes a third layer 26 having a first side 14 and an opposing second side 16. The third layer 26 is made of LARC-SI. The first side 14 of the third layer 26 is in contact with the second side 16 of the second layer 24.
Preferably, the first, second and third layers have at least one hole 22 extending continuously through them from the second side 16 of the third layer 26 to the first layer 20. It can extend from the top down to any layer or group of layers directly beneath it. The hole 22 is plated with metal so the second side 16 of the third layer 24 is in electrical communication with the first side 14 of the first layer 20.
The rigid interconnect device 10 preferably includes a fourth layer 28 having a first side 14 and an opposing second side 16. The fourth layer 28 is made of LARC-SI. The first side 14 of the fourth layer 28 is in contact with the second side 16 of the third layer 26. Preferably, the first, second, third and fourth layers have at least one hole 22 extending continuously through them from the second side 16 of the fourth layer 28 to the first layer 20. It can extend from the top down to any layer or group of layers directly beneath it. The hole 22 is plated with metal so the second side 16 of the fourth layer 28 is in electrical communication with the first side 14 of the first layer 20.
The rigid interconnect device 10 preferably includes a fifth layer 30 having a first side 14 and an opposing second side 16. The fifth layer 30 is made of LARC-SI. The first side 14 of the fifth layer 30 is in contact with the second side 16 of the fourth layer 28.
Preferably, the first, second, third, fourth and fifth layers have at least one hole 22 extending continuously through them from the second side 16 of the fifth layer 30 to the rigid substrate. It can extend from the top down to any layer or group of layers directly beneath it. The hole 22 is plated with metal so the second side 16 of the fifth layer 30 is in electrical communication with the first layer 20. Preferably, the second side 16 of the first, second, third, fourth and fifth layers have circuitry 18.
The present invention pertains to a method for producing a rigid interconnect device 10. The method comprises the steps of depositing LARC-SI onto a rigid substrate. Then there is the step of curing the LARC-SI so it forms a first layer 20 having a first side 14 and an opposing second side 16. The first side 14 of the first layer 20 is in contact with the rigid substrate 12. Preferably, before the depositing step, there is the step of forming circuitry 18 on the rigid substrate 12. After the curing step, there is preferably the step of forming at least one hole 22 extending through the rigid substrate 12 and the first layer 20 from the second side 16 of the first layer 20 to the rigid substrate 12. It should be noted that hole 22 may not go through both layers. It may only go from the second side of layer 20 to the second side of layer 12.
Preferably, after the forming the hole 22 step, there is a step of plating the hole 22 with metal. The forming the hole 22 step preferably includes the step of drilling the hole 22 through the rigid substrate and second layer although it may not go through all layers with a laser although other techniques could be used also. Preferably, the depositing step includes the step of coating the LARC-SI on the rigid substrate 12. The depositing step alternatively can include the step of spraying (or other deposition technique) the LARC-SI on to the rigid substrate 12.
In the operation of the preferred embodiment, the rigid interconnect device 10 is formed first by coating LARC- SI onto a rigid substrate 12. The LARC-SI is coated onto the rigid substrate 12 by well known techniques. The LARC-SI is allowed to cure to form a first layer 20 having a first side 14 and an opposing second side 16. The first side 14 of the first layer 20 is in contact with the rigid substrate 12 after the LARC-SI has cured.
The second side 16 of the first layer 20 has circuitry 18 formed on it by well known techniques. Holes 22 that extend only through the rigid substrate 12 and first layer 20 are then drilled by well known techniques. The holes 22 extending through the rigid substrate 12 and first layer 20 from the second side 16 of the first layer 20 to the rigid substrate 12 are then plated with copper by well known techniques although it may not go through all layers. This is not limited to plating copper. Can plate any metal or use non-plating methods of adding conductivity. In this way, the plated holes 22 provide for electrical communication between the second side 16 of the first layer 20 and the rigid substrate 12.
A second layer 24 of LARC-SI is then placed onto the second side 16 of the first layer 20. The second layer 24 of LARC-SI can be placed onto the first layer 20 by well known techniques, or an adhesive can be coated onto the second side 16 of the first layer 20 and the first side 14 of the second layer 24 placed into contact with the second side 16 of the first layer 20 by well known techniques. Other well known techniques of placing LARC-SI onto an already existing layer can also be used. The second side 16 of the second layer 24 has circuitry 18 formed in them by well known techniques. Holes 22 that only extend through the rigid substrate 12, first layer 20 and the second layer 24 are then drilled by well known techniques although it may not go through all layers. The holes 22 extending through the rigid structure 12, first layer 20 and second layer 24 from the second side 16 of the second layer to the rigid substrate 12 are then plated with copper, by well known techniques. In this way, the plated holes 22 provide for electrical communication between the second side 16 of the second layer 24 and rigid substrate 12.
LARC-SI is then sprayed (although other deposition techniques can be used) on the second side 16 of the second layer 24 by well known techniques. The LARC-SI is allowed to cure to form a third layer 26 having a first side 14 and an opposing second side 16. The first side 14 of the third layer 26 is in contact with the second side 16 of the second layer 24. Holes 22 that extend only through the rigid substrate 12, first layer 20, second layer 24 and third layer 26 are then drilled by well known techniques although it may not go through all layers. The holes 22 extending through the rigid substrate 12, the first layer 20, second layer 24 and third layer 26 from the second side 16 of the third layer 26 to the rigid substrate 12 are then plated with copper by well known techniques. In this way, the plated holes 22 provide for electrical communication between the second side 16 of the third layer 26 and the rigid substrate 12.
The fourth layer 28 of LARC-SI can be applied onto the third layer 26 by well known techniques, or an adhesive can be coated onto the second side 16 of the third layer 26 and the first side 14 of the fourth layer 28 placed into contact with the second side 16 of the third layer 26 by well known techniques. Other well known techniques of placing LARC-SI onto an already existing layer can also be used. The second side 16 of the fourth layer 28 has circuitry 18 formed in them by well known techniques. Holes 22 that only extend through the rigid substrate 12, first layer 20, second layer 24, third layer 26 and fourth layer 28 are then drilled by well known techniques although it may not go through all layers. The holes 22 extending through the rigid substrate 12, first layer 20, second layer 24, third layer 26 and fourth layer 28 from the second side 16 of the fourth layer 28 to the first side 14 of the first layer 20 are then plated with copper, by well known techniques. In this way, the plated holes 22 provide for electrical communication between the second side 16 of the fourth layer 28 and the first side 14 of the first layer 20.
The process of adding additional layers of circuitry or of LARC-SI, as described above, can be repeated as is necessary until a rigid interconnect device 10 having as many layers as desired is formed.
Four major processes are involved in processing LARC-SI
1) The application of the LARC-SI material
2) Hole formation
3) Creation of electrical conductivity in holes 4) Addition of conductive circuitry to the surface of the LARC-SI layer
APPLICATION OF LARC-SI
LARC-SI can be applied to the surface of any rigid substrate composed of any conductive or nonconductive material . The nonconductive substrate may or may not have conductive circuitry on its surface. The LARC-SI material can also be applied in a sequential fashion to the surface of a previously applied layer of it self (a new substrate) which may or may not have conductive circuitry on its surface.
a) The LARC-SI material may be laminated in sheet form under heat and pressure in a suitable pressing apparatus . The LARC-SI may be cured during or after this process.
b) The LARC-SI material can be sprayed to the surface of a substrate layer from a liquid form with suitable spraying equipment. It can then be cured in a subsequent operation.
c) The LARC-SI material can be applied to the surface of a substrate in a liquid form with suitable roller coating equipment and cured in a subsequent operation.
d) The LARC-SI material can be applied to the surface of a substrate in a liquid form with suitable curtain coating equipment or applied by dip coating and cured in a subsequent operation.
e) The LARC-SI material can be applied to the surface of a substrate in a powder form using suitable powder application equipment and cured in a subsequent operation.
HOLE FORMATION
Holes may be formed in the LARC-SI material by any of the following methods:
a) Holes may be created in the LARC-SI material by means of mechanical drilling using drill bits and suitable drilling equipment .
b) Holes may be created in the LARC-SI material by means of laser abiation using suitable laser equipment.
c) Holes may be created in the LARC-SI material by means of plasma etching using suitable plasma equipment and suitable masking material to expose the hole sites .
d) Holes may be created in the LARC-SI material by means of chemical etching. The chemistry used may be any solution that would effectively remove the LARC-SI material when it is in the uncured state. An appropriate mask will be used to expose the hole sites in this situation. Curing of the material will take place in a subsequent operation.
CREATION OF ELECTRICAL CONDUCTIVITY IN HOLES
The above-mentioned holes would have to be made electrically conductive to allow electrical communication between the conductive circuitry of different layers. This may be accomplished in any of the following manners:
a) Electrical conductivity of the holes may be accomplished by chemical deposition of copper using any traditional copper plating processes. These include full build electroless copper plating, electroless followed by electrolytic plating, and any seed plating followed by electrolytic plating.
b) Electrical conductivity of the holes may be accomplished by filling the holes with any type of conductive epoxy material .
c) Electrical conductivity of the holes may be accomplished by vacuum deposition or any sputtering of conductive material in the hole . ADDITION OF COPPER TO THE SURFACE OF LARC-SI MATERIAL
Copper which is required for the conductive circuitry on the surface of the LARC-SI material may be applied in any of the following manners:
a) Deposition of the copper may be accomplished by traditional chemical deposition of copper using any copper plating processes. These include full build electroless copper plating, electroless followed by electrolytic plating.
b) Deposition of the copper may be accomplished by vacuum deposition or any sputtering of copper on the surface of the LARC-SI.
LARC-SI was developed by NASA as an extremely robust adhesive material. There was no intention by NASA of using the material in any electronics application. However, because of its unique, strong adhesive nature, it is highly suitable for rigid interconnects, because each layer must adhere extremely well to the substrate or previous layer. In fact, when applying LARC-SI on top of another layer of LARC-SI and curing, the two layers chemically combine to form one large layer with no interface as is common in other methods. This attribute is an advantage because any interface between the two layers is susceptible to delaminating in future thermal cycles of assembly of electrical components. In addition, it has all the necessary electrical parameters for high speed digital performance. LARC-SI can be obtained from PAR Technologies through Virginia Power Company.
Although the invention has been described in detail in the foregoing embodiments for the purpose of illustration, it is to be understood that such detail is solely for that purpose and that variations can be made therein by those skilled in the art without departing from the spirit and scope of the invention except as it may be described by the following claims.

Claims

WHAT IS CLAIMED IS
1. A rigid interconnect device comprising:
a first layer having a first side and an opposing second side, said first layer made of LARC-SI; and
electrical circuitry disposed on the second side.
2. A rigid interconnect device as described in Claim 1 including a second layer having a first side and an opposing second side, said second layer made of LARC-SI, said first side of the second layer in contact with the second side of the first layer.
3. A rigid interconnect device as described in Claim 2 wherein the first and second layers have at least one hole extending continuously through them from the second side of the second layer to the first side of the first layer, said hole plated with metal so the second side of the second layer is in electrical communication with the first side of the first layer.
4. A rigid interconnect device as described in Claim 3 including a third layer having a first side and an opposing second side, said third layer made of LARC-SI, said second side of said third layer having electrical circuitry, said first side of said third layer in contact with said second side of said second layer.
5. A rigid interconnect device as described in Claim 4 wherein the first, second and third layers having at least one hole extending continuously through them from the second side of the third layer to the first side of the first layer, said hole plated with metal so the second side of the third layer is in electrical communication with the first side of the first layer.
6. A rigid interconnect device as described in Claim 5 including a fourth layer having a first side and an opposing second side, said fourth layer made of LARC-SI, said first side of said fourth layer in contact with the second side of the third layer.
7. A rigid interconnect device as described in Claim 6 wherein the first, second, third and fourth layers having at least one hole extending continuously through them from the second side of the fourth layer to the first side of the first layer, said hole plated with metal so the second side of the fourth layer is in electrical communication with the first side of the first layer.
8. A rigid interconnect device as described in Claim 7 including a fifth layer having a first side and an opposing second side, said fifth layer made of LARC-SI, said second side of said fifth layer having circuitry, said first side of said fifth layer in contact with said second side of said fourth layer.
9. A rigid interconnect device as described in Claim 8 wherein the first, second, third, fourth and fifth layers having at least one hole extending continuously through them from the second side of the fifth layer to the first side of the first layer, said hole plated with metal so the second side of the fifth layer is in electrical communication with the first side of the first layer.
10. The rigid interconnect device as described in Claim 9 wherein said second side of the second and fourth layers having circuitry.
11. A method for producing a rigid interconnect device comprising the steps of:
depositing LARC-SI onto a rigid substrate; and
curing the LARC-SI so it forms a first layer having a first side and an opposing second side, said first side of the first layer in contact with the rigid substrate.
12. A method as described in Claim 10 including after the curing step, there is the step of forming circuitry on the second side of the first layer.
13. A method as described in Claim 12 including after the curing step, there is the step of forming at least one hole extending through the first layer and the rigid substrate .
14. A method as described in Claim 13 including after the forming the hole step, there is a step of plating the hole with metal .
15. A method as described in Claim 13 wherein the forming the hole step includes the step of drilling the hole through the first and second layers with a laser.
16. A method as described in Claim 14 wherein the depositing step includes the step of coating the LARC-SI on to the rigid substrate.
17. A method as described in Claim 14 wherein the depositing step includes the step of spraying the LARC-SI on to the rigid substrate .
PCT/US1999/009101 1998-04-29 1999-04-27 Rigid interconnect device and method of making WO1999056508A1 (en)

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US6903998A 1998-04-29 1998-04-29
US09/069,039 1998-04-29

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Cited By (1)

* Cited by examiner, † Cited by third party
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FR2938970A1 (en) * 2008-11-26 2010-05-28 St Microelectronics Rousset METHOD FOR STACKING AND INTERCONNECTING INTEGRATED CIRCUITS
US8034713B2 (en) 2008-11-26 2011-10-11 Stmicroelectronics (Rousset) Sas Method for stacking and interconnecting integrated circuits
EP2192612A3 (en) * 2008-11-26 2012-04-04 STMicroelectronics Rousset SAS Method for stacking and interconnecting integrated circuits
US8487422B2 (en) 2008-11-26 2013-07-16 Stmicroelectronics (Rousset) Sas Chip stack with conductive column through electrically insulated semiconductor region

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