WO1999017546A1 - Image-in-image processor - Google Patents

Image-in-image processor Download PDF

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Publication number
WO1999017546A1
WO1999017546A1 PCT/DE1998/002833 DE9802833W WO9917546A1 WO 1999017546 A1 WO1999017546 A1 WO 1999017546A1 DE 9802833 W DE9802833 W DE 9802833W WO 9917546 A1 WO9917546 A1 WO 9917546A1
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Prior art keywords
image
picture
decimation
filter
processor according
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PCT/DE1998/002833
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German (de)
French (fr)
Inventor
Maik Brett
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Siemens Aktiengesellschaft
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Publication of WO1999017546A1 publication Critical patent/WO1999017546A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Definitions

  • Picture-in-picture processors for television sets which allow a second, smaller picture to be inserted into a picture which is displayed in full screen. This allows the viewer to watch what is happening in a second program in addition to the first television or video program which is shown full screen, for example in order to be able to change the channel in good time at the beginning of an expected program or after the end of an advertising block in the second program. It cannot be avoided that the viewer finds the lack of a part of the picture of the first program disturbing, and the more so, the more he is interested in the first program.
  • the optimal format of the superimposed image cannot be clearly stated, but that it depends on factors such as the screen size or the ratio of screen size to the distance between the viewer and the device or even purely subjective factors such as the degree of interest of the viewer depends on one program or another.
  • Conventional picture-in-picture processors are unable to address this problem.
  • the corresponding received image signal In order to generate the reduced image to be faded in, the corresponding received image signal must be decimated, the decimation ratio being determined by the size ratio of the faded-in image to the full-format image.
  • the filter characteristics required for optimal filtering depend on the decimation factor or the image size. Since the implementation of variable filter characteristics in a digital decimation filter has so far been technically complex, it has been sufficient to use very simple filters with, for example, the same weighting or filters with a fixed and therefore unchangeable filter characteristic, which do indeed apply to a specific decimation ratio of the faded in The image delivered good results, but in the case of deviating decimation ratios either the sharpness of the image was reduced or alias interference was not adequately suppressed. These filters only provide optimal results for a single size of the displayed image.
  • Filters can be approximated well and theoretically calculated. The use of these filters for picture-in-picture purposes is not mentioned.
  • the object of the invention is to provide a picture-in-picture processor which can be used for a plurality of sizes of the superimposed picture with unchanged good picture quality.
  • FIG. 1 is a block diagram of a picture-in-picture processor with a decimation filter containing a CIC filter
  • FIG. 2 shows the decimation filter from FIG. 1 with an upstream low-pass filter and a downstream frequency response correction device.
  • FIG. 1 shows a circuit arrangement for an example of a picture-in-picture processor according to the invention.
  • This comprises two inputs 1, 2 for a first and a second image signal, a decimation filter 3, which is connected to the first input and, connected in series, contains two integrator stages 5, a first switch 7 and two subtractor stages 9, an image memory 11 and a second switch 13 and one Control circuit 15, which controls the operation of the switches 7, 13 and the image memory 11 in dependence on synchronization signals of the first and second image signals and external signals.
  • a first integrator stage 5 receives image data of a first program via the first input at a clock rate T. It comprises a register 4 and an adder 6, which adds the content of the register 4 to each received data value.
  • the register 4 connected to the output of the adder 6 is a shift register with a memory location which is clocked at the clock T of the incoming signal and thus outputs its output value to the input of the adder 6 with a clock period T delay.
  • the adder 6 has a wrap-around arithmetic, which skips from the largest to the smallest representable numbers or vice versa in the event of an overflow.
  • the transfer function of integrator stage 5 is
  • a second, identically constructed integrator stage 5 is connected in series with the first.
  • Other configurations of the picture-in-picture processor according to the invention may differ with regard to the number of integrator stages 5.
  • the switch 7 is closed by the control circuit 15 during one of M cycles, the rest of the time it is open. Only one out of every M sequence values is passed through, i.e. the data is decimated by a factor of M. On the behind the behind the
  • the switch 7 is followed by two subtracting stages 9. Like the integrator stages 5, these each contain an adder 6 and a register 4, the output of which is connected to a first input of the adder 6. However, the adder 6 of the subtracting stage 9 takes into account the data value at its first input with the opposite sign, and the input of the register 4 is connected to the second input of the adder 6.
  • the register 4 of the subtraction stage 9 like that of the integrator stage 5, has a memory location. However, since the data rate behind the switch 7 is reduced by the factor M, this space is sufficient to cause a delay by M clock periods.
  • the individual subtraction stage 9 thus has the transfer function
  • the transfer function of the filter 3 adapts automatically to decimation factors and thus allows a better suppression of alias interference.
  • An image memory 11 is connected to the output of the second comb stage 9. This is also controlled by the timing control circuit 15 and is used to buffer the decimated image data and to synchronize it with the image of the second program received via input 2.
  • the image data of the second program and the decimated data output by the image memory are combined with the aid of a switch 13 which is also controlled by the control circuit 15 to form an image-in-image signal.
  • the switch 13 is connected to the input 2 in the first half of the line period and to the image memory 11 in the second.
  • the control circuit 15 causes the image memory to output the buffered image lines one after the other at the clock rate T to the switch 11 during the connection time.
  • the control circuit can be designed so that it
  • a more uniform picture-in-picture processor according to the invention can advantageously be used for televisions with any screen sizes and, accordingly, different preferred sizes of the displayed picture, without any adjustments to the decimation filter being necessary beyond the selection of the decimation ratio would be.
  • the control circuit it is also easily possible to design the control circuit so that it is a z.
  • B receives a freely selectable decimation ratio in a range from 2 to 5 and controls switches and image memories accordingly.
  • the invention is in no way limited to the number of two integrator and comb stages 5, 9 used in the example above. Depending on the requirements for alias suppression and other parameters familiar to the filter designer, a different number of levels can be selected.
  • the decimation filter 3 of FIG. 1 is expanded on the input side and on the output side.
  • a low-pass filter 20 or, generally speaking, a pre-filter is arranged at the input and is connected on the output side to the input of the first integrator 5 of the CIC filter.
  • a frequency response correction device 30 is coupled to the output of the last subtraction stage 9 of the CIC filter.
  • the CIC filter is necessary to ensure that it is adapted to the different image sizes of the image to be displayed.
  • the decimation filter relates primarily to horizontal decimation; vertical decimation can be done by weighting / accumulating the lines.
  • the entire implementation of the decimation filter can be designed in terms of block circuitry as in FIG. 2.
  • the low-pass filter 20 is used to filter out interference and the output-side frequency response correction device 30 is used for frequency response correction.

Abstract

An image-in-image processor comprises two inputs (1,2) for each television or video image signal, a decimation filter (3) with a CIC filter for decimating data pertaining to one of two image signals and a switch (13) which receives the second image signal and the output signal of the decimation filter (3) and combines them into a combined image signal, whereby a partial area of the second image is replaced by a smaller first image.

Description

Beschreibungdescription
Bild-in-Bild-ProzessorPicture-in-picture processor
Es sind Bild-in-Bild-Prozessoren für Fernsehgeräte bekannt, die es gestatten, in ein bildschirmfüllend angezeigtes Bild ein zweites, kleineres Bild einzufügen. Dies gestattet es dem Zuschauer, neben dem bildschirmfüllend wiedergegebenen ersten Fernseh- oder Videoprogramm das Geschehen in einem zweiten Programm mitzuverfolgen, beispielsweise um rechtzeitig zu Beginn einer erwarteten Sendung oder nach Ablauf eines Werbe- blocks im zweiten Programm den Kanal wechseln zu können. Dabei läßt sich nicht vermeiden, daß der Zuschauer das Fehlen eines Teils des Bildes des ersten Programms als störend emp- findet, und zwar um so mehr, je höher sein Interesse am ersten Programm ist .Picture-in-picture processors for television sets are known which allow a second, smaller picture to be inserted into a picture which is displayed in full screen. This allows the viewer to watch what is happening in a second program in addition to the first television or video program which is shown full screen, for example in order to be able to change the channel in good time at the beginning of an expected program or after the end of an advertising block in the second program. It cannot be avoided that the viewer finds the lack of a part of the picture of the first program disturbing, and the more so, the more he is interested in the first program.
Dem ließe sich zwar dadurch begegnen, daß man ein kleines Format für das eingeblendete Bild wählt, doch darf es wieder- um nicht so klein werden, daß wichtige Details nicht mehr erkennbar sind oder das Bild der Aufmerksamkeit des Zuschauers ganz entgeht, weil er sich unwillkürlich auf das erste Programm konzentriert .This could be countered by choosing a small format for the displayed image, but it must not be so small that important details are no longer recognizable or the image completely escapes the viewer's attention because he involuntarily focused on the first program.
Man erkennt, daß das optimale Format des eingeblendeten Bildes nicht eindeutig angegeben werden kann, sondern daß es von Faktoren wie etwa der Bildschirmgröße oder dem Verhältnis von Bildschirmgröße zum Abstand Zuschauer-Gerät oder sogar rein subjektiven Faktoren wie dem Grad des Interesses des Zuschau- ers am einen oder anderen Programm abhängt. Herkömmliche Bild-in-Bild-Prozessoren sind nicht in der Lage, diesem Problem Rechnung zu tragen. Um das einzublendende verkleinerte Bild zu erzeugen, muß das entsprechende empfangene Bildsignal dezimiert werden, wobei das Dezimationsverhältnis durch das Größenverhältnis des eingeblendeten Bilds zum voll- formatigen Bild bestimmt ist. Um Aliasstörungen im verkleinerten Bild zu vermeiden, ist es notwendig, das Bildsignal in Verbindung mit der Dezimation geeignet zu filtern, um Frequenzen oberhalb der halben Abtastfrequenz des dezimierten Bilds hinreichend zu unterdrücken. Die für eine optimale Filterung erforderlichen Filtercharakteristiken hängen ab vom Dezimationsfaktor bzw. von der Bildgröße. Da die Realisierung variierbarer Filtercharakteristiken in einem digitalen Dezimationsfilter bislang technisch aufwendig war, hat man sich damit begnügt, sehr einfache Filter mit z.B. gleicher Gewich- tung oder Filter mit einer festen und damit nicht veränderbaren Filtercharakteristik zu verwenden, die zwar für ein bestimmtes Dezimationsverhältnis des eingeblendeten Bildes gute Ergebnisse lieferten, bei denen jedoch bei abweichenden Dezi- mationsverhältnisen entweder die Bildschärfe reduziert war oder Aliasstörungen nicht hinreichend unterdrückt wurden. Diese Filter liefern nur für eine einzige Größe des eingeblendeten Bildes optimale Ergebnisse verwendbar.It can be seen that the optimal format of the superimposed image cannot be clearly stated, but that it depends on factors such as the screen size or the ratio of screen size to the distance between the viewer and the device or even purely subjective factors such as the degree of interest of the viewer depends on one program or another. Conventional picture-in-picture processors are unable to address this problem. In order to generate the reduced image to be faded in, the corresponding received image signal must be decimated, the decimation ratio being determined by the size ratio of the faded-in image to the full-format image. In order to avoid alias interference in the reduced image, it is necessary to appropriately filter the image signal in connection with the decimation in order to adequately suppress frequencies above half the sampling frequency of the decimated image. The filter characteristics required for optimal filtering depend on the decimation factor or the image size. Since the implementation of variable filter characteristics in a digital decimation filter has so far been technically complex, it has been sufficient to use very simple filters with, for example, the same weighting or filters with a fixed and therefore unchangeable filter characteristic, which do indeed apply to a specific decimation ratio of the faded in The image delivered good results, but in the case of deviating decimation ratios either the sharpness of the image was reduced or alias interference was not adequately suppressed. These filters only provide optimal results for a single size of the displayed image.
Durch Hogenauer, „An Economical Class of Digital Filters for Decimation and Interpolation", IEEE Trans. Acoust . , Speech, Signal Processing Bd. ASSP-29, 1981, S. 155 sind sogenannte CIC-Filter^ (Cascaded j.ntegrator-comb filter) bekannt geworden. Diese werden empfohlen zur Datendezimation bei hohen De- zimationsverhältnissen, bei denen das Antwortverhalten derBy Hogenauer, "An Economical Class of Digital Filters for Decimation and Interpolation", IEEE Trans. Acoust., Speech, Signal Processing Vol. ASSP-29, 1981, p. 155, so-called CIC filters ^ (Cascaded j.ntegrator-comb filter), which are recommended for data decimation at high decimation ratios where the response behavior of the
Filter sich gut approximieren und theoretisch berechnen läßt . Die TAnwendung dieser Filter für Bild- im-Bild- Zwecke ist nicht erwähnt .Filters can be approximated well and theoretically calculated. The use of these filters for picture-in-picture purposes is not mentioned.
Aufgabe der Erfindung ist, einen Bild-in-Bild-Prozessor anzu- geben, der für eine Mehrzahl von Größen des eingeblendeten Bildes bei unverändert guter Bildqualität verwendbar ist.The object of the invention is to provide a picture-in-picture processor which can be used for a plurality of sizes of the superimposed picture with unchanged good picture quality.
Die Lösung dieser Aufgabe wird gelöst durch einen Bild-in- Bild-Prozessor nach Anspruch 1.This object is achieved by a picture-in-picture processor according to claim 1.
Unteransprüche betreffen vorteilhafte Ausgestaltungen des erfindungsgemäßen Bild-in-Bild-Prozessors .Subclaims relate to advantageous refinements of the picture-in-picture processor according to the invention.
Nachfolgend wird die Erfindung mit Bezug auf ein Ausführungs- beispiel und zwei Figuren näher erläutert. Es zeigen:The invention is explained in more detail below with reference to an exemplary embodiment and two figures. Show it:
Fig. 1 ein Blockschaltbild eines Bild-im-Bild-Prozessors mit einem ein CIC-Filter enthaltenden Dezimationsfilter, und1 is a block diagram of a picture-in-picture processor with a decimation filter containing a CIC filter, and
Fig.2 das Dezimationsfilter von Fig. 1 mit vorgeschaltetem Tiefpaß und nachgeschalteter Frequenzgangkorrektureinrichtung .2 shows the decimation filter from FIG. 1 with an upstream low-pass filter and a downstream frequency response correction device.
Fig. 1 zeigt eine Schaltungsanordnung für ein Beispiel eines erfindungsgemäßen Bild-in-Bild-Prozessor. Dieser umfaßt zwei Eingänge 1, 2 für ein erstes und ein zweites Bildsignal, ein Dezimationsfilter 3, das an den ersten Eingang angeschlossen ist und hintereinander geschaltet zwei Integratorstufen 5, einen ersten Schalter 7 und zwei Subtrahierstufen 9 enthält, einen Bildspeicher 11, einen zweiten Schalter 13 sowie eine Steuerschaltung 15, die den Betrieb der Schalter 7, 13 und des Bildspeichers 11 in /Abhängigkeit von Synchronisations- signalen des ersten und zweiten Bildsignals und externen Signalen steuert .1 shows a circuit arrangement for an example of a picture-in-picture processor according to the invention. This comprises two inputs 1, 2 for a first and a second image signal, a decimation filter 3, which is connected to the first input and, connected in series, contains two integrator stages 5, a first switch 7 and two subtractor stages 9, an image memory 11 and a second switch 13 and one Control circuit 15, which controls the operation of the switches 7, 13 and the image memory 11 in dependence on synchronization signals of the first and second image signals and external signals.
Eine erste Integratorstufe 5 empfängt Bilddaten eines ersten Programms über den ersten Eingang mit einer Taktrate T. Sie umfaßt ein Register 4 und einen Addierer 6, der zu jedem empfangenen Datenwert den Inhalt des Registers 4 hinzuaddiert. Das an den Ausgang des Addierers 6 angeschlossene Register 4 ist ein Schieberegister mit einem Speicherplatz, das mit dem Takt T des eintreffenden Signals getaktet ist und somit dessen Ausgabewert jeweils mit einer Taktperiode T Verzögerung an den Eingang des Addierers 6 ausgibt . Der Addierer 6 hat eine Wrap-Around-Arithmetik, die bei Überlauf von den größten zu den kleinsten darstellbaren Zahlen oder umgekehrt überspringt . Die Übertragungsfunktion der Integratorstufe 5 istA first integrator stage 5 receives image data of a first program via the first input at a clock rate T. It comprises a register 4 and an adder 6, which adds the content of the register 4 to each received data value. The register 4 connected to the output of the adder 6 is a shift register with a memory location which is clocked at the clock T of the incoming signal and thus outputs its output value to the input of the adder 6 with a clock period T delay. The adder 6 has a wrap-around arithmetic, which skips from the largest to the smallest representable numbers or vice versa in the event of an overflow. The transfer function of integrator stage 5 is
Hi(z) = 1/d-z"1) .Hi (z) = 1 / dz " 1 ).
Eine zweite, identisch aufgebaute Integratorstufe 5 ist mit der ersten in Reihe geschaltet. Andere Ausgestaltungen des erfindungsgemäßen Bild-in-Bild-Prozessors können hinsichtlich der Zahl der Integratorstufen 5 abweichen.A second, identically constructed integrator stage 5 is connected in series with the first. Other configurations of the picture-in-picture processor according to the invention may differ with regard to the number of integrator stages 5.
Die Integratoren 5 erzeugen aus einer Folge von Eingangsdaten al, a2, ... nacheinander die Folgen al, al+a2, ...,∑an, ... und al, 2al+a2, ..., ∑(n+l-i)ai (i=l,...,n), ..., die als einfaches bzw. zweifaches Integral des Eingangssignals über die Zeit aufgefaßt werden können. Der Schalter 7 wird von der Steuerschaltung 15 während eines von je M Takten geschlossen, die restliche Zeit ist er offen. So wird nur einer von je M Folgenwerten durchgelassen, die Daten also um den Faktor M dezimiert. Auf dem hinter demThe integrators 5 successively generate the sequences al, al + a2, ..., ∑an, ... and al, 2al + a2, ..., ∑ (n +) from a sequence of input data al, a2, ... li) ai (i = l, ..., n), ..., which can be understood as a single or double integral of the input signal over time. The switch 7 is closed by the control circuit 15 during one of M cycles, the rest of the time it is open. Only one out of every M sequence values is passed through, i.e. the data is decimated by a factor of M. On the behind the
Schalter 7 liegenden Bereich des Dezimationsfilters 3 ist die Taktperiode somit TM.Switch 7 lying area of the decimation filter 3, the clock period is thus TM.
An den Schalter 7 schließen sich zwei Subrahierstufen 9 an. Diese enthalten wie die Integratorstufen 5 je einen Addierer 6 und ein Register 4, dessen Ausgang an einen ersten Eingang des Addierers 6 angeschlossen ist. Allerdings berücksichtigt der Addierer 6 der Subtrahierstufe 9 den an seinem ersten Eingang anliegenden Datenwert mit umgekehrtem Vorzeichen, und der Eingang des Registers 4 ist mit dem zweiten Eingang des Addierers 6 verbunden.The switch 7 is followed by two subtracting stages 9. Like the integrator stages 5, these each contain an adder 6 and a register 4, the output of which is connected to a first input of the adder 6. However, the adder 6 of the subtracting stage 9 takes into account the data value at its first input with the opposite sign, and the input of the register 4 is connected to the second input of the adder 6.
Das Register 4 der Subtrahierstufe 9 hat wie das der Integratorstufe 5 einen Speicherplatz. Da aber die Datenrate hinter dem Schalter 7 um den Faktor M verringert ist, genügt dieser eine Speicherplatz, um eine Verzögerung um M Taktperioden zu bewirken. Somit hat die einzelne Subtrahierstufe 9 die Über- tragungsfunktionThe register 4 of the subtraction stage 9, like that of the integrator stage 5, has a memory location. However, since the data rate behind the switch 7 is reduced by the factor M, this space is sufficient to cause a delay by M clock periods. The individual subtraction stage 9 thus has the transfer function
Hk(z) = 1- -MH k (z) = 1- -M
Wie man leicht erkennt, führt eine Veränderung des Dezimati- onsfaktors- M automatisch zu einer Veränderung der Gesamtüber- tragungsfunktion H ( z ) = (Hk ( z ) H ( z ) ) 2 = ( l - z -M/l - z " 1 ) 2 .As you can easily see, a change in the decimation factor-M automatically leads to a change in the overall transfer function H (z) = (H k (z) H (z)) 2 = (l - z -M / l - z "1 ) 2 .
Anders als bei den herkömmlichen Dezimationsfiltern für Bildin-Bild-Prozessoren paßt sich die Übertragungsfunktion des Filters 3 automatisch veränderten Dezimationsfaktoren an und gestattet so eine bessere Unterdrückung von Aliasstörungen.In contrast to the conventional decimation filters for picture-in-picture processors, the transfer function of the filter 3 adapts automatically to decimation factors and thus allows a better suppression of alias interference.
An den Ausgang der zweiten Kammstufe 9 ist ein Bildspeicher 11 angeschlossen. Dieser wird ebenfalls von der Zeitsteuer- Schaltung 15 kontrolliert und dient zum Puffern der dezimierten Bilddaten sowie Synchronisieren mit dem Bild des über den Eingang 2 empfangenen zweiten Programms . Die Bilddaten des zweiten Programms und die vom Bildspeicher ausgegebenen dezimierten Daten werden mit Hilfe eines ebenfalls von der Steu- erschaltung 15 kontrollierten Schalters 13 zu einem Bild-inBild-Signal kombiniert. Zu diesem Zweck bestimmt die Steuerschaltung 15 die Phasenbeziehung zwischen den auf den Eingängen 1 und 2 empfangenen Bildern. Wenn das Bild des ersten Programms z . B in die rechte untere Ecke des Bildschirms ein- geblendet werden soll und der Dezimationsfaktor M=2 beträgt, verbindet der Schalter 13 während der ersten Hälfte der Zeilen des zweiten Bildes den Eingang 2 mit dem Ausgang. Während der zweiten Hälfte der Bildschirmzeilen ist der Schalter 13 jeweils in der ersten Hälfte der Zeilenperiode mit dem Ein- gang 2 und in der zweiten mit dem Bildspeicher 11 verbunden. Gleichzeitig veranlaßt die Steuerschaltung 15 den Bildspeicher, während der Verbindungszeit die gepufferten Bildzeilen der Reihe -nach mit der Taktrate T an den Schalter 11 auszugeben. Die Steuerschaltung kann so ausgelegt sein, daß sie dieAn image memory 11 is connected to the output of the second comb stage 9. This is also controlled by the timing control circuit 15 and is used to buffer the decimated image data and to synchronize it with the image of the second program received via input 2. The image data of the second program and the decimated data output by the image memory are combined with the aid of a switch 13 which is also controlled by the control circuit 15 to form an image-in-image signal. For this purpose, the control circuit 15 determines the phase relationship between the images received on inputs 1 and 2. If the picture of the first program z. B is to be faded into the lower right corner of the screen and the decimation factor is M = 2, switch 13 connects input 2 to output during the first half of the lines of the second image. During the second half of the screen lines, the switch 13 is connected to the input 2 in the first half of the line period and to the image memory 11 in the second. At the same time, the control circuit 15 causes the image memory to output the buffered image lines one after the other at the clock rate T to the switch 11 during the connection time. The control circuit can be designed so that it
Schalter 7 und den Bildspeicher 11 entsprechend einem festen, vom Hersteller des Fernsehgeräts vorgegebenen Dezimationsverhältnis M betreibt. In diesem Fall läßt sich ein einheitli- eher erfindungsgemäßer Bild-in-Bild-Prozessor vorteilhaft für Fernsehgeräte mit beliebigen Bildschirmgrößen und dementsprechend unterschiedlichen bevorzugten Größen des eingeblendeten Bildes einsetzen, ohne daß über die Auswahl des Dezimations- verhältnisses hinaus irgendwelche Anpassungen am Dezimations- filter erforderlich wären. Es ist aber auch ohne weiteres möglich, die Steuerschaltung so auszulegen, daß sie ein durch den Benutzer z . B in einem Bereich von 2 bis 5 frei wählbares Dezimationsverhältnis empfängt und Schalter und Bildspeicher entsprechend steuert .Operates switch 7 and the image memory 11 in accordance with a fixed decimation ratio M specified by the manufacturer of the television set. In this case, a more uniform picture-in-picture processor according to the invention can advantageously be used for televisions with any screen sizes and, accordingly, different preferred sizes of the displayed picture, without any adjustments to the decimation filter being necessary beyond the selection of the decimation ratio would be. But it is also easily possible to design the control circuit so that it is a z. B receives a freely selectable decimation ratio in a range from 2 to 5 and controls switches and image memories accordingly.
Die Erfindung ist in keiner Weise auf die im obigen Beispiel verwendete Zahl von je zwei Integrator- und Kammstufen 5, 9 beschränkt. Je nach Anforderungen an Aliasunterdrückung und andere dem Filterkonstrukteur geläufige Parameter kann eine abweichende Zahl von Stufen gewählt werden.The invention is in no way limited to the number of two integrator and comb stages 5, 9 used in the example above. Depending on the requirements for alias suppression and other parameters familiar to the filter designer, a different number of levels can be selected.
In Fig. 2 ist das Dezimationsfilter 3 von Fig. 1 eingangssei- tig und ausgangsseitig erweitert. Am Eingang ist ein Tiefpaß 20 bzw. allgemein gesagt ein Prefilter angeordnet, welches ausgangsseitig an den Eingang des ersten Integrators 5 des CIC-Filters geschaltet ist. Am Ausgang der letzten Subtrahierstufe 9 des CIC-Filters ist eine Frequenzgangkorrektureinrichtung 30 angekoppelt. Das CIC-Filter ist notwendig, um den für die Anpassung an die verschiedenen Bildgrößen des einzublendenden Bildes zu sorgen. Das Dezimationsfilter bezieht sich erfindungsgemäß vorrangig auf die horizontale Dezimation; die vertikale Dezimation kann durch gewichtete /Akkumulation der Zeilen erfolgen. Die gesamte Realisierung des Dezimationsfilters kann blockschaltmäßig so gestaltet sein wie in Fig. 2. Der Tiefpaß 20 dient zum Ausfiltern von Störungen und die ausgangsseitige Frequenz- gangkorrektureinrichtung 30 zur Frequenzgangkorrektur. 2, the decimation filter 3 of FIG. 1 is expanded on the input side and on the output side. A low-pass filter 20 or, generally speaking, a pre-filter is arranged at the input and is connected on the output side to the input of the first integrator 5 of the CIC filter. A frequency response correction device 30 is coupled to the output of the last subtraction stage 9 of the CIC filter. The CIC filter is necessary to ensure that it is adapted to the different image sizes of the image to be displayed. According to the invention, the decimation filter relates primarily to horizontal decimation; vertical decimation can be done by weighting / accumulating the lines. The entire implementation of the decimation filter can be designed in terms of block circuitry as in FIG. 2. The low-pass filter 20 is used to filter out interference and the output-side frequency response correction device 30 is used for frequency response correction.
BezugszeichenlisteReference list
1 , 2 Eingänge 3 Dezimationsfilter 4 Register1, 2 inputs 3 decimation filters 4 registers
5 Integratorstufen5 integrator levels
6 Addierer 7, 13 Schalter6 adders 7, 13 switches
9 Subtrahierstufen 11 Bildspeicher9 subtraction levels 11 image memories
15 Steuerschaltung15 control circuit
20 Tiefpaß20 low pass
30 Frequenzggangkorrektureinrichtung 30 frequency response correction device

Claims

Patentansprüche claims
1. Bild-in-Bild-Prozessor mit zwei Eingängen (1, 2) für je ein Fernseh- oder Videobildsignal, einem Dezimationsfilter (3) zum Dezimieren der Daten eines ersten der zwei Bildsignale und einem Schalter (13) , der das zweite Bildsignal und das Ausgangssignal des Dezimationsfilters (3) empfängt und zu einem kombinierten Bildsignal zusammenfügt, in dem eine Teilfläche des zweiten Bilds durch ein verkleinertes erstes Bild ersetzt ist, d a d u r c h g e k e n n z e i c h n e t, daß das Dezimationsfilter (3) ein CIC-Filter aufweist.1. picture-in-picture processor with two inputs (1, 2) for a television or video image signal, a decimation filter (3) for decimating the data of a first of the two image signals and a switch (13) which the second image signal and the output signal of the decimation filter (3) receives and combines them into a combined image signal in which a partial area of the second image is replaced by a reduced first image, characterized in that the decimation filter (3) has a CIC filter.
2. Bild-in-Bild-Prozessor nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß das CIC- Filter (3) einen Dezimationsfaktor von größer gleich 2, insbesondere von 6 oder 8 hat .2. picture-in-picture processor according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the CIC filter (3) has a decimation factor of greater than or equal to 2, in particular of 6 or 8.
3. Bild-in-Bild-Prozessor nach Anspruch 2, d a d u r c h g e k e n n z e i c h n e t, daß der Dezimationsf aktor umschaltbar ist.3. picture-in-picture processor according to claim 2, d a d u r c h g e k e n n z e i c h n e t that the decimation factor is switchable.
4. Bild-in-Bild-Prozessor nach Anspruch 1, 2 oder 3, d a d u r c h g e k e n n z e i c h n e t, daß eine Ein- richtung zum Auswählen des Dezimationsfaktors vorgesehen ist.4. picture-in-picture processor according to claim 1, 2 or 3, d a d u r c h g e k e n z e i c h n e t that a device is provided for selecting the decimation factor.
5. Bild-in-Bild-Prozessor nach einem der Ansprüche 1 bis 4, d a d u r e h g e k e n n z e i c h n e t, daß vor das CIC- Filter ein Tiefpaß (20) und hinter das CIC-Filter eine Fre- quenzgangkorrektureinrichtung (30) geschaltet ist. 5. Picture-in-picture processor according to one of claims 1 to 4, that a low pass (20) is connected in front of the CIC filter and a frequency response correction device (30) is connected behind the CIC filter.
PCT/DE1998/002833 1997-09-30 1998-09-22 Image-in-image processor WO1999017546A1 (en)

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DE19743206A DE19743206A1 (en) 1997-09-30 1997-09-30 Picture-in-picture processor
DE19743206.9 1997-09-30

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