WO1998020533A3 - Method for using photoabsorptive coatings to enhance both blind and through micro-via entrance quality - Google Patents

Method for using photoabsorptive coatings to enhance both blind and through micro-via entrance quality Download PDF

Info

Publication number
WO1998020533A3
WO1998020533A3 PCT/US1997/019069 US9719069W WO9820533A3 WO 1998020533 A3 WO1998020533 A3 WO 1998020533A3 US 9719069 W US9719069 W US 9719069W WO 9820533 A3 WO9820533 A3 WO 9820533A3
Authority
WO
WIPO (PCT)
Prior art keywords
photoabsorptive
blind
coatings
enhance
micro
Prior art date
Application number
PCT/US1997/019069
Other languages
French (fr)
Other versions
WO1998020533A2 (en
Inventor
David B Noddin
Original Assignee
Gore & Ass
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gore & Ass filed Critical Gore & Ass
Priority to JP52145098A priority Critical patent/JP2001525120A/en
Priority to AU50849/98A priority patent/AU5084998A/en
Publication of WO1998020533A2 publication Critical patent/WO1998020533A2/en
Publication of WO1998020533A3 publication Critical patent/WO1998020533A3/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0112—Absorbing light, e.g. dielectric layer with carbon filler for laser processing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1383—Temporary protective insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Abstract

A method of forming a via in a laminated substrate by applying a polymeric photoabsorptive layer on an exposed surface of a laminated substrate. Ablated material is formed by laser drilling a via in the substrate through the photoabsorptive layer. The ablated material is redeposited on the photoabsorptive layer surrounding the via. The entrance of the via is enhanced by removing the photoabsorptive layer and the ablated redeposited material on the photoabsorptive layer.
PCT/US1997/019069 1996-11-08 1997-10-22 Method for using photoabsorptive coatings to enhance both blind and through micro-via entrance quality WO1998020533A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP52145098A JP2001525120A (en) 1996-11-08 1997-10-22 Using light-absorbing coatings to improve the quality of both blind and through micro-via entrances
AU50849/98A AU5084998A (en) 1996-11-08 1997-10-22 Method for using photoabsorptive coatings to enhance both blind and through micro-via entrance quality

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74564596A 1996-11-08 1996-11-08
US08/745,645 1996-11-08

Publications (2)

Publication Number Publication Date
WO1998020533A2 WO1998020533A2 (en) 1998-05-14
WO1998020533A3 true WO1998020533A3 (en) 1998-11-12

Family

ID=24997611

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/019069 WO1998020533A2 (en) 1996-11-08 1997-10-22 Method for using photoabsorptive coatings to enhance both blind and through micro-via entrance quality

Country Status (4)

Country Link
US (1) US6018196A (en)
JP (1) JP2001525120A (en)
AU (1) AU5084998A (en)
WO (1) WO1998020533A2 (en)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0943392B1 (en) * 1998-03-18 2004-06-23 Mitsubishi Gas Chemical Company, Inc. Method of making through hole with laser, copper-clad laminate suitable for making hole, and auxiliary material for making hole
SG75841A1 (en) * 1998-05-02 2000-10-24 Eriston Invest Pte Ltd Flip chip assembly with via interconnection
US6406939B1 (en) 1998-05-02 2002-06-18 Charles W. C. Lin Flip chip assembly with via interconnection
US6280641B1 (en) 1998-06-02 2001-08-28 Mitsubishi Gas Chemical Company, Inc. Printed wiring board having highly reliably via hole and process for forming via hole
KR100855529B1 (en) * 1998-09-03 2008-09-01 이비덴 가부시키가이샤 Multilayer printed wiring board and method for manufacturing the same
TW522536B (en) 1998-12-17 2003-03-01 Wen-Chiang Lin Bumpless flip chip assembly with strips-in-via and plating
TW396462B (en) 1998-12-17 2000-07-01 Eriston Technologies Pte Ltd Bumpless flip chip assembly with solder via
SG82590A1 (en) 1998-12-17 2001-08-21 Eriston Technologies Pte Ltd Bumpless flip chip assembly with strips and via-fill
US6175160B1 (en) * 1999-01-08 2001-01-16 Intel Corporation Flip-chip having an on-chip cache memory
US6310120B1 (en) * 1999-02-12 2001-10-30 Shin-Etsu Chemical Co., Ltd. Flip-chip type semiconductor device sealing material
JP2001007526A (en) * 1999-06-18 2001-01-12 Ibiden Co Ltd Multilayer buildup wiring board and its manufacture
US6736988B1 (en) * 1999-11-04 2004-05-18 Mitsubishi Gas Chemical Company, Inc. Copper-clad board suitable for making hole with carbon dioxide laser, method of making hole in said copper-clad board and printed wiring board comprising said copper-clad board
KR100381052B1 (en) * 2000-02-23 2003-04-18 엘지.필립스 엘시디 주식회사 Tape Carrier Package with Window and Liquid Crystal Display Device containing the TCP
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
US6350633B1 (en) 2000-08-22 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US6660626B1 (en) 2000-08-22 2003-12-09 Charles W. C. Lin Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
US6551861B1 (en) 2000-08-22 2003-04-22 Charles W. C. Lin Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive
US6403460B1 (en) 2000-08-22 2002-06-11 Charles W. C. Lin Method of making a semiconductor chip assembly
US6402970B1 (en) 2000-08-22 2002-06-11 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
US6562709B1 (en) 2000-08-22 2003-05-13 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US6562657B1 (en) 2000-08-22 2003-05-13 Charles W. C. Lin Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
US6436734B1 (en) 2000-08-22 2002-08-20 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
US6462423B1 (en) 2000-08-31 2002-10-08 Micron Technology, Inc. Flip-chip with matched lines and ground plane
US6627999B2 (en) 2000-08-31 2003-09-30 Micron Technology, Inc. Flip-chip with matched signal lines, ground plane and ground bumps adjacent signal bumps
US6511865B1 (en) 2000-09-20 2003-01-28 Charles W. C. Lin Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly
US6350632B1 (en) 2000-09-20 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with ball bond connection joint
US6350386B1 (en) 2000-09-20 2002-02-26 Charles W. C. Lin Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly
US6544813B1 (en) 2000-10-02 2003-04-08 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6448108B1 (en) 2000-10-02 2002-09-10 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6740576B1 (en) 2000-10-13 2004-05-25 Bridge Semiconductor Corporation Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly
US7414319B2 (en) * 2000-10-13 2008-08-19 Bridge Semiconductor Corporation Semiconductor chip assembly with metal containment wall and solder terminal
US6440835B1 (en) 2000-10-13 2002-08-27 Charles W. C. Lin Method of connecting a conductive trace to a semiconductor chip
US6576493B1 (en) 2000-10-13 2003-06-10 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps
US6537851B1 (en) 2000-10-13 2003-03-25 Bridge Semiconductor Corporation Method of connecting a bumped compliant conductive trace to a semiconductor chip
US6576539B1 (en) 2000-10-13 2003-06-10 Charles W.C. Lin Semiconductor chip assembly with interlocked conductive trace
US6699780B1 (en) 2000-10-13 2004-03-02 Bridge Semiconductor Corporation Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching
US6548393B1 (en) 2000-10-13 2003-04-15 Charles W. C. Lin Semiconductor chip assembly with hardened connection joint
US6667229B1 (en) 2000-10-13 2003-12-23 Bridge Semiconductor Corporation Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip
US6673710B1 (en) 2000-10-13 2004-01-06 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip
US6492252B1 (en) 2000-10-13 2002-12-10 Bridge Semiconductor Corporation Method of connecting a bumped conductive trace to a semiconductor chip
US6444489B1 (en) 2000-12-15 2002-09-03 Charles W. C. Lin Semiconductor chip assembly with bumped molded substrate
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
US6847527B2 (en) * 2001-08-24 2005-01-25 3M Innovative Properties Company Interconnect module with reduced power distribution impedance
US7015066B2 (en) * 2001-09-05 2006-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly
US7357486B2 (en) 2001-12-20 2008-04-15 Hewlett-Packard Development Company, L.P. Method of laser machining a fluid slot
JP3908157B2 (en) * 2002-01-24 2007-04-25 Ｎｅｃエレクトロニクス株式会社 Method of manufacturing flip chip type semiconductor device
US6744132B2 (en) * 2002-01-29 2004-06-01 International Business Machines Corporation Module with adhesively attached heat sink
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6703704B1 (en) 2002-09-25 2004-03-09 International Business Machines Corporation Stress reducing stiffener ring
US20040104463A1 (en) * 2002-09-27 2004-06-03 Gorrell Robin E. Crack resistant interconnect module
US7993983B1 (en) 2003-11-17 2011-08-09 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with chip and encapsulant grinding
US7425759B1 (en) 2003-11-20 2008-09-16 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal and filler
US7538415B1 (en) 2003-11-20 2009-05-26 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal, filler and insulative base
US7270845B2 (en) * 2004-03-31 2007-09-18 Endicott Interconnect Technologies, Inc. Dielectric composition for forming dielectric layer for use in circuitized substrates
US7145221B2 (en) * 2004-03-31 2006-12-05 Endicott Interconnect Technologies, Inc. Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same
US7078816B2 (en) * 2004-03-31 2006-07-18 Endicott Interconnect Technologies, Inc. Circuitized substrate
US7598167B2 (en) * 2004-08-24 2009-10-06 Micron Technology, Inc. Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
US7429529B2 (en) * 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US7517798B2 (en) * 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7949867B2 (en) * 2006-07-19 2011-05-24 Rel-Id Technologies, Inc. Secure communications
US7811863B1 (en) 2006-10-26 2010-10-12 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment
US8440916B2 (en) * 2007-06-28 2013-05-14 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
US7952207B2 (en) * 2007-12-05 2011-05-31 International Business Machines Corporation Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening
KR100956688B1 (en) * 2008-05-13 2010-05-10 삼성전기주식회사 Printed Circuit Board and Manufacturing Method Thereof
US7971347B2 (en) * 2008-06-27 2011-07-05 Intel Corporation Method of interconnecting workpieces
US20120081872A1 (en) * 2010-09-30 2012-04-05 Alcatel-Lucent Canada Inc. Thermal warp compensation ic package
US8481425B2 (en) 2011-05-16 2013-07-09 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8828745B2 (en) 2011-07-06 2014-09-09 United Microelectronics Corp. Method for manufacturing through-silicon via
US8518823B2 (en) 2011-12-23 2013-08-27 United Microelectronics Corp. Through silicon via and method of forming the same
US8609529B2 (en) 2012-02-01 2013-12-17 United Microelectronics Corp. Fabrication method and structure of through silicon via
US8716625B2 (en) * 2012-02-03 2014-05-06 Trumpf Werkzeugmaschinen Gmbh + Co. Kg Workpiece cutting
US8691600B2 (en) 2012-05-02 2014-04-08 United Microelectronics Corp. Method for testing through-silicon-via (TSV) structures
US8691688B2 (en) 2012-06-18 2014-04-08 United Microelectronics Corp. Method of manufacturing semiconductor structure
US9275933B2 (en) 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US8900996B2 (en) 2012-06-21 2014-12-02 United Microelectronics Corp. Through silicon via structure and method of fabricating the same
US8525296B1 (en) 2012-06-26 2013-09-03 United Microelectronics Corp. Capacitor structure and method of forming the same
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same
US10340203B2 (en) 2014-02-07 2019-07-02 United Microelectronics Corp. Semiconductor structure with through silicon via and method for fabricating and testing the same

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602318A (en) * 1981-04-14 1986-07-22 Kollmorgen Technologies Corporation Substrates to interconnect electronic components
US4954313A (en) * 1989-02-03 1990-09-04 Amdahl Corporation Method and apparatus for filling high density vias
WO1991003375A1 (en) * 1989-08-31 1991-03-21 David Sarnoff Research Center, Inc. Manufacture of printed circuit boards
US5245751A (en) * 1990-04-27 1993-09-21 Circuit Components, Incorporated Array connector
EP0661734A2 (en) * 1993-12-28 1995-07-05 Nec Corporation Method of forming via holes in an insulation film and method of cutting the insulation film
GB2286787A (en) * 1994-02-26 1995-08-30 Oxford Lasers Ltd Selective machining by dual wavelength laser
US5454161A (en) * 1993-04-29 1995-10-03 Fujitsu Limited Through hole interconnect substrate fabrication process
WO1996002351A1 (en) * 1994-07-18 1996-02-01 Electro Scientific Industries, Inc. Ultraviolet laser system and method for forming vias in multi-layered targets
US5493096A (en) * 1994-05-10 1996-02-20 Grumman Aerospace Corporation Thin substrate micro-via interconnect
EP0706309A1 (en) * 1994-10-06 1996-04-10 International Computers Limited Printed circuit manufacture
JPH0994686A (en) * 1995-09-29 1997-04-08 Dainippon Printing Co Ltd Method for machining metallic plate

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE392582B (en) * 1970-05-21 1977-04-04 Gore & Ass PROCEDURE FOR THE PREPARATION OF A POROST MATERIAL, BY EXPANDING AND STRETCHING A TETRAFLUORETENE POLYMER PREPARED IN AN PASTE-FORMING EXTENSION PROCEDURE
US4473737A (en) * 1981-09-28 1984-09-25 General Electric Company Reverse laser drilling
US4348253A (en) * 1981-11-12 1982-09-07 Rca Corporation Method for fabricating via holes in a semiconductor wafer
US4482516A (en) * 1982-09-10 1984-11-13 W. L. Gore & Associates, Inc. Process for producing a high strength porous polytetrafluoroethylene product having a coarse microstructure
US4445978A (en) * 1983-03-09 1984-05-01 Rca Corporation Method for fabricating via connectors through semiconductor wafers
US4720308A (en) * 1984-01-03 1988-01-19 General Electric Company Method for producing high-aspect ratio hollow diffused regions in a semiconductor body and diode produced thereby
US4595428A (en) * 1984-01-03 1986-06-17 General Electric Company Method for producing high-aspect ratio hollow diffused regions in a semiconductor body
US4547836A (en) * 1984-02-01 1985-10-15 General Electric Company Insulating glass body with electrical feedthroughs and method of preparation
EP0151490B1 (en) * 1984-02-09 1991-01-16 Toyota Jidosha Kabushiki Kaisha Process for producing ultra-fine ceramic particles
US4647476A (en) * 1984-03-05 1987-03-03 General Electric Company Insulating glass body with electrical feedthroughs and method of preparation
US4943032A (en) * 1986-09-24 1990-07-24 Stanford University Integrated, microminiature electric to fluidic valve and pressure/flow regulator
US4901136A (en) * 1987-07-14 1990-02-13 General Electric Company Multi-chip interconnection package
US4915981A (en) * 1988-08-12 1990-04-10 Rogers Corporation Method of laser drilling fluoropolymer materials
US4985296A (en) * 1989-03-16 1991-01-15 W. L. Gore & Associates, Inc. Polytetrafluoroethylene film
US4913656A (en) * 1989-04-07 1990-04-03 Rogers Corporation Electrical connector
US5459634A (en) * 1989-05-15 1995-10-17 Rogers Corporation Area array interconnect device and method of manufacture thereof
US5019997A (en) * 1989-06-05 1991-05-28 General Electric Company Adaptive lithography accommodation of tolerances in chip positioning in high density interconnection structures
US5009607A (en) * 1989-07-24 1991-04-23 Rogers Corporation Flexible circuit connector
US5108785A (en) * 1989-09-15 1992-04-28 Microlithics Corporation Via formation method for multilayer interconnect board
US4959119A (en) * 1989-11-29 1990-09-25 E. I. Du Pont De Nemours And Company Method for forming through holes in a polyimide substrate
DE4115043A1 (en) * 1991-05-08 1997-07-17 Gen Electric High density interconnect structure for packaging microwave and other overlay sensitive chips
US5071359A (en) * 1990-04-27 1991-12-10 Rogers Corporation Array connector
US5293626A (en) * 1990-06-08 1994-03-08 Cray Research, Inc. Clock distribution apparatus and processes particularly useful in multiprocessor systems
US5251097A (en) * 1990-06-11 1993-10-05 Supercomputer Systems Limited Partnership Packaging architecture for a highly parallel multiprocessor system
US5171964A (en) * 1990-07-23 1992-12-15 International Business Machines Corporation High accuracy, high flexibility, energy beam machining system
US5442475A (en) * 1991-07-15 1995-08-15 Cray Research, Inc. Optical clock distribution method and apparatus
US5293025A (en) * 1991-08-01 1994-03-08 E. I. Du Pont De Nemours And Company Method for forming vias in multilayer circuits
US5391516A (en) * 1991-10-10 1995-02-21 Martin Marietta Corp. Method for enhancement of semiconductor device contact pads
US5224265A (en) * 1991-10-29 1993-07-06 International Business Machines Corporation Fabrication of discrete thin film wiring structures
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5428803A (en) * 1992-07-10 1995-06-27 Cray Research, Inc. Method and apparatus for a unified parallel processing architecture
US5355397A (en) * 1992-09-24 1994-10-11 Cray Research, Inc. Clock start up stabilization for computer systems
WO1994008443A1 (en) * 1992-09-29 1994-04-14 Berg N Edward Method and apparatus for fabricating printed circuit boards
US5466892A (en) * 1993-02-03 1995-11-14 Zycon Corporation Circuit boards including capacitive coupling for signal transmission and methods of use and manufacture
US5378313A (en) * 1993-12-22 1995-01-03 Pace; Benedict G. Hybrid circuits and a method of manufacture
US5509553A (en) * 1994-04-22 1996-04-23 Litel Instruments Direct etch processes for the manufacture of high density multichip modules
US5541367A (en) * 1994-10-31 1996-07-30 Dell Usa, L.P. Printed circuit board having a land with an inwardly facing surface and method for manufacturing same
US5541731A (en) * 1995-04-28 1996-07-30 International Business Machines Corporation Interferometric measurement and alignment technique for laser scanners
US5774340A (en) * 1996-08-28 1998-06-30 International Business Machines Corporation Planar redistribution structure and printed wiring device
WO1998020557A1 (en) * 1996-11-08 1998-05-14 W.L. Gore & Associates, Inc. Method for reducing via inductance in an electronic assembly and device
US5888631A (en) * 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Method for minimizing warp in the production of electronic assemblies

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602318A (en) * 1981-04-14 1986-07-22 Kollmorgen Technologies Corporation Substrates to interconnect electronic components
US4954313A (en) * 1989-02-03 1990-09-04 Amdahl Corporation Method and apparatus for filling high density vias
WO1991003375A1 (en) * 1989-08-31 1991-03-21 David Sarnoff Research Center, Inc. Manufacture of printed circuit boards
US5245751A (en) * 1990-04-27 1993-09-21 Circuit Components, Incorporated Array connector
US5454161A (en) * 1993-04-29 1995-10-03 Fujitsu Limited Through hole interconnect substrate fabrication process
EP0661734A2 (en) * 1993-12-28 1995-07-05 Nec Corporation Method of forming via holes in an insulation film and method of cutting the insulation film
GB2286787A (en) * 1994-02-26 1995-08-30 Oxford Lasers Ltd Selective machining by dual wavelength laser
US5493096A (en) * 1994-05-10 1996-02-20 Grumman Aerospace Corporation Thin substrate micro-via interconnect
WO1996002351A1 (en) * 1994-07-18 1996-02-01 Electro Scientific Industries, Inc. Ultraviolet laser system and method for forming vias in multi-layered targets
EP0706309A1 (en) * 1994-10-06 1996-04-10 International Computers Limited Printed circuit manufacture
JPH0994686A (en) * 1995-09-29 1997-04-08 Dainippon Printing Co Ltd Method for machining metallic plate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 097, no. 008 29 August 1997 (1997-08-29) *

Also Published As

Publication number Publication date
JP2001525120A (en) 2001-12-04
AU5084998A (en) 1998-05-29
WO1998020533A2 (en) 1998-05-14
US6018196A (en) 2000-01-25

Similar Documents

Publication Publication Date Title
WO1998020533A3 (en) Method for using photoabsorptive coatings to enhance both blind and through micro-via entrance quality
WO1998020531A3 (en) Method for forming a through-via in a laminated substrate
CA2377641A1 (en) Method of applying and removing a protective film to the surface of a handrail of an escalator or moving walkway
AU3553795A (en) Apparatus and method for clampling a substrate
FI972639A (en) Method and apparatus for coating or coating a substrate layer
ATE137460T1 (en) METHOD AND DEVICE FOR WRAPPING ROLLS, IN PARTICULAR PAPER ROLLS, IN A WRAPPING FILM
EP0692815A3 (en) Method and apparatus for etching film layers on large substrates
AU5084198A (en) Method to correct astigmatism of fourth yag to enable formation of sub 25 micron micro-vias using masking techniques
AU1576595A (en) A method of making a composite laminate and a PWB substrate so made
EP0757291A3 (en) Processing method and processing apparatus using fast atom beam
AU4067399A (en) Method for selective plating of a metal substrate using laser developed masking layer and apparatus for carrying out the method
AU8688698A (en) Method and apparatus for making formed laminate
JPS62210072A (en) Method and apparatus for applying adhesive surface coating to web
DE50000836D1 (en) METHOD FOR PUTTING CONTACT HOLES INTO AN ELECTRICALLY INSULATING BASE MATERIAL PROVIDED ON TWO-SIDED METAL LAYERS
EP0725559A3 (en) Method and apparatus for applying a film onto a surface
EP0751009A3 (en) Product containing a reproduced image and method of forming a reproduced image layer
AU4896499A (en) Method and device for applying a plastic layer to the inner surfaces of hollow bodies
EP0731188A3 (en) Apparatus and method for depositing films on substrate via off-axis laser ablation
CA2282009A1 (en) Apparatus and method of making polymer-based laminates
NO943225L (en) Method and apparatus for removing a surface layer
JPS6447053A (en) Formation of multilayer interconnection
AU5179098A (en) Method and apparatus for directional deposition of thin films using laser ablation
GB2298959B (en) Method of fabricating metallized substrates using an organic etch block layer
EP0707339A3 (en) Method and apparatus for planarizing a layer of material on a semiconductor substrate surface
EE9800205A (en) Method for the production of boards with a homogeneous decorative surface layer containing electron beam treated varnish

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

ENP Entry into the national phase

Ref country code: JP

Ref document number: 1998 521450

Kind code of ref document: A

Format of ref document f/p: F

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD AT

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
122 Ep: pct application non-entry in european phase