WO1998007238A1 - Parallel input ecc encoder and associated method of remainder computation - Google Patents

Abstract

An ECC encoder (25) with several sub-encoders (55, 100, 125) configured in such a way that the encoder (25) can accept an arbitrary number of input symbols at a single clock cycle. The disclosed encoder configuration can speed up the encoding and remainder computation by an arbitrary factor, albeit with increased encoder complexity. Because the growth of the complexity is at a much slower rate than the speed improvement in the encoding process, however, the design is capable of significantly improving the overall speed of the ECC system because the encoding and remainder computation processes are among the most time consuming operations in an ECC system.

Description

PARALLEL INPUT ECC ENCODER

AND ASSOCIATED

METHOD OF REMAINDER COMPUTATION

Field of the Invention

This invention relates generally to an encoder for encoding data in accordance with an error-correcting code. More particularly, it relates to an encoder and associated method for speeding up the encoding and remainder computation processes when employing cyclic codes for error detection and correction.

Background

In an error-correcting system using cyclic codes, the data encoding process is usually one of the most time-consuming processes (the other is the determination of the error locations). In accordance with the prior art, an error-correcting code ("ECC") encoder for a cyclic code is typically designed so that the data symbols are fed to the encoder one symbol per clock cycle to simplify the encoder design. For a cyclic code with monic generator polynomial g(x) = x^r + g[r-l]*x^(I"1) + g[r-2]*x^(r"2) + ... + g[2]*x² + g[l]*x + g[0], an encoder 10 can be realized as shown in Fig. 1 where each <g[i]> is a Galois field ("GF") multiplier 12 whose output is equal to g[i] times its input; GF adders 13 (represented by (+) symbols) have outputs equal to the Galois field sum of their respective inputs; and temporary storage devices 14 (or a single stage shift register) have respective contents s[i] that are updated at each clock cycle while the old content is output. Encoder 10 is a serial one-data-symbol-per-clock-cycle encoder which is essentially the same as that shown in Fig. 8.2 of Peterson and Weldon, Error-Correcting Codes (2d ed. 1972) p. 227, with g[r] = 1. For the purposes of the present discussion, it is assumed that the r registers are initially set to zero, however this condition may be removed. Switch 17 should be at position 1 when the data symbols are serially fed to the encoder; after the last data symbol is fed, switch 17 is set to position 2 and the contents of the r registers are the r redundant symbols for the set of the data.

In fact, the data symbols can be fed serially to any of the GF adders because the storage device (or the register) is a delay element. A delay will be introduced if the data symbols are fed to GF adders 13, except GF adder 13', as shown in Fig. 1. Turning to Fig. 2, for example, a delay of one clock cycle will be introduced in encoder 20 to get the redundant symbols. Encoder 20 is an example of a prior art serial encoder with unit cycle delay. Switch 17 is in position 1 for all of the data symbols but one additional clock cycle after the last data symbol is fed in it is switched to position 2 for the redundant symbols in the registers to be outputted.

Although such prior art serial input encoders are relatively easy to implement, the serial input constraint substantially limits the data throughput at the encoder input.

Moreover, because the encoder of a cyclic code is also in fact a remainder computation circuit, both the input encoding and remainder computation processes suffer from the same serial input limitation. For example, let the data symbols be c[N-l], c[N-2], ..., c[r] and let the encoder generate the redundant symbols c[r-l], c[r-2], ..., c[l ], c[0] for the given data symbols; then

c(x) = c[N-l]*x^(N-^,) + c[N-2]*x^(N"2) + ... + c[r]*x^r + c[r-l]*x^(r-" + ... + c[3]*x³ + c[2]*x² + c[l]*x + c[0]

is a multiple of the generator polynomial g(x). Let the retrieved codeword be:

c'(x) - c^,[N-l]*x^(N-^,) + c^,[N-2]*x^(N"2) + ... + c'[r]*x^r

+ c'[r-l]*x^(r-¹⁾ + ... + c'[3]*x³ + c'[2]*x² + c'[l]*x + c*[0]

where c'[i] may or may not be equal to c[i] due to errors. In other words, c'[i] = c[i] implies that the retrieved symbol c'[i] is correct, whereas if c'[i] differs from c[i] then the retrieved symbol includes an error. To compute the remainder for c'(x), c'fN-1], c'[N-2], ..., c'[r] are fed to the encoder to generate c'*[r-l], c"[r-2], ..., c"[2], c"[l], c"[0]. The remainder for c'(x) is then given by:

(c"[r-l] + c'[r-l])*x^(τ-^l) + (c"[r-2] + c'[r-2])*x^(r"2) + ... +

(c"[2] + c'[2])*x² + (c"[l] + c'[l])*x + (c"[0] + c'[0]).

Thus the same circuit can be used for both encoding and remainder computation.

The invention to be described enables ECC encoder designers to increase the data encoding speed by an arbitrary factor while limiting increases in circuit complexity to a rate much smaller rate than the rate of increased encoding speed. The invention also provides commensurate speed increases in the remainder computation process.

Summary of the Invention An ECC encoder in accordance with the invention includes a plurality of inputs each coupled to a distinct sub-encoder to facilitate parallel data input to speed up data encoding and remainder computation.

A general object of the present invention is to provide an apparatus and method for speeding up the encoding and remainder computation processes when employing cyclic codes for error-correction and/or error-detection.

These and other objects, advantages, aspects, and features of the present invention will be more fully appreciated and understood upon consideration of the following detailed descriptions of a preferred embodiment presented in conjunction with the accompanying drawings.

Brief Description of the Drawings

In the Drawings:

Fig. 1 is a high-level linear circuit diagram of a prior art serial one-data-symbol-per- clock-cycle ECC encoder.

Fig. 2 is a high-level linear circuit diagram of a prior art serial ECC encoder with unit cycle delay.

Fig. 3 is a high-level diagram of an ECC encoder capable of receiving rwo-data-symbols- per-clock-cycle input.

Fig. 4 is a timing diagram illustrating the operation of a pair of T^k encoders requiring k units of time to process k or fewer parallel inut symbols.

Fig. 5 is a timing diagram illustrating the operation of dual parallel sub-encoders.

Fig. 6 is a timing diagram illustrating the operation of triple parallel sub-encoders.

Fig. 7 illustrates a sub-encoder circuit encoder, connected according to T⁸.

Figs. 8A-8B illustrate a notation for compactly representing a set of circuit elements in a circuit diagram. Fig. 9 illustrates a sub-encoder circuit encoder₂ connected according to T⁸ and T⁶.

Fig. 10 illustrates a sub-encoder circuit encoder-, connected according to T⁸ and T³.

Fig. 1 1 is a timing diagram illustrating the operation of L+l parallel sub-encoders.

Detailed Description of a Preferred Embodiment

An improved ECC encoder in accordance with a preferred embodiment of the invention may be more clearly understood when described in the context of and in contrast with the prior art serial encoders illustrated in Figs. 1 and 2. The prior art encoders of both Fig. 1 and Fig. 2 can be characterized mathematically by the same companion matrix. That companion matrix is:

This definition of the companion matrix is the same as the one set forth in

Peterson and Weldon (id. at p. 200). (Note that in the literature, authors sometimes also refer to the transpose of T as the companion matrix, e.g., Eq. (7.36) of Peterson and Weldon (id. at p.199).)

If the contents of the shift registers are s[0], s[l], ..., s[r-l] at a particular cycle, then the contents of the shift registers s'[0], s'[l], ..., s'[r-l] at the next cycle (without any input) is given by:

s'[0] = 0 + g[0]*s[r-l], s'[l] = s[0] + g[l]*s[r-l], s^,[2] = s[l] + g[2]*s[r-l],

> (Eq. 2d) s'[r-2] = s[r-3] + g[r-2]*s[r-l], s'[r-l] = s[r-2] + g[r-l]*s[r-l].

The first term of each equation in Eqs. (2a) represents one input of each register from the previous register and the second term of each equation in Eqs. (2a) comes from the feedback term from the output of the rightmost register. Therefore, Eq. (2), or equivalently Eqs. (2a), describes both Fig. 1 and Fig. 2 without taking the input into consideration.

A complete mathematical description of the operation of the circuit of Fig. 1 is given by:

(Eq. 3)

where c[i] is the ith data symbol. The order of data fed to the encoder is c[n-l], c[n-2], .. c[r+l], c[r] for a cyclic code of length n, and c[r-l], c[r-2], ..., c[2], c[l], c[0] are the redundant symbols taken for the registers after the last input symbol was fed in.

Similarly, a complete mathematical description of the operation of the circuit of Fig. 2 is given by:

s~[0] I I s[0] s~[l] I | s[l] s~[2] I I s[2] (Eq. 4)

. . . | = T*| _ yi_l s~[r-3]| I s[r-3] s~[r-2]| | s[r-2] + c[i]| s~[r-l]| | s[r-l] |

Note that s~[j] is used in Eq. 4 instead of s'[j] merely to avoid confusion.

To design a parallel input encoder in accordance with a preferred embodiment of the invention, let us denote a r-component column vector as t]. For example, we let:

s~] = transpose of row vector (s~[0], s~[l], ..., s~[r-l])

s] = transpose of row vector (s[0], s[l], ..., s[r-l]) and

c~] = transpose of row vector (0, 0, ..., 0, c[i], 0) then Eq. (4) can be rewritten as

s~] = T*(s] + c~]) = T*s] + T*c~] (Eq. 4a)

Let us also define:

c] = transpose of row vector (0, 0, ..., 0, 0, c[i]) then Eq. (3) can be rewritten as

s^*] - T*(s] + c]) = T*s] + T*c] (Eq. 3a)

By thus defining Eq. (3a) and Eq. (4a), it becomes possible to consider the introduction of inputs separately. Therefore, in accordance with a preferred embodiment of the invention, a circuit is designed for s'] = T*s] such that T in s'] = T*s] can be given a physical implementation which then allows the input data to be presented in parallel.

The rows and columns of T are numbered from 0 to r-1 as indicated in Eq. (1). The element at i'th row and j'th column, t[i][j], means that s|j]*t[i][j] is one part of the input to s[i]. Column j of T indicates how s[j] is fed to different s'[i]:

sβ]*t[i][j] is part of input to s'[i] for all i.

Row i of T gives the all the input to s'[i]:

s'[i] = s[0]*t[i][0] + s[l]*t[i][l] + ... + s[r-l]*t[i][r-l]. Therefore, given the appropriate companion matrix, it is possible to specify a circuit for the encoder. To obtain a companion matrix which will take two input symbols in parallel, define the two input symbols to be fed as c[i] and c[i-l]. The column s'] can be obtained from s] by:

s'j = T*s] + T* {transpose of (0, 0, ..., 0, c[i])} (Eq. 5)

column s"] can then be computed by:

s"] = T*s'] + T* {transpose of (0, 0, ..., 0, c[i-l])}

= T*T*s] + T*T* {transpose of (0, 0, ..., 0, c[i])}

+ T* {transpose of (0, 0, ..., 0, c[i-l])} (Eq. 6)

However, T* {transpose of (0, 0, ..., 0, c[i-l], 0)}

- {transpose of (0, 0, ..., c[i-l])} (Eq. 7)

Substituting Eq. (7) into Eq. (6), we have

s"] = T*T*s] + T*T* {transpose of (0, 0, ..., 0, 0, c[i])}

+ T*T* {transpose of (0, 0, ..., 0, c[i-l], 0)} = T*T*s] + T*T* {transpose of (0, 0, ..., 0, c[i-l], c[i])} (Eq. 8)

Since T*T = T² is nothing but yet another matrix, a new "companion matrix" is therefore defined which will accept c[i] and c[i-l] in one cycle:

s"] = (T²)*s] + (T²)* {transpose of (0, 0, ..., 0, c[i-l], c[i])}

(Eq. 9)

Translating Eq. (9) into a circuit proceeds as follows: since

I 0 0 0 . . . 0 0 g[0] I | 1 0 0 . . . 0 0 g[l] | T = I 0 1 0 . . . 0 0 g[2] I (Eq. 10)

I 0 0 0 . . . 1 0 g[r-2]| I 0 0 0 . . . 0 1 g[r-l]| then

(Eq. 11)

0 0 0 . . . 1 g[r-l] g[r-21 + g[r-l]

Accordingly, a two-data-symbol-input per clock cycle parallel encoder circuit 25 for encoding a pair of input data symbols at each clock cycle may be configured as illustrated in Fig. 3, where GF multipliers 27 operate with multiplicands h[0] = g[r-l], h[l] = g[r-l] + g[0], ..., h[j] = g[r-l] + g[j-l] forj = 1 , 2, ..., r-1 ; switches 17 and 17' are at positions 1 and 1' for data symbols and at positions 2 and 2' for redundant symbols s[r-l], s[r-2], ..., s[2], s[l], s[0], respectively. Note that the data symbols c[i] and c[i-l] are fed in pairs to encoder 25. If there are an odd number of data symbols, a zero is assumed to be inserted as the first symbol prior to the data symbols; the zero and the data symbols thus form an even number of symbols. In the case that the initial values for shift registers 14 are not zeros, the same set of initial values can be assigned to the registers 14 as if the number of data symbols is even. In the case that the number of data symbols is odd, i.e. there is one zero symbol inserted prior to the actual data, the initial values assigned to encoder 25 will be different. Let the desired initial value for the single-input-data- symbol-per-cycle encoder of Fig. 1 be p] = transpose of {p[0], p[l], ..., p[r-l]} and the actual value assigned to Fig. 3 be u] = transpose of {u[0], u[l], ..., u[r-l]} . Since, the first data symbol is zero, this means that u[0], u[l], ..., u[r-l] differ from p[0], p[l], ..., p[r- 1 ] by a matrix transformation T, i.e.

T*p] = u] (Eq. 12)

or u] = T'-'^p], (Eq. 13)

where T ^l) denotes the inverse of T. Because the matrix T is of special form, it can be easily shown that T^('° is given by:

By computing T^k, for k = 2, 3, 4, ..., r, a k-symbol per clock cycle encoder can be designed from T^k. (There are r places the circuit can accept input symbols.) If more than r parallel input symbols per clock cycle, we need to duplicate the circuit for the case r < k <= 2r and to triplicate the circuit for the case 2r < k <= 3r, etc., as shown:

i) For k-input data symbols per clock cycle with r < k <= 2r

In this case, k parallel input symbols are divided into two sets of input symbols k, symbols and k₂ symbols such that k, + k₂ = k. It is clear that k, > 0 and k₂ > 0. The set of k, symbols is fed to encoder, and the set of k₂ symbols is fed to encoder k₂. All the input symbols to both sub-encoders are fed in order to the GF adders at the output of s[r-l], s[r- 2], etc. Both sub-encoders are connected according to T^k for all the inputs except encoder₂ should switch to connection T for the last set of k₂ input symbols. The redundant symbols are the GF sum of the the corresponding shift registers of both sub- encoders after the last set of k data symbols are fed.

If the total number of data symbols is not a multiple of k, the data are filled with zero prior to data symbols to make the total number of symbols a multiple of k. If the number of data symbols is exactly a multiple of k, the initial values can be set on the shift registers of encoder, and the initial values for encoder₂ are all set to zeros. If there are n zeros filled in for the data with n < k„ and let the desired initial values for the single- input-data-symbol-per-cycle-encoder be p], then the initial values for encoder, is

u] = T⁽-ⁿ⁾*p]. (Eq. 15)

If there are n zeros filled in for the data with n = k„ then the initial condition are set on encoder₂. If there are n zeros filled in for data with n > k„ then the initial condition for encoder, are set to zeros and the initial condition for encoder₂ are set to:

u] = T⁽-^{n +} 7*P]; {Eq. 16) In fact, in this case, encoder, can be considered as the first encoder followed by encoder,.

A timing diagram 30, as shown in Fig. 4, may help clarify some of the concepts discussed above. In timing diagram 30, we assume for ease of conceptual understanding that the time to operate an encoder connected according to T^s to take any parallel s or fewer symbols is s time units. Initially, both encoder, and encoder₂ are connected according to T^k. Therefore, encoder, needs k units of time to process k, symbols and encoder₂ also needs k units of time to process k₂ symbols. We further assume that encoder, starts at k, units of time ahead of encoder₂. as shown in Fig. 4. At the very last k, symbols for encoder, the encoder is still connected according to T^k; however, the very last k₂ symbols for encoder₂ the encoder is connected according to T as shown in Fig. 4. Therefore, both encoders will produce, respectively, the redundant symbols RED, from encoder, and RED₂ from encoder₂ at the exactly the same time as shown in Fig. 4. The final encoded redundant symbols are obtained from symbol by symbol exclusive-oring of RED, and RED₂.

In fact, the time for an encoder T^k to process k, input symbols or k₂ symbols is the same as T^k ₂ ⁾ to process k₂ input symbols are exactly the same. Let us call this common process time t. The value oft can be an arbitrary value; however, t can be made equal to or slightly less than the time for k input symbols to be fed to the encoders. Furthermore, both encoder, and encoder₂ are starting at the same time. Therefore, a realistic timing diagram 40 for dual encoders is illustrated in Fig. 5. It is evident from the timing diagram 40 of Fig. 5 that it is possible to design an encoder which can take up to 2r parallel inputs with two sub-encoders encoder, and encoder₂. If the initial condition is not zero, only one of the sub-encoders have non-zero initial condition set according to Eq. (15) or Eq. (16) and the initial condition for the other initial condition are set to all zero.

ii) For k-input data symbols per clock cycle with 2r < k <= 3r

It should also be clear from the foregoing that, in accordance with the present disclosure, three sub-encoders, encoder,, encoder₂ and encoder,, will be needed to accomplish parallel encoding in the present case. A timing diagram 50 (of the same type developed in Section i), illustrated in Fig. 6, may be used to represent the timing for case ii). Timing diagram 50 illustrates a realistic timing model for triple parallel sub-encoders.

An example will serve to illustrate all of the important concepts. Although this example describes a particular case, those skilled in the art will recognize that the disclosed concepts are generally applicable and extensible to the design of other parallel input encoders. In this example, assume r = 3. The generator polynomial is g(x) = x³ + α²¹⁵x² + α²¹⁵x + 1 over GF(2⁸) whose non-zero elements are generated by binary primitive polynomial x⁸ + x⁴ + x³ + x² + 1. Let us further assume that the input symbols are available at k=8 symbols per clock cycle. Since 8 is greater than 2*r but less than 3*r, therefore, we can design an encoder with three sub-encoders encoder,, encoder₂ and encoder₃. Let assume k = k, + k₂ + k₃ with k, = 2, k₂ = 3, and k₃ = 3. We need T⁸, T⁶ and T³ to get the complete design. We can easily compute the following companion matrices:

| 0 0 α^ϋ I

T = | ° 0 α , 197 I α α .197 I

α _α.97 _α246

α¹⁹⁷ α²⁴⁶ α¹⁶⁰

α^{160 250} α²²³

T⁶ = | α²³⁷ α¹⁹⁵ α⁸⁰ l ^{250 223} α²³¹

and

²²³ α²³' α²³⁸ 1

T⁸ = | α 8⁸0^U „ α. !"75^J α „ 163 α²³' <x^{238 58}

Therefore, using T⁸, we can design a sub-encoder as shown in Fig. 7, which illustrates sub-encoder 55, designated encoder,, connected according to T⁸ (as an example). Switches 17, 17', and 17" are in positions 1, 1', and 1", respectively, for data input (i.e., for c[i] and c[i-l] for i >= r) and are in positions 2, 2', and 2", respectively, for outputting the redundant symbols after all the data symbols are fed in. In this example, GF multipliers 57-65 multiply their respective inputs by the indicated power of α in Fig.

7. In this example, k = 8 and k, = 2 also noted that i = 1, 2, ..., j, ... and c[i] precedes c[i- 1 ] in time.

To get encoder₂, we need both T⁸ and T⁶. The sub encoder is connected according to T⁸ most of the time and switched to the connection according to T⁶ for the last k data input symbols. For compactness of representation, let us introduce the equivalent circuit notation illustrated in Figs. 8A - 8B. The circuit elements (switchable GF multiplier(s)) represented by notation 90 of Fig. 8A is to be interpreted as being equivalent to the expanded [equivalent] switchable GF multiplier circuit 91 shown in Fig. 8B, where switches 95 and 95' are at positions 3 and 3' for c[i] with i >= k+r and at position 4 and 4' for i < k+r; GF multiplier 96 is an α^p multiplier for all of the input data symbols except the last k symbols and GF multiplier 97 is an α^q multiplier for the last k input data symbols. With the notation thus described, sub-encoder 100, designated encoder₂, is given in Fig. 9, which illustrates a circuit diagram of sub-encoder encoder₂ connected according to T⁸ and T⁶, wherein switches K are in positions 1 for data input c[i-2], c[c-3] and c[i-4] for i >= r and are in positions 2 for outputting the redundant symbols after all data symbols are fed in. Switchable GF multipliers 105 - 113 operate as previously described in connection with Figs. 8A and 8B using the indicated multiplicand(s). In the illustrated example, k = 8 and k, = 2 and k₂ = 3.

Similarly, we can design sub-encoder encoder₃ from T⁸ and T³, as shown in Fig. 10. Switches 17, 17', and 17" are in positions 1, 1', and 1" for data input c[i-5], c[c-6] and c[i-7] for i >= r and are in positions 2, 2', and 2" for outputting the redundant symbols after all data symbols are fed in. Switchable GF multipliers 130 - 138 operate as previously described using the indicated multiplicand(s). In this example, k =

8, k, = 2, k₂ = 3 and k₄ = 3.

The final three redundant symbols after the last data symbol are in order:

s[2] = s3[2] + s2[2] + sl [2], s[l] = s3[l] + s2[l] + sl [l], and s[0] = s3[0] + s2[0] + sl [0].

As for the initial conditions for the sub-encoders, they depends on the number of data symbols, which, in turn, determines the number of zero fills for the each of the encoders. Let us assume that the total number of data symbols is 100. Since 100 is not divisible by 8, we need to fill in 4 symbols. This means that encoder, will have both inputs being zero and encoder₂ will have two zeros at the very beginning. Therefore, the initial conditions for encoder, and encoder₃ are all zeros and the initial condition for encoder₂ is

u] = T^{( 2)}*p].

If p] = transpose of ( °, α¹, α²)

we can easily computed the initial condition for encoder₂ be the transpose of (α¹²⁷, ¹⁰², α²⁴)

or s3[0] = α¹²⁷, s3[l] = α¹⁰² and s3[2] = α²⁴.

iii) For k-input data symbols per clock cycle with Lr < k <= (L+l)r

In this general case, we need L+l encoders. A representative timing diagram is shown in Fig. 1 1, which illustrates a realistic timing diagram 150 for the case of L parallel sub-encoders. The L sub-encoders can be designed from the timing diagram, in the manner previously set forth. In the illustrated example:

k_i. = k - (k, + k₂ + ... + k_i); . . . .

K^ -i₎ ^{1 =} k - [k, + k₂ + k₃ + ... + k^_L.,₎]; k_L. = k - (k, + k₂ + ... + k_L); and k_(L+ιy ⁼ k - [k, + k₂ + k₃ + ... + ^₊^J.

For remainder computations, if c'[N-l], c'[N-2], ..., c'[r], c'[r-l], c'[r-2], ..., c'[l],c'[0] is the retrieved codeword of the original codeword c[N-l], c[N-2], ..., c[r], c[r- 1], c[r-2], ..., c[l], c[0], then we can feed the retrieved data symbols c'[N-l], c'[N-2], ..., c'[r] to an encoder to compute the redundant symbols c"[r-l], c"[r-2], ..., c"[l], c"[0]. The remainder of the retrieved codeword is given by:

c'[r-l]+c"[r-l], c'[r-2]+c"[r-2], ..., c'[l]+c"[l], c'[0]+c"[0] Therefore, the speed improvement in remainder computation is the same as the speed improvement in the encoder.

In summary, the instant invention provides an apparatus and method for speeding up the encoding process and the remainder computation by an arbitrary factor. The time saved in the encoding process and the remainder computation can be used to perform other more complex decoding algorithms. Thus the present invention facilitates the design and fabrication of, for example, more reliable and higher performance disk drives.

Although the present invention has been described in terms of the presently preferred embodiment, various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. It should therefore be understood that the instant disclosure is not to be interpreted as limiting. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.

Claims

In Re the ClaimsWhat is claimed is:

1. A k-input ECC encoder circuit, wherein k is a natural number greater than one, for encoding input data in accordance with a cyclic ECC code, the circuit comprising:

L+l distinct and independently operating sub-encoders, wherein L is a natural number greater than zero and wherein the sub-encoders operate on k,, k₂, ..., k_L+1 inputs in parallel.

2. The encoder circuit of claim 1, wherein each sub-encoder is a linear finite-state switching circuit.

3. The encoder circuit of claim 2, wherein the cyclic ECC code has a generator polynomial of degree less than k.

4. A k-input remainder computation circuit, where k is a natural number greater than one, for computing remainders of a retrieved code word encoded in accordance with a cyclic ECC code, the circuit comprising:

L+l distinct and independently operating sub-encoders, wherein L is a natural number greater than zero and wherein the sub-encoders operate on k,, k₂, ..., k_L+, inputs in parallel.

5. The remainder computation circuit of claim 4, wherein each sub-encoder is a linear finite-state switching circuit.

6. The remainder computation circuit of claim 5, wherein the cyclic ECC code has a generator polynomial of degree less than k.

7. A k-input ECC encoder and remainder computation circuit, wherein k is a natural number greater than one, for encoding input data in accordance with a cyclic ECC code, the circuit comprising:

L+l distinct and independently operating sub-encoders, wherein L is a natural number greater than zero and wherein the sub-encoders operate on k,, k₂, ..., k_L+, inputs in parallel.

8. The encoder and remainder computation circuit of claim 7, wherein each sub- encoder is a linear finite-state switching circuit.

9. The encoder and remainder computation circuit of claim 8, wherein the cyclic ECC code has a generator polynomial of degree less than k.