WO1997006601A1 - Multi-bit sigma-delta dac - Google Patents

Abstract

In multi-bit sigma-delta digital-to-analog (D/A) conversion, a highly linear switched-capacitor digital-to-analog converter (17) (DAC) in accordance with the invention is employed. The inventive DAC includes an array of holding capacitors (C12, C11, C21, C22) connected in parallel to an opamp (23) having a finite gain. A conversion period is divided into subintervals and each holding capacitor is associated with one of the subintervals. The inventive DAC also includes switches (S10, S20, S12, S22, S11, S21) for transferring a packet of charge to each holding capacitor during the subinterval associated with the holding capacitor.

Description

Description

Multi-bit Sigma-Delta DAC

Technical Field

This invention relates generally to digital-to- analog conversion techniques, and more particularly to a technique for multi-bit sigma-delta digital-to-analog conversion using a highly linear switched-capacitor digital-to-analog converter.

Detailed Description

Sigma-delta digital-to-analog (D/A) converters, including a sigma-delta modulator coupled with a one- bit digital-to-analog converter (DAC) , have been popular for use in integrated circuit (IC) devices for D/A conversion. Their popularity stems in part from the inherently perfect linearity of the one-bit DAC, thereby obviating the requirement of precision component matching to achieve high linearity which otherwise causes undesirable noise and distortion effects on the D/A conversion. However, one of the problems with a one-bit DAC when used for the D/A conversion is the requirement of a large over-sampling ratio and accordingly an operation of a very high speed. As a result, the circuit design of a sigma- delta D/A converter incorporating a one-bit DAC tends to be complex, and provisions for accommodating high power dissipation are also required. In addition, use of the one-bit DAC causes an idle tone problem associated with the sigma-delta modulation in the D/A conversion. An attempt has been made to solve the above-identified problems by using a muti-bit DAC instead. However, use of a multi-bit DAC generally degrades the performance of the sigma-delta D/A converter due to nonlinearity introduced by the DAC.

To achieve high linearity, a multi-bit DAC normally requires precisely matched linear components . For example, in the traditional multi-bit DACs, a binary-weight capacitor array is employed to generate an output analog signal resulting from the sum of a number of packets of charge determined by an input digital word. The linearity of the multi-bit DAC depends largely on the capacitance ratio matching in the array. Such DAC exhibits nonlinearity directly proportional to the capacitor mismatch error, which at least 0.1% using current VLSI technology.

In order to obtain the desired linearity with matched components for a multi-bit DAC, component adjustment techniques calling for use of off-chip precision passive components or laser trimming of on- chip components have been introduced. However, these techniques have disadvantages in significantly boosting the cost of the DAC.

Circuit techniques which improve component matching have also been introduced. Two such circuit techniques --the dynamic element matching technique and self-calibration technique-- are disclosed in U.S. Patent No. 5,305,004 issued April 19, 1994 to

Fattaruso. The disclosed DAC employs a dynamic element matching circuit to randomly select among the capacitors to reduce the effect of mismatching of capacitor values. In addition, a self-calibration circuit is employed to adjust the capacitor values to achieve further tolerance of capacitor mismatch. Unfortunately, the additional circuits introduced by the circuit techniques invariably take up substantial space. Ratio-independent techniques have emerged to achieve high-resolution A/D conversion without use of matched capacitors . One such technique is described in: P. Li et al. , "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique", IEEE Journal of Solid-State Circuits, vol. SC-19, no. 6, pp. 828- 836, December 1984. It calls for algorithmic A/D conversion wherein integral multiplication of the signal required by the conversion is realized by an algorithmic circuit involving charge summing with an integrator and an exchange of capacitors. Another ratio-independent technique is described in: J. Vital et al. , "Novel Capacitance-Ratio Independent Switched-Capacitor Digital-Analogue Converter," Electronics Letters, vol. 25, no. 20, pp. 1362-1363, September 28, 1989. In accordance with this technique, the multi-bit DAC includes a switched- capacitor circuit which processes a digital word, bit- by-bit, by integrating the reference voltage for a number of time slots corresponding to the bit-weight. Nevertheless, the ratio-independent techniques heretofore introduce nonlinearity inversely proportional to the gain of an operational amplifier (opamp) typically employed by those techniques. As such, high performance DACs would require a large opamp gain, which however is difficult to be realized in high-speed circuits.

Accordingly, it is desirable to have a multi-bit DAC for sigma-delta D/A applications which achieves high linearity, without the necessity of precisely matched components or an opamp having a large gain.

Summarv of the Invention

An inventive switched-capacitor DAC is employed for multi-bit sigma-delta D/A applications where a digital signal is converted into an analog signal represented thereby. The DAC in its single-ended form includes an array of N holding capacitors, where N is an integer greater than 1, and an amplifier which may be for example an opamp. In accordance with the invention, a D/A conversion period is divided into N+l subintervals . Each holding capacitor is associated with a respective one of the first N of the N+l subintervals . The DAC also includes switches which are operated in such a manner that each holding capacitor forms a feedback loop across the opamp, and is charged in response to the magnitude of the digital signal to be converted during the subinterval corresponding to the capacitor.

The inventive DAC achieves converter nonlinearity proportional to the ratio of a holding capacitor mismatch error to the opamp gain. By taking advantage of the capacitor matching accuracy afforded by advanced VLSI processing technology, the inventive DAC renders high converter linearity even with a modest opamp gain.

Brief Description of the Drawing Further objects, features and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying figures showing a preferred embodiment of the invention, of which: Fig. 1 is a block diagram of a multi-bit sigma- delta digital-to-analog converter in accordance with the invention;

Fig. 2A illustrates a fully differential multi-bit switched-capacitor digital-to-analog converter and an output buffer in the converter of Fig. 1;

Fig. 2B tabulates certain outputs of a data decoder and clock generator in the converter of Fig. 2A in response to certain inputs thereto;

Fig. 3 is a timing diagram of various signals for controlling the opening and closure of switches in the converter of Fig. 2A; Fig. 4 tabulates the measured performance of the converter of Fig. 1;

Fig. 5 is a generalized multi-bit switched- capacitor digital-to-analog converter in accordance 5 with the invention;

Fig. 6 is a timing diagram of various signals for controlling the opening and closure of switches in the generalized converter of Fig. 5; and

Fig. 7 is a timing diagram modified from Fig. 6 10. and applicable when voltage output of the converter of Fig. 5 is required.

Detailed Description

Fig. 1 illustrates multi-bit sigma-delta D/A

15 converter 10 in accordance with the invention. As shown in Fig. 1, a 24-bit PCM 44 kHz (fs) parallel input data is applied to interpolating filter 13, where it is sampled at 1.408 MHz so that its sample rate is increased to 32 fs, producing 32 samples of 24-bit

20 parallel data for each 24-bit input sample.

Interpolation filter 13 is realized as a 5- stage FIR low-pass filter with 2,459 effective taps, and of the type of the chip DSP56002 manufactured by Motorola, Inc. The output of filter 13 is so determined that the

25 digital equivalent of its amplitude is within a predetermined range, and applied to 24-bit fourth-order delta-sigma modulator 15 of conventional design and of the type of the chip DSP96002 manufactured by Motorola, Inc. Modulator 15 in a standard way quantizes the

30 input data from 24 bits to 5 levels, shapes the quantization noise and removes it from the signal band. In short, with the above oversampling and noise- shaping, the quantization noise spectrum extends beyond the spectrum of the input signal, and thus only a

35 fraction of the noise exists in the signal spectrum. The output signal of modulator 15 is fed to multi-bit DAC 17. This DAC provides a charge signal to buffer 19 which converts it to electric voltage. Buffer 19 also performs a first-order low-pass filtering on the voltage to yield an analog signal, which corresponds to its digital representation at the input of converter 10.

The major problem with a prior art multi-bit sigma delta D/A converter lies in its nonlinearity contributed by a multi-bit DAC therein, which undesirably causes signal distortion and noise.

Perfect linearity usually calls for precisely matched linear components in the DAC, and is extremely difficult to achieve.

Fig. 2A illustrates multi-bit DAC 17 and buffer 19 in accordance with the invention. DAC 17 is a fully differential 5-level charge-mode switched-capacitor (SC) DAC, incorporating an inventive time- and capacitor-multiplexed technique. DAC 17 is fabricated in a 2-μm CMOS technology, and thus compatible with advanced VLSI processing. As shown hereinbelow, the inventive technique achieves converter nonlinearity proportional to the ratio of a capacitor mismatch error to an opamp gain. By taking advantage of the capacitor matching accuracy afforded by advanced VLSI processing technology, the inventive technique renders high converter linearity even with a modest opamp gain.

DAC 17 comprises data decoder and clock generator (DDCG) 21 of conventional design, sampling capacitor pair C₁₀ and C₂₀ (in this embodiment, components of the same pair are denoted with the same second subscript) , first holding capacitor pair C_1X and C₂₁, second holding capacitor pair C₁₂ and C₂₂, and balanced opamp 23. The charging and discharging of the above capacitor pairs are controlled by switch pairs which constitute conventional MOSFET switches. As shown in Fig. 2A, these switch pairs such as switch pair S₁₀ and S₂₀, switch pair S_λl and S₂₁, switch pair S₁₂ and S₂₂ etc., open and close in response to different signals such as Φ_o > Φ 'o i Φ_ι > Φι > 03 ^{M and} sign to be described, and the derivatives thereof. For example, switch pair S₁₀ and S₂₀ operate in response to controlling signals φ_od»M and φ '_{o d}*M , respectively, which are indicated in Fig. 2A next to the switch pair. (The symbol "•" denotes a logical "AND" operator.) The switches are closed when the respective controlling signals are high, and otherwise open. Due to use of MOSFET switches in DAC 17, a signal in Fig. 2A with a subscript d (e) , e.g., φ_od, rises or falls slightly after (before) the signal without the subscript, e.g., φ₀, so as to generate a switching sequence that significantly reduces the undesirable charge injection effects caused by the MOSFET switches .

In addition, for example, switch pair S_xl and S₂₁ operate in response to signals φJ,_d+(φ_od»M) and φ_od+ (φf,_d»M) , respectively. (The symbol "+" denotes a logical "OR" operator, and " " denotes a logical

"COMPLEMENT" operator.) Switch pair S₁₂ and S₂₂ both operate in response to signal φ_le.

DDCG 21 receives, from modulator 15, a digital input comprising three parallel data bits b2, bl and bO (in the order from MSB to LSB) in a two's complement binary format representing one of the possible five quantized levels. DDCG translates the data bits b2, bl, and bO into the sign signal, and the pulse signal M representing the input magnitude m, in accordance with the table in Fig. 2B. Referring to Fig. 2B, DAC 17 translates, for example, input bits 0, 1, and 0 to sign = 0 and = 2 representing a +2 charge level as its output. (In this embodiment, sign = 1 represents a negative charge level, and sign = 0 represents a positive charge level.) In this instance, a +2 charge level output results in a charge signal having +2V_R(C₁₀ + C₂₀) worth of charge at the output of DAC 17, where V_R is a reference voltage to be described. Similarly, a -2 charge level output results in a charge signal having -2V_R(C₁₀ + C₂₀) worth of charge at the output of DAC 17; a +(-)l charge level output results in a charge signal having +(-)V_R(C₁₀ + C₂₀) worth of charge at the output; and a 0 charge level output results in a charge signal having no charge at the output.

In response to an input clock signal denoted φ₀, DDCG 21 also generates clock signals φ₀, φ '₀ , φ_1# φ₂, and φ₃. Fig. 3 is a timing diagram illustrating these clock signals, the sign signal, and the pulse signals M(m=0) , M(m=l) and M(m=2) although it should be noted that only one pulse signal M is applied during a conversion period (1/fs) depending on the value of m. As shown in Fig. 3, clock signal φ₀ has a period (or subinterval) one-third as long as the conversion period.

Opamp 23 is a single-stage amplifier, designed with a gain of 70 dB, unity-gain frequency of 63 MHz, input referred white noise of 3.9 nV/Vϊiz , setting to

0.0001% in 70 ns, and power dissipation of 17 mW. The supply voltages (not shown) for the circuitry in Fig. 2A are ±5V. The reference voltage V_R (V_R = 3.5V in this instance) is also provided at switch pair S10 and S20. The operation of DAC 17 is further described hereinbelow with reference to a generalized DAC in accordance with the invention. It suffices to know for now that DAC 17 provides to buffer 19 a charge signal corresponding to a charge level represented by the 3 input bits described above. This charge signal is applied across damping capacitor C_ex0 in buffer 19 to limit voltage spikes that can cause distortion due to nonlinearity within the input stage of opamp 25. The latter is a two-stage class AB opamp, measured with a gain of 94 dB with a load capacitance of 50 pf and resistance of 600 ohms, unity-gain frequency of 35 MHz, total in-band (audio band) noise of -100 dB with a 7.5 Vp-p full scale signal, and power dissipation of 138 W. The output of opamp 25 is filtered by a first order low-pass filter comprised of resistor-capacitor 5 pairs R_exl-C_ex2 and R_ex2-C_ex2.

Fig. 4 tabulates the measured performance of converter 10. As shown in Fig. 4, among other things, converter 10 advantageously commands a dynamic range of 92 dB and a total harmonic distortion (THD) of less

10. than -94 dB.

Fig. 5 shows generalized (N+l) level SC DAC 50 in accordance with the invention, where N is an integer greater than 1. In fact, DAC 17 is a fully differential version of DAC 50 with N = 2. In theory,

15 DAC 50 (with N=2) which is in single-ended form performs a function equivalent to DAC 17. However, in practice, the fully differential form is preferred as it allows an increased input signal dynamic range. It is also capable of suppressing common-mode noise/errors

20 in a circuit, such as digital noise coupled through power supplies and substrates, distortions caused by the voltage dependence of the integrated poly-poly capacitors, and channel charge injection and clock feed-through common in SC circuits.

25 Traditionally, a fully differential version of DAC 50 can be generated by including the configuration of DAC 50 and its mirror image reflected on an imaginary mirror across opamp 53. Thus, in deriving DAC 17 from DAC 50 (with N = 2) , one would (a) substitute opamp 53

30 of DAC 50 with balanced opamp 23, and (b) reproduce the capacitors and switches of DAC 50 symmetrically about opamp 23. However, a closer look at DAC 17 reveals that it is slightly different from the fully- differential DAC constructed in the above manner

35 although it can be shown they are equivalent circuits. Their differences stem in part from avoiding use of an additional clock signal φ_N+1 (with N=2) in DAC 17, and minimizing the number of switches in each feedback loop across opamp 23. Referring to Fig. 6 together with Fig. 5, Fig. 6 shows a general timing diagram of the signals controlling the opening and closure of switches of DAC 50. DAC 50 is a parasitic-insensitive SC integrator- type DAC, comprising a sampling capacitor C₀ and an array of N holding (or integrating) capacitors C-. through C_N. The sampling capacitor C₀ and each of holding capacitors C_x through C_N are of equal size. As shown in Fig. 6, each conversion period is divided into (N+l) subintervals denoted T. In each of the first N subintervals, only one of the N holding capacitors in the array is connected in the feedback loop of the SC integrator (for example, C_k, is connected in the loop in the k^th subinterval) . The remaining (N- 1) capacitors are isolated, either holding the charge already on them or waiting for their turns to be connected in the loop. Two phases of operations are carried out within a subinterval: sampling either the reference voltage source V_R or the GND by C₀ in phase one (when φ₀ is high) and transferring charge from C₀ to the corresponding holding capacitor for the subinterval in phase two (when φ '₀ is high) . The input magnitude, m (0 ≤ m ≤ N) , is encoded into a pulse signal M whose ON-duration (or high-duration) is exactly m subintervals. In the first m subintervals of a conversion period, V_R is sampled by C₀ while the holding capacitor in the feedback loop is discharged in phase one. In phase two, a packet of charge Q₀ = V_RC₀ is transferred from C₀ to the holding capacitor. A total number of m packets of charge are transferred at the end of m^th subinterval, one to each of m holding capacitors C_x through C_m in the array. In the next (N- m) subintervals, C₀ samples the GND instead, and (N-m) packets of charge Q₀ = 0 are transferred, one to each of the remaining capacitors in the array. In the last subinterval, all holding capacitors in the array are connected in parallel and their charges are combined forming an output charge signal having charge Q₀= mV_RC₀, assuming that opamp 53 is ideal and there are no mismatches among the holding capacitors in the array. The reference charge is Q_R= (NV_RC₀) . In practice, however, opamp 53 has a finite gain and offset voltage, and the holding capacitors exhibit mismatches . The offset voltage sampled by C₀ in phase one is cancelled in phase two and therefore does not affect the conversion linearity when charge is the output signal. The finite opamp gain results in incomplete charge transfer because the inverting input node of opamp 53 cannot be forced to be the true virtual ground, and therefore, some residue charge is left on C₀ at the end of phase two. This residue charge is different in each subinterval when a different holding capacitor is connected in the feedback loop. Assume that the gain of opamp 53 be A₀ and capacitor mismatch error be δ, ' such that C_k = (l+δ_k)C₀, and |δ_k|≤δ. With an input magnitude of m, the charge on each of the holding capacitors in the array at the end of N^h subinterval of a conversion period is

The residue charge on C₀ in the k^ch subinterval (k≤m) iε Q_k =(l-δ_k)V_R C₀/A₀, which is a very small fraction of one LSB charge packet, V_RC_C. It is even smaller when the differences among m residue charges are considered, resulting in high linearity. For example, the maximum differential nonlinearity is DNL_max = 2δ/A₀ of one LSB.

It can be shown that the nonlinearity of DAC 50 at the i^εh output level is:

A closer look at this formula reveals that the maximum nonlinearity occurs when the first half of the holding capacitors take one extreme value and the second half take the other extreme value. For example, consider

C_k = (l+δ)C₀, g_k = g_max - l-[(l-δ)/A₀] for A₀ >> 1, C, = (l-δ)C₀, and g. = g_mιn = 1- [ (1+δ) /A₀] , for k= 1, ..., N/2, and j=(N+l)/2, ..., N, where N is an even integer. The maximum integral nonlinearity then becomes:

ΔO_nax = ^-f^ ( g_max - g_mιn) = -^ (NV_RC₀ )

Both differential and integral nonlinearities are functions of δ/A₀. By using capacitor multiplexing, any capacitor mismatches of less than 100% helps improve the linearity performance beyond what can be achieved with the finite opamp gain. With δ = 0.01 and A₀= 1,000 (or 60 dB) , both readily obtainable in today's CMOS technology, the maximum integral nonlinearity is 0.0005% of the reference charge (NV_RC₀) . This is in contrast to the ratio independent methods where a gain of at least 100,000 is needed to achieve the same performance.

The presence of parasitic capacitance (C_parasιtlc) at the inverting input node of opamp 53 degrades the linearity performance of DAC 50 linearity as -δ_k) c p, arasi tic •

9_k ^{a 1} ( 1 and,

A "r0, "-o

A O_max = -^ ( l ÷ ^C »»^ ) (W,C₀ ) .

This effect is negligible if C_parasιcιc << C₀.

As mentioned before, charge injection from analog MOSFET switches and clock feedthrough can cause nonlinearities. However, these effects can be minimized by employing a fully differential configuration such as that of DAC 17 and proper switching sequences described above. The fact that all holding capacitors always experience the same switching sequence also helps to reduce the effects of these nonidealities.

The foregoing merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise numerous D/A converter arrangements which, although not explicitly shown or described herein, embody the principles of the invention and are thus within the spirit and scope of the invention.

For example, in some applicationε, it is desirable to have voltage rather than charge as the analog output signal of DAC 50. Some modifications in timing are εhown in Fig. 7, where φ_N+1 is kept high all the time, and in the last subinterval, φ s (i = 1, ..., N) are kept high only during phase two. DAC 50 operates the same way in the first N εubintervals of a conversion period as described earlier. In phase one of the last subinterval, opamp 53 is in the unity-gain configuration and C₀ is discharged. In phase two all N holding capacitors in the array are connected in parallel between the inverting input node and the output node of opamp 53. After their charges are rediεtributed, the final output voltage at the output node of opamp 53 for an input digital signal with m is

where g_ouc is a constant very close to 1, V_os is the offset voltage of the opamp.

Since the contribution of the V_os is the same for all analog output values, it does not affect the linearity performance of the DAC. The maximum integral nonlinearity due to the finite opamp gain and capacitor mismatches is:

( C ■ \

A V 1 + P^araΞ1 t^l max * - _2A V_R

Co

which is the same result as in the charge output case when the parasitic capacitance at the inverting input node of the opamp is considered. However, the voltage dependence of the holding capacitors causes additional nonlinearity in this case. In general, the voltage dependence of a capacitor can be expressed aε C(V) = C (1+ a_xV + a₂V + ...) where V iε the voltage across the capacitor, C is the capacitance when V=0, and a^s are the voltage coefficients of the capacitor. Assuming that everything else in DAC 50 is ideal, and that a_x dominates the voltage dependence, the maximum integral nonlinearity DAC 50 is Δ V_max -- ■ V_R . With a₁ ranges

between 10 and 100 ppm/V for a poly-poly capacitor and V_R = 3V, the worst case nonlinearity is 0.0075%, which iε not good enough for today's high performance converters . Fully differential topology, such as that of DAC 17, helps by cancelling out the even order harmonic distortions due to the capacitance voltage coefficientε. One well-known technique to alleviate this problem iε to εplit each holding capacitor into two halves and connect the top plate of one half to the bottom plate of the other half, and vice versa, and any voltage dependence of the capacitor would be effectively cancelled.

Claims

Claimε

1. Apparatus for converting a digital signal to an analog signal represented thereby during a conversion period comprising: a clock generator for defining N+l subintervals within said conversion period, where N is an integer greater than 1; a decoder responsive to said digital signal for generating at least a magnitude signal representative of a magnitude of said analog signal; an amplifier; and N capacitor means, each capacitor means being associated with a respective one of first N of said N+l subintervals, and each capacitor means forming a feedback path between an output and an input of said amplifier and being charged in response to said magnitude signal during the subinterval associated with the capacitor means .

2. The apparatus of claim 1 wherein said N capacitor means include capacitors each having substantially the same capacitance.

3. The apparatus of claim 1 wherein each subinterval is of equal length.

4. The apparatus of claim 1 wherein said amplifier is an operational amplifier (opamp) .

5. The apparatus of claim 4 wherein said opamp is a balanced opamp.

6. The apparatus of claim 1 being of a fully differential design, wherein each of said N capacitor means comprises a pair of substantially identical capacitors.

7. The apparatuε of claim 1 further comprising a sampler for oversampling said digital signal.

8. The apparatus of claim 7 wherein said sampler includes an interpolation filter.

9. The apparatus of claim 8 wherein said interpolation filter is a low-pass filter.

10. The apparatus of claim 7 further comprising a delta-sigma modulator for shaping noise in the εampled digital εignal.

11. Apparatus for converting a digital signal to an analog signal represented thereby during a conversion period comprising: a clock generator for defining N+l subintervals within said conversion period, where N is an integer greater than 1; a decoder responsive to said digital signal for generating at least a magnitude signal representative of a magnitude m of said analog signal, where 0 ≤ m ≤ N; an amplifier; N capacitor means, each capacitor means being associated with a respective one of first N of said N+l subintervals; and switching means for transferring a packet of charge to each capacitor means during the subinterval associated therewith in selected m of said first N subintervalε, for tranεferring zero charge to each capacitor meanε during the subinterval asεociated therewith in the remaining (N-m) of said first N subintervals, and for connecting said N capacitor means in parallel to said amplifier in the (N+l)^th subinterval.

12. The apparatus of claim 11 wherein said switching means includes at least one switch which, when closed, transfers said packet of charge.

13. The apparatus of claim 11 wherein said N capacitor means include capacitors each having substantially the same capacitance.

14. The apparatus of claim 11 wherein each subinterval is of equal length.

15. The apparatus of claim 11 wherein said amplifier is an opamp.

16. The apparatus of claim 15 wherein said opamp is a balanced opamp. '

17. The apparatus of claim 11 being of a fully differential design, wherein each of said N capacitor means comprises a pair of substantially identical capacitors.

18. The apparatus of claim 11 further comprising a sampler for oversampling said digital signal.

19. The apparatus of claim 18 wherein said sampler includes an interpolation filter.

20. The apparatus of claim 19 wherein said interpolation filter is a low-pass filter.

21. The apparatus of claim 18 further comprising a delta-sigma modulator for shaping noise in the sampled digital signal.

22. A method for use in apparatus for converting a digital signal to an analog signal represented thereby during a conversion period, said apparatus including an amplifier and N capacitor means, where N is an integer greater than 1, said method comprising the steps of: defining N+l subintervals within said conversion period, each capacitor means being associated with a respective one of first N of said N+l subintervals; generating, in response to said digital signal, at least a magnitude signal representative of a magnitude of said analog signal; and forming a feedback path between an output and an input of said amplifier using one of said N capacitor means and charging each capacitor means in response to said magnitude signal during the subinterval associated with the capacitor means.

23. The method of claim 22 wherein each subinterval is of equal length.

24. The method of claim 22 further comprising the step of oversampling said digital signal.

25. The method of claim 24 further comprising the step of shaping noise in the sampled digital signal.

26. A method for use in apparatus for converting a digital signal to an analog signal represented thereby during a conversion period, said apparatuε including an amplifier, switching means and N capacitor means, where N is an integer greater than 1, said method comprising the stepε of: defining N+l subintervals within said conversion period, each capacitor means being associated with a respective one of first N of said N+l subintervals; generating, in response to said digital signal, at least a magnitude signal representative of a magnitude m of said analog signal, where 0 ≤ m ≤ N; and transferring a packet of charge to each capacitor means during the subinterval asεociated therewith in εelected m of εaid firεt N subintervals, transferring zero charge to each capacitor means during the subinterval associated therewith in the remaining (N-m) of said first N subintervals, and connecting said N capacitor means in parallel to said amplifier in the (N+l)^ch subinterval.

27. The method of claim 26 wherein each subinterval is of equal length.

28. The method of claim 26 further comprising the step of oversampling said digital signal.

29. The method of claim 28 further comprising the step of shaping noise in the sampled digital signal.