WO1995032521A1 - Method for forming solder bumps - Google Patents

Method for forming solder bumps Download PDF

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Publication number
WO1995032521A1
WO1995032521A1 PCT/US1995/000800 US9500800W WO9532521A1 WO 1995032521 A1 WO1995032521 A1 WO 1995032521A1 US 9500800 W US9500800 W US 9500800W WO 9532521 A1 WO9532521 A1 WO 9532521A1
Authority
WO
WIPO (PCT)
Prior art keywords
phosphoric acid
recited
layer
approximately
acid solution
Prior art date
Application number
PCT/US1995/000800
Other languages
French (fr)
Inventor
Mark H. Baker
Original Assignee
National Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Priority to EP95908602A priority Critical patent/EP0711454B1/en
Priority to KR1019960700354A priority patent/KR100323657B1/en
Priority to DE69512991T priority patent/DE69512991T2/en
Publication of WO1995032521A1 publication Critical patent/WO1995032521A1/en

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie

Definitions

  • This invention relates generally to etching processes m semiconductor wafer processing and more specifically to solder bump processing in flip chip technology.
  • IC integrated circuit
  • a traditional method of input-output (I/O) interconnection is wirebonding This involves the bonding of I/O pads around the periphery of the wafer die with wires on a leadframe, followed by encapsulation into a chip package or packaging in a cavity-type package.
  • An example of a typical wirebond is illustrated in Figure la. As shown, a die 10 is bonded to a leadframe or substrate surface 12 by a wire bond 14. While this is a satisfactory implementation, the wafer area required for the bond pads rest ⁇ cts full utilization of wafer dies with increasing feature density on a single die.
  • TAB bonding Another form of interconnection is known as tape automated bonding or TAB bonding.
  • the lead frame is bonded to a die by means of a tape placed over the die.
  • One side of the tape goes over the die.
  • the other side of the tape goes on the leadframe or interconnects to a substrate board
  • Contacts on the die are plated up, i.e., grown above the circuit, to form "bump" contacts on the IC so that the passivation layers on the die are not cracked by the application of the tape. While this has been used successfully for many years in semiconductor manufacturing, there are risks of cracking the die during the tape application and forming sites of destruction, so that some fabrication facilities have begun to phase it out for cost-effectiveness reasons. Cost is also a factor since custom tapes are needed for each specific chip design.
  • flip chip technology provides an increased density of possible interconnections on a single die without risking the integrity of the die.
  • Flip chip devices implement connections directly on the wafer so that the wafer can be "flipped" over, as the name implies, and bonded directly to a substrate, such as bonding to trace pattern wiring pads on a printed circuit board The bonding is done via solder bumps, i.e., soldered areas formed on top of the die.
  • Figure lb illustrates a chip 16 having solder bumps 18 connecting it to a substrate 20 It is the integrity of these solder bumps that determines the integrity of the interconnection and chip functionality for a given use
  • these solder bumps are formed by depositing a layer of solder into openings over bond pads on a patterned wafer and then etching the areas outside these soldered bond pads to leave the solder bumps 18.
  • Solder deposition includes using evaporation methods, which are expensive and time-consuming, or using plating techniques.
  • the etched areas are typically multiple metal cathode layers each of which requires a separate etching and cleaning step for removal. For example, aluminum, nickel, and copper are typical metals used for the metal layers.
  • a standard etchant for the copper and nickel layers is a nitric acid solution, while a strongly phosphoric acid (>80% phosphoric acid) solution is commonly used for the aluminum layer.
  • These etchants have been found to attack the applied solder, making them less than ideal for solder bump formation.
  • each time the wafer is etched and cleaned to remove each of the metal layers there is an increased risk of contamination and degradation of the solder bumps, so that every added step increases production time and cost. Therefore, in a continuing effort to improve upon solder bump formation, the present invention uses a dilute phosphoric acid solution to remove the metal layers in a more efficient and effective manner without degrading the solder layer. In this way, a simpler, one-step etching process results, which offers less waste production and less chemical consumption.
  • a method for forming solder bumps begins with a semiconductor wafer that has been patterned with bond pad areas. A plurality of distinct metal layers are then deposited over the wafer. Subsequently, solder is deposited by way of plating through a mask over the metal layers in the bond pad areas. After the removal of the mask, the metal layers outside of the soldered areas are etched using a dilute phosphoric acid solution, which includes phosphoric acid, acetic acid, hydrogen peroxide, and deionized water. By the use of this solution, the metal layers are removed without attacking the soldered areas. Thus, a pattern of solder bumps are formed on the integrated circuit (IC) wafer.
  • IC integrated circuit
  • the metal layers include distinct layers of aluminum, nickel-vanadium, and copper.
  • the aluminum layer is eliminated.
  • the composition of the dilute phosphoric acid solution includes approximately 1 to 25% phosphoric acid, 63 to 98% deionized water, 1 to 10% acetic acid, and 0.1 to 2% hydrogen peroxide by volume for use in the etching step.
  • a single etchant in the form of a dilute phosphoric acid solution, is used to remove the deposited metal layers outside of the soldered areas. This increases the efficiency of forming solder bumps of high integrity, which are suitable for flip chip applications.
  • Figure l is an illustration of a wire bond of the prior art
  • Figure lb is an illustration of a standard solder bumped die inverted on a substrate
  • Figure 2a illustrates an initial substrate with bond pads and passivation layers
  • Figure 2b illustrates the substrate of Figure 2a with the addition of a plurality of metal layers
  • Figure 2c illustrates the substrate of Figure 2b with a photoresistive mask
  • Figure 2d illustrates the substrate of Figure 2c with solder deposited through the mask
  • Figure 2e illustrates the substrate of Figure 2d following the removal of the mask and the metal layers outside of the deposited solder leaving a series of solder bumps
  • Figure 3 is a flow diagram illustrating an overall process for forming the solder bumps illustrated in Figure 2e.
  • FIGS. 2a-2e illustrate the step-by-step appearance of a substrate processed in accordance with a method of the present invention, the overall steps of which are presented with reference to Figure 3.
  • FIG. 2a illustrates an initial substrate 30, which may be formed of any suitable material such as a silicon wafer or gallium arsenide wafer that may be patterned to include many layers of features, as is appreciated by those skilled in the art. and that is generically referred to as a substrate for purposes of this description.
  • the topmost layer of substrate 30 has been patterned to have bond pads 32 and passivation layers 34.
  • the bond pads 32 are formed by depositing a layer of aluminum (Al) over the substrate 30 and patterning the layer to form the bond pads 32.
  • the passivation layers 34 preferably include silicon dioxide deposited by chemical vapor deposition (CVD) or other suitable methods as is well known to those skilled in the art.
  • the passivation layers are etched using standard techniques from the bond pads 32, so that the bond pads 32 are exposed for subsequent interconnecting.
  • Figure 2b illustrates the addition of metal layers 36. 38, and 40 over the passivation layers 34 and bond pads 32.
  • the substrate completed through passivation, is ashed, wet cleaned, sputter etched, and sputter deposited.
  • the first layer may be an approximately 4 kiloAngstrom (k ⁇ ) layer of aluminum (Al) for layer 36, which acts as an adhesive layer.
  • An approximately 2 kA layer of nickel-vanadium (NiV) is then deposited for layer 38 to act as a barrier layer to prevent migration between the surrounding metal layers.
  • the NiV comprises approximately 93% nickel and 7% vanadium.
  • An approximately 4 kA layer of copper (Cu) then follows for layer 40, which acts as a cathode layer for subsequent solder plating.
  • the thickness of these layers may be varied in accordance with the needs of a particular system.
  • a layer of photoresistive material 42 is deposited and openings 44 are developed over the bond pad areas by standard photolithographic techniques, the results of which are illustrated in Figure 2c.
  • the openings 44 expose the areas in which the solder is to be plated.
  • Figure 2d illustrates the solder-filled areas 46 formed by plating solder over the metal layers on the bond pads.
  • lead/tin solders may be used in the solder plating step. By way of example, solder having in the range of approximately 60-95% lead and 5-40% tin has been found to work well.
  • layer 40 acts as the cathode in order to seed the solder deposition, as is well known to those skilled in the art.
  • solder bumps 48 solder bumps 48, as shown in Figure 2e.
  • the composition of this dilute phosphoric acid solution is preferably approximately in the range of 1 to 25% by volume phosphoric acid, 1 to 10% by volume acetic acid, 0.1 to 2% by volume hydrogen peroxide, and 63 to 98% by volume deionized (DI) water.
  • etching times approximately in the range of 90 to 600 seconds are appropriate, with 130 seconds having been found to work well, when the solution is approximately 10% phosphoric acid. 5% acetic acid, 1% hydrogen peroxide, and 84% DI water.
  • the etching may be performed at a wide variety of temperatures, and the temperature used will in turn affect the appropriate duration of the etch, as is appreciated by those skilled in the art.
  • the dilute phosphoric acid solution does not attack the solder layer as other standard acid etchant solutions do.
  • these other standard solutions include a nickel/copper acid etchant and an acid solution used for aluminum etching.
  • the nickel/copper acid etchant a dilute nitric acid solution
  • Table 1 the nickel/copper acid etchant, a dilute nitric acid solution
  • the aluminum etchant. a strongly phosphoric acid solution, has approximately 83% phosphoric acid, 11% acetic acid, and 6% DI water and is usually applied at about 60°C. Both of these have been found to attack deposited solder, so that neither of these standard etchants is as well suited for performing the etching that the dilute phosphoric acid solution of the present invention performs.
  • Figure 3 is a flow diagram illustrating the overall steps (shown in Figures 2a-2e) for forming a series of solder bumps.
  • the process begins in step 100 with wafers which have been processed up through passivation layering (see Fig. 2a).
  • step 102. is the formation of a plurality of metal layers, as shown in Figure 2b.
  • the wafer is first ashed and then wet cleaned, sputter etched, and sputter deposited, as previously described.
  • a layer to approximately 4 kA of aluminum (Al) may be first sputter deposited, followed by an approximately 2 kA layer of nickel vanadium (NiV) and an approximately 4 kA layer of copper (Cu).
  • a layer of photoresist is then deposited over the wafer in step 104. This layer is then patterned by standard photolithographic techniques to open the bond pad areas of the wafer, as shown in Figure 2c. Following an ashing and wet clean, solder is plated into the openings of the photoresist to build up the bumps in step 106 (e.g., Figure 2d). Upon the completion of the plating, the photoresist is stripped using standard techniques in step 108.
  • step 1 10 is the etching of the sputter deposited metal layers outside of the soldered areas.
  • each layer i.e., the Cu layer, the NiV layer, and the Al layer, would have to be etched in separate etching steps with a cleaning step performed in between each etch.
  • all three metal layers are etched during one step using a dilute phosphoric acid solution.
  • the preferable composition of this solution is approximately in the range of 1 to 25% phosphoric acid by volume, 1 to 10% acetic acid by volume, 0.1 to 2% hydrogen peroxide by volume, and the remaining balance 63 to 98% deionized (DI) water by volume.
  • DI deionized
  • the aluminum layer acting as the adhesive layer in the three metal layer arrangement may be eliminated.
  • the remaining metal layer thicknesses are preferably adjusted to maintain a total thickness approximately equal to the three layer thickness, e.g., 1 micron.
  • the seed layer of copper is replaced by gold.
  • the etching sequence is slightly altered.
  • the gold layer is first removed using potassium cyanide (KCN) applied for approximately 60 seconds at an approximate temperature of 40°C, for example, before the dilute phosphoric acid solution is used to etch the remaining metal layers.
  • KCN potassium cyanide
  • duration and temperature of the etching are interrelated.
  • increases in the duration of etching correspond to decreases in etching temperature or decreases in phosphoric acid concentration.
  • the etching time is approximately 600 seconds, while the solution having approximately 10% by volume phosphoric acid requires etching for approximately 130 seconds and the solution having approximately 25% by volume phosphoric acid requires etching for approximately 90 seconds.
  • the described solution has more than approximately 32% by volume phosphoric acid, no discernible etching of metal layer NiV occurs.

Abstract

In accordance with the present invention, a method for forming solder bumps begins with a wafer that has been patterned with bond pad areas. A plurality of distinct metal layers are then deposited over the wafer. Subsequently, solder is deposited by way of plating through a mask over the metal layers in the bond pad areas. After the removal of the mask, the metal layers outside of the soldered areas are etched using a dilute phosphoric acid solution, which includes phosphoric acid, acetic acid, hydrogen peroxide, and deionized water. By the use of this solution, the metal layers are removed without attacking the soldered areas. Thus, a pattern of solder bumps are formed. The metal layers include distinct layers of aluminum, nickel-vanadium, and copper. Alternatively, the aluminum layer is eliminated. Further, the dilute phosphoric acid solution has approximately 10 % phosphoric acid, 84 % deionized water, 5 % acetic acid, and 1 % hydrogen peroxide by volume, which is used for the etching step preferably performed at a temperature of approximately 70 °C for a period between about 60 to 600 seconds. With the present invention, a single etchant, a dilute phosphoric acid solution, is used to remove the deposited metal layers outside of the soldered areas. This increases the efficiency of forming solder bumps of high integrity, which are then suitable for flip chip applications.

Description

Method for Forming Solder Bumps
BACKGROUND OF THE INVENTION
This invention relates generally to etching processes m semiconductor wafer processing and more specifically to solder bump processing in flip chip technology.
The formation of integrated circuit (IC) chips involves many processes From design to production, each aspect requires considerable attention to detail and precision to create and maintain a high yield of functioning chips. One such aspect is the method employed for interconnection and packaging of a patterned wafer die.
A traditional method of input-output (I/O) interconnection is wirebonding This involves the bonding of I/O pads around the periphery of the wafer die with wires on a leadframe, followed by encapsulation into a chip package or packaging in a cavity-type package. An example of a typical wirebond is illustrated in Figure la. As shown, a die 10 is bonded to a leadframe or substrate surface 12 by a wire bond 14. While this is a satisfactory implementation, the wafer area required for the bond pads restπcts full utilization of wafer dies with increasing feature density on a single die.
Another form of interconnection is known as tape automated bonding or TAB bonding. In this method, the lead frame is bonded to a die by means of a tape placed over the die. One side of the tape goes over the die. while the other side of the tape goes on the leadframe or interconnects to a substrate board Contacts on the die are plated up, i.e., grown above the circuit, to form "bump" contacts on the IC so that the passivation layers on the die are not cracked by the application of the tape. While this has been used successfully for many years in semiconductor manufacturing, there are risks of cracking the die during the tape application and forming sites of destruction, so that some fabrication facilities have begun to phase it out for cost-effectiveness reasons. Cost is also a factor since custom tapes are needed for each specific chip design.
Alternatively, flip chip technology provides an increased density of possible interconnections on a single die without risking the integrity of the die. Flip chip devices implement connections directly on the wafer so that the wafer can be "flipped" over, as the name implies, and bonded directly to a substrate, such as bonding to trace pattern wiring pads on a printed circuit board The bonding is done via solder bumps, i.e., soldered areas formed on top of the die. Figure lb illustrates a chip 16 having solder bumps 18 connecting it to a substrate 20 It is the integrity of these solder bumps that determines the integrity of the interconnection and chip functionality for a given use In prior art practices, these solder bumps are formed by depositing a layer of solder into openings over bond pads on a patterned wafer and then etching the areas outside these soldered bond pads to leave the solder bumps 18. Solder deposition includes using evaporation methods, which are expensive and time-consuming, or using plating techniques. The etched areas are typically multiple metal cathode layers each of which requires a separate etching and cleaning step for removal. For example, aluminum, nickel, and copper are typical metals used for the metal layers. Accordingly, a standard etchant for the copper and nickel layers is a nitric acid solution, while a strongly phosphoric acid (>80% phosphoric acid) solution is commonly used for the aluminum layer. These etchants have been found to attack the applied solder, making them less than ideal for solder bump formation. Further, each time the wafer is etched and cleaned to remove each of the metal layers, there is an increased risk of contamination and degradation of the solder bumps, so that every added step increases production time and cost. Therefore, in a continuing effort to improve upon solder bump formation, the present invention uses a dilute phosphoric acid solution to remove the metal layers in a more efficient and effective manner without degrading the solder layer. In this way, a simpler, one-step etching process results, which offers less waste production and less chemical consumption.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming solder bumps begins with a semiconductor wafer that has been patterned with bond pad areas. A plurality of distinct metal layers are then deposited over the wafer. Subsequently, solder is deposited by way of plating through a mask over the metal layers in the bond pad areas. After the removal of the mask, the metal layers outside of the soldered areas are etched using a dilute phosphoric acid solution, which includes phosphoric acid, acetic acid, hydrogen peroxide, and deionized water. By the use of this solution, the metal layers are removed without attacking the soldered areas. Thus, a pattern of solder bumps are formed on the integrated circuit (IC) wafer.
In one embodiment, the metal layers include distinct layers of aluminum, nickel-vanadium, and copper. In an alternate embodiment, the aluminum layer is eliminated. By way of example, the composition of the dilute phosphoric acid solution includes approximately 1 to 25% phosphoric acid, 63 to 98% deionized water, 1 to 10% acetic acid, and 0.1 to 2% hydrogen peroxide by volume for use in the etching step.
With the present invention, a single etchant, in the form of a dilute phosphoric acid solution, is used to remove the deposited metal layers outside of the soldered areas. This increases the efficiency of forming solder bumps of high integrity, which are suitable for flip chip applications. BRIEF DESCRIPTION OF THE DRAWINGS
The invention, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
Figure l is an illustration of a wire bond of the prior art;
Figure lb is an illustration of a standard solder bumped die inverted on a substrate;
Figure 2a illustrates an initial substrate with bond pads and passivation layers;
Figure 2b illustrates the substrate of Figure 2a with the addition of a plurality of metal layers;
Figure 2c illustrates the substrate of Figure 2b with a photoresistive mask;
Figure 2d illustrates the substrate of Figure 2c with solder deposited through the mask;
Figure 2e illustrates the substrate of Figure 2d following the removal of the mask and the metal layers outside of the deposited solder leaving a series of solder bumps; and
Figure 3 is a flow diagram illustrating an overall process for forming the solder bumps illustrated in Figure 2e.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention relates to solder bump formation for use in flip chip IC interconnection. Figures 2a-2e illustrate the step-by-step appearance of a substrate processed in accordance with a method of the present invention, the overall steps of which are presented with reference to Figure 3.
Figure 2a illustrates an initial substrate 30, which may be formed of any suitable material such as a silicon wafer or gallium arsenide wafer that may be patterned to include many layers of features, as is appreciated by those skilled in the art. and that is generically referred to as a substrate for purposes of this description. The topmost layer of substrate 30 has been patterned to have bond pads 32 and passivation layers 34. The bond pads 32 are formed by depositing a layer of aluminum (Al) over the substrate 30 and patterning the layer to form the bond pads 32. The passivation layers 34 preferably include silicon dioxide deposited by chemical vapor deposition (CVD) or other suitable methods as is well known to those skilled in the art. The passivation layers are etched using standard techniques from the bond pads 32, so that the bond pads 32 are exposed for subsequent interconnecting.
Figure 2b illustrates the addition of metal layers 36. 38, and 40 over the passivation layers 34 and bond pads 32. For the application of metal layers 36-40. the substrate, completed through passivation, is ashed, wet cleaned, sputter etched, and sputter deposited. By way of example, the first layer may be an approximately 4 kiloAngstrom (kλ) layer of aluminum (Al) for layer 36, which acts as an adhesive layer. An approximately 2 kA layer of nickel-vanadium (NiV) is then deposited for layer 38 to act as a barrier layer to prevent migration between the surrounding metal layers. Typically, the NiV comprises approximately 93% nickel and 7% vanadium. An approximately 4 kA layer of copper (Cu) then follows for layer 40, which acts as a cathode layer for subsequent solder plating. Of course, the thickness of these layers may be varied in accordance with the needs of a particular system.
Following the deposition of the metal layers 36-40, a layer of photoresistive material 42 is deposited and openings 44 are developed over the bond pad areas by standard photolithographic techniques, the results of which are illustrated in Figure 2c. The openings 44 expose the areas in which the solder is to be plated. Figure 2d illustrates the solder-filled areas 46 formed by plating solder over the metal layers on the bond pads. A wide variety of lead/tin solders may be used in the solder plating step. By way of example, solder having in the range of approximately 60-95% lead and 5-40% tin has been found to work well. During the plating process, layer 40 acts as the cathode in order to seed the solder deposition, as is well known to those skilled in the art.
Once the solder has been plated through the openings 44. the photoresistive material is removed in a stripper by standard removal techniques. All of the metal layers 36-40 outside of the solder-filled areas 46 are then etched using a dilute phosphoric acid solution to leave solder bumps 48, as shown in Figure 2e. The composition of this dilute phosphoric acid solution is preferably approximately in the range of 1 to 25% by volume phosphoric acid, 1 to 10% by volume acetic acid, 0.1 to 2% by volume hydrogen peroxide, and 63 to 98% by volume deionized (DI) water. By way of example, when the etching is done at about 70°C, etching times approximately in the range of 90 to 600 seconds are appropriate, with 130 seconds having been found to work well, when the solution is approximately 10% phosphoric acid. 5% acetic acid, 1% hydrogen peroxide, and 84% DI water. Of course, the etching may be performed at a wide variety of temperatures, and the temperature used will in turn affect the appropriate duration of the etch, as is appreciated by those skilled in the art. When used in this manner, the dilute phosphoric acid solution does not attack the solder layer as other standard acid etchant solutions do.
In comparative experiments, these other standard solutions include a nickel/copper acid etchant and an acid solution used for aluminum etching. As shown in the following table, Table 1, the nickel/copper acid etchant, a dilute nitric acid solution, has approximately 84% DI water. 10% nitric acid, 5% acetic acid, and 1% hydrogen peroxide and is usually applied at about 50°C. The aluminum etchant. a strongly phosphoric acid solution, has approximately 83% phosphoric acid, 11% acetic acid, and 6% DI water and is usually applied at about 60°C. Both of these have been found to attack deposited solder, so that neither of these standard etchants is as well suited for performing the etching that the dilute phosphoric acid solution of the present invention performs.
TABLE 1
Ni/Cu Etch Al Etch Dilute Phosphoric
DI Water: 84% 6% 86%
Acetic Acid: 5% 11% 4%
H2O2: 1% 1%
Phosphoric Acid: 83% 9%
Nitric Acid: 10%
Temperature: 50°C 60°C 70°C
In accordance with the present invention, Figure 3 is a flow diagram illustrating the overall steps (shown in Figures 2a-2e) for forming a series of solder bumps. The process begins in step 100 with wafers which have been processed up through passivation layering (see Fig. 2a). The next step, step 102. is the formation of a plurality of metal layers, as shown in Figure 2b. The wafer is first ashed and then wet cleaned, sputter etched, and sputter deposited, as previously described. Again, by way of example, a layer to approximately 4 kA of aluminum (Al) may be first sputter deposited, followed by an approximately 2 kA layer of nickel vanadium (NiV) and an approximately 4 kA layer of copper (Cu). A layer of photoresist is then deposited over the wafer in step 104. This layer is then patterned by standard photolithographic techniques to open the bond pad areas of the wafer, as shown in Figure 2c. Following an ashing and wet clean, solder is plated into the openings of the photoresist to build up the bumps in step 106 (e.g., Figure 2d). Upon the completion of the plating, the photoresist is stripped using standard techniques in step 108. The next step, step 1 10, is the etching of the sputter deposited metal layers outside of the soldered areas. In prior art practices, each layer, i.e., the Cu layer, the NiV layer, and the Al layer, would have to be etched in separate etching steps with a cleaning step performed in between each etch. In the present invention, all three metal layers are etched during one step using a dilute phosphoric acid solution. Again, the preferable composition of this solution is approximately in the range of 1 to 25% phosphoric acid by volume, 1 to 10% acetic acid by volume, 0.1 to 2% hydrogen peroxide by volume, and the remaining balance 63 to 98% deionized (DI) water by volume. The results of this etching step are shown in Figure 2e, which illustrates that by this process, solder bumps are formed with one etching step without negatively affecting the size, shape, or integrity of the bump.
In an alternate embodiment, the aluminum layer acting as the adhesive layer in the three metal layer arrangement may be eliminated. For this embodiment, the remaining metal layer thicknesses are preferably adjusted to maintain a total thickness approximately equal to the three layer thickness, e.g., 1 micron.
In another alternate embodiment, the seed layer of copper is replaced by gold. In this case, the etching sequence is slightly altered. The gold layer is first removed using potassium cyanide (KCN) applied for approximately 60 seconds at an approximate temperature of 40°C, for example, before the dilute phosphoric acid solution is used to etch the remaining metal layers.
Although only a few embodiments of the present invention have been described in detail, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, the invention has been described in the context of solder deposition involving plating. Alternatively, an evaporation deposition process could also be performed. Further, the composition of the solder may be varied. Although the solder has been described as a lead and tin combination, pure tin solder could also be used.
Further, as will be appreciated by those skilled in the art, variations of the duration and temperature of the etching along with the percentage composition of the etchant components are interrelated. Thus, increases in the duration of etching correspond to decreases in etching temperature or decreases in phosphoric acid concentration. For example, for the solution having approximately 1% by volume phosphoric acid, the etching time is approximately 600 seconds, while the solution having approximately 10% by volume phosphoric acid requires etching for approximately 130 seconds and the solution having approximately 25% by volume phosphoric acid requires etching for approximately 90 seconds. However, when the described solution has more than approximately 32% by volume phosphoric acid, no discernible etching of metal layer NiV occurs.

Claims

C L A I M S
1 . A method for forming solder bumps on a substrate, said substrate including bond pad areas, the method comprising the steps of:
depositing a plurality of distinct metal layers over said substrate;
depositing solder through a mask over said metal layers in said bond pad areas;
removing said mask; and
etching said metal layers outside of said solder with a dilute phosphoric acid solution comprising phosphoric acid, deionized (DI) water, acetic acid, and hydrogen peroxide that does not attack said solder to leave a series of solder bumps on said substrate in said bond pad areas.
2. A method as recited in claim 1 wherein said dilute phosphoric acid solution is applied at approximately 70°C.
3. A method as recited in claim 2 wherein said dilute phosphoric acid solution is applied for approximately in the range of 90 to 600 seconds.
4. A method as recited in claim 1 wherein said dilute phosphoric acid solution includes in the range of approximately 1 to 25 % by volume phosphoric acid.
5. A method as recited in claim 4 wherein said dilute phosphoric acid solution includes approximately 10% by volume phosphoric acid.
6. A method as recited in claim 1 wherein said dilute phosphoric acid solution includes in the range of approximately 63 to 98% by volume DI water.
7. A method as recited in claim 6 wherein said dilute phosphoric acid solution includes approximately 84% by volume DI water.
8. A method as recited in claim 1 wherein said dilute phosphoric acid solution includes in the range of approximately 1 to 10 % by volume acetic acid.
9. A method as recited in claim 8 wherein said dilute phosphoric acid solution includes approximately 5% by volume acetic acid.
10. A method as recited in claim 1 wherein said dilute phosphoric acid solution includes in the range of approximately 0.1 to 2 % by volume hydrogen peroxide.
1 1 A method as recited in claim 10 wherein said dilute phosphoric acid solution includes approximately 1% by volume hydrogen peroxide
12 A method as recited 1 wherein said metal layers include a layer of aluminum, a layer of nickel-vanadium, and a layer of copper
13 A method as recited 1 wherein said metal layers include a layer of nickel -vanadium and a layer of copper
14 A method as recited in claim 1 wherein said metal layers include a top layer of gold, and further wherein said gold layer is etched with potassium cyanide prior to said step of etching with said dilute phosphoric acid solution
15. A method for forming solder bumps over a substrate having a pattern of bond pad areas and a passivation layer deposited over said substrate and patterned to have openings in said bond pad areas, the method compnsing the steps of
depositing a plurality of distinct metal layers over a substrate,
depositing a photoresistive layer over said metal layers;
developing openings in said photoresistive layer over said bond pad areas on said substrate;
plating solder over said metal layers into said openings,
removing said photoresistive layer; and
etching exposed metal layers from said substrate outside of said solder with a dilute phosphoric acid solution without etching said solder to leave a series of solder bumps on said substrate.
16. A method as recited in claim 15 wherein said dilute phosphoric acid solution compπses phosphoric acid, deionized (DI) water, acetic acid, and hydrogen peroxide.
17 A method as recited in claim 15 wherein said dilute phosphoric acid consists substantially ot phosphoric acid, deionized (DI) water, acetic acid, and hydrogen peroxide.
18 A method as >ecιted in claim 15 wherein said step of etching is performed at approximately 70°C
19 A method as recited in claim 15 wherein said dilute phosphoric acid solution includes in the range of approximately 1 to 25 % by volume phosphoric acid
20. A method as recited in claim 17 wherein said dilute phosphoric acid solution includes approximately 10% by volume phosphoric acid.
21. A method as recited in claim 15 wherein said dilute phosphoric acid solution includes in the range of approximately 63 to 98 % by volume DI water.
22. A method as recited in claim 21 wherein said dilute phosphoric acid solution includes approximately 84% by volume DI water.
23. A method as recited in claim 15 wherein said dilute phosphoric acid solution includes in the range of approximately 1 to 10 % by volume acetic acid.
24. A method as recited in claim 23 wherein said dilute phosphoric acid solution includes approximately 5% by volume acetic acid.
25. A method as recited in claim 15 wherein said dilute phosphoric acid solution includes in the range of approximately 0.1 to 2 % by volume hydrogen peroxide.
26. A method as recited in claim 25 wherein said dilute phosphoric acid solution includes approximately 1% by volume hydrogen peroxide.
27. A method as recited claim 15 wherein said step of depositing further comprises depositing a layer of aluminum over said substrate, depositing a layer of nickel-vanadium over said layer of aluminum, and depositing a layer of copper over said layer of nickel-vanadium.
28. A method as recited claim 15 wherein said step of depositing further comprises depositing a layer of nickel-vanadium over said substrate and depositing a layer of copper over said layer of nickel-vanadium.
29. A method as recited claim 15 wherein said step of depositing further comprises depositing a layer of aluminum over said substrate, depositing a layer of nickel-vanadium over said layer of aluminum, and depositing a layer of gold over said layer of nickel-vanadium, and wherein said method further includes the step of etching said layer of gold with potassium cyanide prior to said step of etching with a dilute phosphoric acid solution.
30. A method as recited in claim 15 wherein said solder comprises lead and tin.
31. A method as recited in claim 30 wherein approximately 60-95% of said solder is lead and approximately 5-40% is tin.
32. An integrated circuit chip having solder bumps for use in a flip chip application, said chip comprising: a substrate having a pattern of bond pad areas and a passivation layer covering said substrate outside of said bond pad areas;
a plurality of distinct metal layers covering said substrate including said bond pad areas and said passivation layer;
a solder layer plated over said multiple metal layers through a mask in said pattern of bond pad areas; and
solder bumps isolated over said bond pad areas after removing said mask by etching said metal layers with a dilute phosphoric acid solution.
33. An integrated circuit chip as recited in claim 32 wherein said substrate comprises a silicon wafer.
34. An integrated circuit chip as recited in claim 32 wherein said metal layers comprise aluminum, nickel-vanadium, and copper.
35. An integrated circuit chip as recited in claim 32 wherein said solder layer comprises lead and tin.
36. An integrated circuit chip as recited in claim 32 wherein said dilute phosphoric acid comprises approximately 10% phosphoric acid, 84% deionized (DI) water, 5% acetic acid, and 1% hydrogen peroxide by volume.
PCT/US1995/000800 1994-05-24 1995-01-20 Method for forming solder bumps WO1995032521A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP95908602A EP0711454B1 (en) 1994-05-24 1995-01-20 Method for forming solder bumps
KR1019960700354A KR100323657B1 (en) 1994-05-24 1995-01-20 How to Form Soul the Bump
DE69512991T DE69512991T2 (en) 1994-05-24 1995-01-20 SOLDER STOOL PRODUCTION METHOD

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US08/248,409 US5508229A (en) 1994-05-24 1994-05-24 Method for forming solder bumps in semiconductor devices

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WO1995032521A1 true WO1995032521A1 (en) 1995-11-30

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EP0711454A1 (en) 1996-05-15
DE69512991T2 (en) 2000-05-31
KR100323657B1 (en) 2002-06-24
DE69512991D1 (en) 1999-12-02
KR960705348A (en) 1996-10-09
US5508229A (en) 1996-04-16
EP0711454B1 (en) 1999-10-27

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