WO1995026045A1 - Method for producing integrated components - Google Patents
Method for producing integrated components Download PDFInfo
- Publication number
- WO1995026045A1 WO1995026045A1 PCT/SE1995/000296 SE9500296W WO9526045A1 WO 1995026045 A1 WO1995026045 A1 WO 1995026045A1 SE 9500296 W SE9500296 W SE 9500296W WO 9526045 A1 WO9526045 A1 WO 9526045A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- process step
- region
- substrate
- semiconductor device
- layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 230000000873 masking effect Effects 0.000 claims abstract description 14
- 239000011248 coating agent Substances 0.000 claims abstract description 3
- 238000000576 coating method Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000001419 dependent effect Effects 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 150000002736 metal compounds Chemical class 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000004377 microelectronic Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Bipolar Transistors (AREA)
Abstract
The present invention discloses a method to avoid additional masking steps in the manufacturing of semiconductor components, by generating an asymmetrical process step which will be self-aligned to an earlier made material structure (20) on a substrate (30), by in the asymmetrical process step illuminating the substrate at a given angle of incidence (40) to create a shadowed region (25), and utilizing the shadowed region (25), which in the asymmetrical process step is shadowed by the previously formed material structure (20), whereby, if the region (25) is coated, the process step, will not act on this coating, and, if the region (25) is not coated, the process step will still not be able to act on the region, respectively, by what means the region (25) for this process step thus will act as if there were a mask present, without having to perform any previous masking step.
Description
Method for producing integrated components.
Field of invention
The present invention relates to a method for producing inte¬ grated components and more particularly for the forming of microelectronic structures with a reduced number of masking steps.
Background of the invention
Today, modern microelectronics processes involve a great number of different masking steps (numbers of 20-30 are not being rare) . Each masking step is time-consuming, causes a decreasing yield and thus a significant part of the total cost. Therefore, it is of great interest to minimize the number of masking steps. It is also difficult to maintain a high resolution and small line width when a large number of masks have to be aligned to each other. This problem will increase further when shrinking the size of the devices.
The particular problem in steps to align a mask to a previous one, has driven the technology towards self-aligning by utilizing that a structure itself could act as a mask in a following pro¬ cess step.
An example of a self-aligned process step is presented in a paper "A Self-Aligned Lateral Bipolar Transistor Realized on SIMOX- Material" by B. Edholm et al. , IEEE Transactions on Electron Devices, Vol 40, No. 12, December 1993, where a nitride spacer is used to align the base and the emitter to the collector region in a lateral bipolar transistor. An other similar example is the formation of a spacer at the gate structure in a MOS device.
However, the self-aligned processes disclosed in the examples above are symmetric around an earlier defined feature. When an asymmetric structure has to be formed, as in the case of a lateral bipolar transistor, this technique can not be used without an additional mask step to create the asymmetry.
Also in the case of a MOS structure, utilizing a lightly doped
drain electrode, it is advantageous to avoid a lightly doped source side. This can not be done utilizing prior art self- aligned methods.
To conclude, there is a need of a self-aligned asymmetric process step in order to substantially reduce the number of critical mask steps in the microelectronic manufacturing process.
In a future microelectronic manufacturing process, cluster systems are expected to replace present technology. This will further increase the demand of an asymmetric self-aligned process, since mask steps are difficult to implement in cluster tools.
Summary of invention
An object of the present invention is to overcome the above described prior art problems and drawbacks and to provide a method for forming self-aligned asymmetric structures without the use of additional aligned mask steps.
According to a first object of the method of the present inven¬ tion to avoid additional masking steps in the manufacturing of semiconductor components, comprising generation of an asymmetrical process step which will be self-aligned to an earlier made material structure on a substrate by in said asymmetrical process step illuminating said substrate at a given angle of incidence to create a shadowed region, and utilizing said shadowed region, which in said asymmetrical process step is shadowed by the previously formed material structure, whereby if said region is coated said process step will not act on this coating, and if said region is not coated said process step will still not be able to act on said region, respectively, by what means said region for this process step thus will act as if there were a mask present, without having to perform any previous masking step.
According to a second object of the method of the present inven-
tion this shadow region is used to define an area or areas where an ion implantation process step, a depositing process step or an etch process step having a certain angle of incidence will not be acting on the substrate to define a specific semiconductor device region, said specific semiconductor device region being any of a base, an emitter or a collector definition in a bipolar component, or a channel, a source, drain or gate region in a field effect component.
According to a third object of the method of the present inven¬ tion a remaining part of material defined in a previous step by said shadow region is used in a next step to protect an area or areas where an ion implantation process step, a depositing pro¬ cess step or an etch process having a certain angle of incidence will be acting on the substrate to define specific semiconductor device region, said specific semiconductor device region being any of a base, an emitter or a collector definition in a bipolar component or a channel, a source, drain or gate region in a field effect component.
According to a fourth object of the method of the present inven¬ tion a remaining part of material defined in a previous step by said shadow region will be forming the contact electrode to a specific semiconductor device region, said specific semiconductor device region being any of a base, an emitter or a collector definition in a bipolar component or a channel, a source, drain or gate region in a field effect component.
According to a fifth object of the method of the present inven¬ tion a remaining part of a layer defined by the shadow region is utilized to protect the substrate and/or one of the vertical sides of the structure during a subsequent etch process step or any another following process step.
Brief description of the drawings
The objects, features and advantages of the present invention as mentioned above will become apparent from the description of the
invention given below in conjunction with the drawings, in which:
Fig. 1 shows an asymmetric structure to be formed by etching from a well defined angle according to the present invention,*
Fig. 2 shows an asymmetric structure to be formed by ion implantation at a well defined angle according to the present invention,*
Fig. 3 shows an asymmetric structure to be formed by depo¬ sition from a well defined angle according to the present invention;
Fig. 4 shows an asymmetric structure to be formed by etching or deposition from a well defined angle according to the present invention when the residue is used to protect one side of the structure during further processing;
Fig. 5 shows an initial structure, consisting of a patterned multi layer of oxide-polysilicon-nitride on top of a substrate,*
Fig. 6 a nitride layer been deposited over the structure defined in figure 5;
Fig. 7 shows the structure after that the deposited nitride film has been partly etched, leaving nitride spacers;
Fig. 8 shows the structure after a local oxidation where the remaining nitride has worked as a mask;
Fig. 9 shows the structure after that the nitride has been removed;
Fig. 10 shows the structure after a polysilicon film has been
deposited and the deposited polysilicon will be used for contacting the base region;
Fig. 11 shows the structure after the polysilicon has been etched using technique according to the present invention, leaving a contact to the base region;
Fig. 12 shows the way the base region is implanted and defined when utilizing the method of the present invention;
Fig. 13 shows the way the collector and emitter regions are implanted and defined when utilizing the present invention,*
Fig. 14 shows the final contact definition to separate the different contacts which is made by spacers of oxide, which may be followed by a self-aligned silicidation process.
Detailed description
In a number of steps and referring to figures 1 - 4 of the drawings, the present invention will be described in an exempli¬ fying embodiment. When etching, implanting or depositing is utilized a shadow region 25 from a structure 20. In this way asymmetrically self-aligned regions or structures will be created.
Fig. la demonstrates a substrate 30 on which has been formed a structure 20 which at the moment also will serve as a mask. A typical height of the structure may be of the order 0,1 - 1 μm. A layer 10 is covering the substrate 30 and the structure 20. When at a given angle of incidence illuminating the substrate 30 with the structure 20 and the layer 10 by, for instance, an ion beam 40 or any similar source, a portion 11 of the material 10 is left at a shadowed region. The extension of this shadow region 25 along the substrate 30 is depending of the height of the structure 20 as well as of the angle of the radiation 40. If for
simplicity the angle of incidence should be 45° then this shadow region will have an extension corresponding to the height of the structure 20 and the steeper this angle of incidence gets the smaller the extent of the shadow region will be. Thus a certain amount of remaining material 11 will be determined by the height of the structure 20 and direction 40 in for instance an etching process by the radiation 40 as is indicated in fig. lb. The etching process could as indicated above be an ion beam assisted etching process with an angular dependent etch rate which is well known by a person skilled in the art.
In fig 2 is demonstrated the use of the shadow region 25 to asymmetrically implant regions, 12 and 13, which then are defined by an ion implantation 40 having a defined incident angle.
When depositing a layer 10 of a material on top of the substrate 30 having the structure 20 at a certain angle of incidence, as is indicated in fig. 3, the shadow region 25 formed by the structure 20 will implement that asymmetrically deposited regions of the material 10 are being formed around the structure 20. The deposition process could for example be evaporation, where the evaporation source is placed in such way that the deposited mate¬ rial has a desired incident angle in respect to the substrate 30.
Utilizing the shadow region 25 at the structure 20 according to the method of the present invention, one side of the structure 20 will be protected from subsequent process steps by a residue 11 of a previously deposited and partly removed material 10 as was shown in fig. lb. An example of such a series of steps is shown in figure 4a - 4c. If the structure 20 consists of two different layers, a material 21 and a material 22, having different etching properties, the material 22 is partly etched away from one side of the structure 20, as shown in fig. 4a. In a subsequent step, shown in figure 4b, a new material 50 is regularly deposited over the top surface. In figure 4c finally the new material 50 is removed but leaving a residue 51.
Common to all steps demonstrated in figs. 1 - 4 no alignment of new masks was necessary as the shadow region 25 is playing the important role to generate the necessary protection needed instead of an additional masking step. Having perfect parallel irradiation and by selecting a proper angle of incidence the shadow region 25 will easily be producing a line width producing even a better resolution than at the moment available high resolution masks.
Further examples of embodiments
The method according to the present invention may be utilized to extensively reduce the number of masking steps in a manufacturing process of a lateral bipolar transistor. In figs. 5 - 14 is shown a manufacturing process sequence when making a lateral bipolar transistor and according to the present invention only one mask step will be used to define doping areas and contacts.
Utilizing the present invention, the device will manufactured with only one mask step. In figure 5 is shown an initial structure, consisting of amultilayered oxide-polysilicon-nitride structure 22, 21, 23 on top of a substrate. To form a structure similar to structure 20 in fig 1 the rest of the layers 21, 22, 23 have been etched down to the substrate in for example an ordinary masking step well known to a person skilled in the art. On top of the structure, a nitride layer 50 is deposited, as shown in fig. 6. Nitride spacers 51, 52 are then formed, as shown in fig. 7, using dry etching. The remaining nitride 23, 51, 52 will be used as the mask for the subsequential local oxidation. Figure 8 shows the structure after a local oxidation step forming the areas 31 and 32. Subsequent the remaining nitride spacers 51 and 52 as well as the nitride layer 23 are removed as indicated in fig. 9, and a layer of polysilicon 10 is deposited as shown in fig. 10. This layer will asymmetrically be removed partly leaving a residue 11 according to the present invention which is shown i fig. 11, which thus is similar to fig. lb.
The remaining polysilicon will then work as a contact to the
region intended to constitute a base region as indicated in figure 11. A base region 41 is then asymmetrically implanted at a defined angle of incidence at the same time as a region 42, utilizing the technique according to the method of the present invention technique, as demonstrated in fig. 12. In fig. 13 emitter and collector regions 46, 47 are defined by the same technique but using a different angle of incidence. Finally, in fig. 14, oxide spacers 61 and 62 are formed to separate the different contact areas for a subsequential self-aligned silicidation process.
Consequently the production of a lateral bipolar transistor when starting from a readily prepared multilayered oxide-polysilicon- nitride mesa structure is completed in accordance with the method of the present invention in a self-aligned way without adding any more masks which will have to be accurately aligned.
As will readily be recognised by a person skilled in the art the method according to the present invention is not limited to the production of a lateral bipolar transistor, but may be utilized for the production any type of integrated component on a sub¬ strate where the disclosed asymmetric process step is adequate and will avoid the otherwise necessary extra masking step according to the state of the art.
Claims
1. A method to decrease the number of masking steps in the manufacturing of semiconductor components, characterized in generation of an asymmetrical process step which will be self- aligned to an earlier made material structure (20) on a substrate (30) by in said asymmetrical process step illuminating said substrate at a given angle of incidence (40) to create a shadowed region (25) , and utilizing said shadowed region (25) , which in said asymmetrical process step is shadowed by the previously formed material structure (20) , whereby if said region (25) is coated said process step will not act on this coating, and if said region (25) is not coated said process step will still not be able to act on said region, respectively, by what means said region (25) for this process step thus will act as if there were a mask present, without having to perform any previous masking step.
2. The method according to claim 1, characterized in that said shadow region (25) is used to define an area or areas where an ion implantation process step, a depositing process step or an etch process step, which has a certain angle (40) of incidence will not be acting on the substrate (30) to define a specific semiconductor device region, said specific semiconductor device region being any of a base, an emitter or a collector definition in a bipolar component or a channel, a source, a drain or a gate region in a field effect component.
3. The method according to claim 1, characterized in that a remaining part of material defined in a previous step by said shadow region (25) is used in a next step to protect an area or areas where an ion implantation process step, a depositing process step or an etch process step, which has a certain angle
(40) of incidence will be acting on the substrate (30) to define specific semiconductor device region, said specific semiconductor device region being any of a base, an emitter or a collector definition in a bipolar component or a channel, a source, a drain or a gate region in a field effect component.
4. The method according to claim 1, characterized in that a remaining part of material (11) defined in a previous step by said shadow region (25) is forming a contact electrode to a specific semiconductor device region, said specific semiconductor device region being any of a base, an emitter or a collector definition in a bipolar component or a channel, a source, a drain or a gate region in a field effect component.
5. The method according to claim 1, characterized in that said earlier made material structure (20) , comprises at least one silicon dioxide or one silicon nitride layer.
6. The method according to claim 1, characterized in that a layer (10) being deposited on the substrate (30) and said earlier made material structure (20) comprises silicon or a compound including silicon atoms.
7. The method according to claim 1, characterized in that a layer (10) being deposited on the substrate (30) and said earlier made material structure (20) consists of a metal or a metal compound.
8. The method according to claim 6 or 7, characterized in that a remaining part (11) of said layer (10) defined by said shadow region (25) is utilized to protect the substrate (30) and/or one of the vertical sides of said structure (20) during a subsequent etch process step or another following process step.
9. The method according to claim 8, characterized in that said following process step is an oxidization step.
10. The method according to claim 8, characterized in that said following process step is an isotropic etch or material removal.
11. The method according to claim 1, characterized in that the substrate (30) which the the direction dependent process step is acting on, consists of a multilayer structure where the direction dependent process step enables a subsequnet process step to asymmetrically act or get in contact with an underlying layer in the substrate (30) without necessitating said process step to be direction dependen or asymmetrically applied.
12. The method according to claims 1 and 11, characterized in that the substrate (30) consists of at least one insulating layer and one conducting or semiconducting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU21534/95A AU2153495A (en) | 1994-03-24 | 1995-03-22 | Method for producing integrated components |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9401000-6 | 1994-03-24 | ||
| SE9401000A SE506433C2 (en) | 1994-03-24 | 1994-03-24 | Method of manufacturing integrated components |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1995026045A1 true WO1995026045A1 (en) | 1995-09-28 |
Family
ID=20393411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/SE1995/000296 WO1995026045A1 (en) | 1994-03-24 | 1995-03-22 | Method for producing integrated components |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU2153495A (en) |
| SE (1) | SE506433C2 (en) |
| WO (1) | WO1995026045A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6686233B2 (en) | 2000-11-03 | 2004-02-03 | Telefonaktiebolaget Lm Ericsson | Integration of high voltage self-aligned MOS components |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3873371A (en) * | 1972-11-07 | 1975-03-25 | Hughes Aircraft Co | Small geometry charge coupled device and process for fabricating same |
| US4771012A (en) * | 1986-06-13 | 1988-09-13 | Matsushita Electric Industrial Co., Ltd. | Method of making symmetrically controlled implanted regions using rotational angle of the substrate |
| US5258319A (en) * | 1988-02-19 | 1993-11-02 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step |
-
1994
- 1994-03-24 SE SE9401000A patent/SE506433C2/en not_active IP Right Cessation
-
1995
- 1995-03-22 WO PCT/SE1995/000296 patent/WO1995026045A1/en active Application Filing
- 1995-03-22 AU AU21534/95A patent/AU2153495A/en not_active Abandoned
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3873371A (en) * | 1972-11-07 | 1975-03-25 | Hughes Aircraft Co | Small geometry charge coupled device and process for fabricating same |
| US4771012A (en) * | 1986-06-13 | 1988-09-13 | Matsushita Electric Industrial Co., Ltd. | Method of making symmetrically controlled implanted regions using rotational angle of the substrate |
| US5258319A (en) * | 1988-02-19 | 1993-11-02 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6686233B2 (en) | 2000-11-03 | 2004-02-03 | Telefonaktiebolaget Lm Ericsson | Integration of high voltage self-aligned MOS components |
Also Published As
| Publication number | Publication date |
|---|---|
| SE9401000L (en) | 1995-09-25 |
| SE506433C2 (en) | 1997-12-15 |
| AU2153495A (en) | 1995-10-09 |
| SE9401000D0 (en) | 1994-03-24 |
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