WO1995019596A1 - Addressable communication port expander - Google Patents

Addressable communication port expander Download PDF

Info

Publication number
WO1995019596A1
WO1995019596A1 PCT/US1995/000323 US9500323W WO9519596A1 WO 1995019596 A1 WO1995019596 A1 WO 1995019596A1 US 9500323 W US9500323 W US 9500323W WO 9519596 A1 WO9519596 A1 WO 9519596A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
input port
output ports
signal
computer
Prior art date
Application number
PCT/US1995/000323
Other languages
French (fr)
Inventor
Rodger T. Lovrenich
Original Assignee
Teramar Group, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teramar Group, Inc. filed Critical Teramar Group, Inc.
Publication of WO1995019596A1 publication Critical patent/WO1995019596A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Definitions

  • This invention generally relates to computer data communications, and more particularly, to comrnu- nication between a computer and a plurality of periph ⁇ eral devices .
  • serial communications Transmission of digital data using serial communications is a long established practice in the art of data communication. With the advent of the digital computer, and specifically personal computers, the use of serial communications has become commonplace. Personal computers use serial communication to drive peripheral devices, such as printers, plotters, modems, and page scanners, via serial output ports located on each computer.
  • the RS-232 standard defined by specifi ⁇ cation EIA-232-D, is the predominant standard by which serial communication is performed using a personal computer.
  • many personal computers contain at least one RS-232 serial port, wired in a data terminal equipment (DTE) configuration, for communication with peripheral devices containing an RS-232 serial port wired in a data circuit-terminating equipment (DCE) configuration.
  • DTE data terminal equipment
  • DCE data circuit-terminating equipment
  • a difference between the DTE and DCE configurations is a result of reversing a data receive line (also known as an RD line or an RXD line) with a data transmit line (also known as a TD line or a TXD line) .
  • a data receive line also known as an RD line or an RXD line
  • a data transmit line also known as a TD line or a TXD line
  • Such electron ⁇ ic instrumentation devices include digital voltmeters, ammeters, power meters, pressure meters, flow meters, and thermometers .
  • electronic.instrumentation devices have incorporat ⁇ ed RS-232 serial ports therein to enable data to be transferred to a computer.
  • RS-232 protocol has been favor ⁇ ably employed for interfacing conventional peripheral devices to computers
  • its scope of application is limited by its inherent design for communication between a single sending device and a single receiving device, namely, a single computer and a single peripheral device. Therefore, an unaccompanied use of a single RS-232 port presents an obstacle in applications where a large number of peripheral devices are to be inter- faced to the computer, such as a power plant or any general process control application wherein many instru ⁇ mentation devices are to be monitored.
  • One method of interfacing a plurality of peripheral devices to a single RS-232 port on a computer is by wiring, in parallel, the RS-232 ports on the peripheral devices to the RS-232 port on the computer.
  • parallel wiring does allow the same serial data to be sent to the plurality of peripheral devices, difficulties arise when the peripheral devices attempt to transmit data to the computer.
  • damage to either a peripheral device or the computer can result when two peripheral devices simultaneously attempt to impress different voltages on the same parallel-wired line.
  • An improved approach to handling data from multiple RS-232 devices is to employ one RS-232 computer port for each device.
  • Many personal computers have software provision for four serial ports (C0M1, COM2, COM3, and COM4), although only two of these ports have operating-system-specified software interrupts.
  • C0M1, COM2, COM3, and COM4 serial ports
  • this approach is currently limited to applications having no greater than four peripheral devices.
  • Another approach is to install a multi-port expansion board in an internal computer slot.
  • the number of serial ports can be extended up to eight.
  • the multi-port board approach suffers in that the number of peripheral devices is limited to the number of output ports on the board. This limitation is significant in applications such as power plant monitor- ing, where the number of devices that need to be ac ⁇ Ded can be more than a dozen, with 16 or 32 peripher ⁇ al devices being common.
  • a more flexible method for communication between a single computer port and many remote peripher- al devices is based on a serial communication standard defined by EIA specification RS-485.
  • the RS-485 stan ⁇ dard utilizes tri-state outputs on the sending units of each remote device, in other words, each device output is either high, low, or off.
  • the computer When the computer needs to exchange data with a specific device, the computer first sends an address for a selected peripheral device of interest on a transmit line of the computer.
  • each peripheral device must have inherent addressing circuitry so that it can recognize its own address code.
  • the individual address code for each peripheral device is set by the positions of a number of DIP switches on the device.
  • the device After the selected peripheral device has recognized that its address code was sent on the transmit line of the computer, the device activates its output and seizes a receive line of the computer. When the receive line of the computer is seized, other devices on the system must release the receive line of the computer by putting their respective device output in the off state to avoid incapacitating any messages sent from the addressed device. All devices that are not sending data to the computer must be in the off state so that there is no contention for the computer's receive line.
  • a shortcom ⁇ ing of the RS-485 protocol is that if identical address codes are assigned to more than one remote device, the possibility exists of a system malfunction caused by two devices forcing two different voltage levels on the receive line of the computer. Moreover, many peripheral devices are not equipped to communicate using the RS-485 standard.
  • a method of providing parallel communications between a computer and a plurality of peripheral devices employs the IEEE-488 interface bus.
  • IEEE-488 has been applied to a wide variety of conventional peripherals, such as disk drives, printers, and plotters, along with programmable instrumentation devices such as data recorders, oscilloscopes, and digital voltmeters.”
  • Hewlett-Packard has combined the IEEE-488 standard with a communication system that allows devices on the IEEE-488 bus to communicate with one another, the combination being known as HPIB.
  • the HPIB interface is currently limited to no more than 15 devices being connected in parallel on an HPIB bus.
  • SCSI Small Computer Systems Interface
  • ANSI American National Standards Institute
  • a SCSI bus is designed to support up to eight devices (includ ⁇ ing the computer) with up to 2,048 addressable units per device. Data may be transferred using SCSI not only to and from the host computer, but between peripheral devices as well.
  • a shortcoming of SCSI is in its general unavailability as an option for instrumentation devices. Further, the cost of providing the intelli ⁇ gence mandated by the SCSI protocol can be prohibitive for some applications.
  • Another object of the present invention is to provide the multiplexed output ports to remote peripher ⁇ al devices not having inherent addressing circuitry.
  • a further object is to provide a computer interfacing system which can be constructed using conventional integrated circuit components.
  • a still further object is to include presence detectability in a computer interface, wherein the presence can be detected by a computer using routine transmitted and received data signals.
  • the present invention provides a cascadable computer interface apparatus for providing a data communication path between an input port and a selected one of a plurality of output ports.
  • the apparatus comprises a data selec ⁇ tor circuit which provides the data communication path between the input port and the selected one of the plurality of output ports based upon a received signal indicating the selected one of the plurality of output ports.
  • the apparatus further comprises a secondary signal generator responsive to the received signal, which provides a secondary signal to each of the plural ⁇ ity of output ports capable of driving a like cascadable computer interface apparatus, wherein the secondary signal is derived from a previous received signal.
  • the present invention further provides a computer interface appara ⁇ tus for providing a data communication path between an input port and a selected one of a plurality of output ports, wherein the input port and each of the plurality of output ports is a RS-232 port having a data transmit line, a data receive line, a first control line, and a second control line.
  • the apparatus comprises a shift register having a data input, a clock input, and a plurality of outputs.
  • the data input is responsive to a first control signal received from the -first control line of the input port, and the clock input is respon ⁇ sive to a second control signal received from the second control line, so that the plurality of outputs identi- fies the selected one of the plurality of output ports.
  • the apparatus further comprises a multiplexer which responds to the plurality of outputs of the shift register to provide a first data transmission path between the data transmit line of the selected one of the plurality of output ports and the data receive line of the input port.
  • the apparatus further comprises a demultiplexer with responds to the plurality of outputs of the shift register to provide a second data transmis ⁇ sion path between the data transmit line of the input port and the data receive line of the selected one of the plurality of output ports.
  • the first control line of each of the plurality of output ports is coupled to a selected one of plurality of output ports
  • the second control line of each of the plurality of output ports is coupled to the second control line of the input port.
  • the present invention still further provides a system for providing a data communication path between a computer and a selected one of a plurality of peripheral devices.
  • One or more cascadable interfaces wherein each of the interfaces has an input port and a plurality of output ports, are coupled in a tree-like configuration such that each of the plurality of peripheral devices is coupled to the computer by a cascade of at least one of the one or more cascadable interfaces.
  • Each of the interfaces is capable of providing a local data communi- cation path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port.
  • Each of the inter ⁇ faces is further capable of providing a secondary address signal at each of the plurality of output ports capable of driving a like cascadable interface, wherein the secondary address signal is derived from a previous address signal received at the input port.
  • the data communication path is provided in response to a global address signal generated by the computer, wherein the global address signal contains the address signal for each local data communication path forming the cascade of the at least one of the one or more interfaces coupling the selected one of the peripheral devices to the computer.
  • the present invention yet further provides a cascadable computer interface apparatus for providing a first data communi ⁇ cation path between an input port and each of a plurali ⁇ ty of output ports, and for providing a second data communication path between the input port and a selected one of the plurality of output ports.
  • the first data communication path is provided by coupling means between the input port and each of the plurality of output - 9 -
  • a data selector circuit provides the second data communication path between the input port and the selected one of the plurality of output ports based upon a received signal indicating the selected one of the plurality of output ports.
  • a secondary signal generator provides a secondary signal, derived from a previous received signal, to each of the plurality of output ports capable of driving a like cascadable computer interface apparatus.
  • the present invention yet still further provides a computer inter ⁇ face apparatus for providing a first data communication path between an input port and each of a plurality of output ports, and for providing a second data communica- tion path between the input port and a selected one of the plurality of output ports, wherein the input port and each of the plurality of output ports is a parallel communications port having at least one selectable data line, at least one fixed data line, a first control line, and a second control line.
  • a bus provides the first data communication path by coupling in parallel the at least one fixed data line of the input port to the at least one fixed data line of each of the plurali ⁇ ty of output ports.
  • a plurality of outputs of a shift register having a data input responsive to a first control signal received from the first control line of the input port, and a clock input responsive to a second control signal received from the second control line, identifies the selected one of the plurality of output ports.
  • At least one multiplexer provides at least one data transmission path from the at least one selectable data line of the selected one of the plurality of output ports to the at least one selectable data line of the • 10 -
  • the first control line of each of the plurality of output ports is coupled to a selected one of the plurality of outputs of the shift register, and the second control line of each of the plurality of output ports is coupled to the second control line of the input port.
  • the present invention further provides a computer interface appara- tus.
  • the apparatus comprises a serial input port, a plurality of serial output ports, and a data selector which provides a data communication path between the serial input port and a selected one of the plurality of serial output ports in response to a received signal indicating the selected one of the plurality of serial output ports.
  • the present invention still further provides a computer system.
  • the computer system comprises a computer having a communica- tion port, a plurality of peripheral devices each having a corresponding communication port, and one or more cascadable interfaces each having an input port and a plurality of output ports.
  • the one or more cascadable interfaces are coupled in a tree-like configuration such that the corresponding communication port of each of the plurality of peripheral devices is coupled to the communication port of the computer by a cascade of at least one of the one or more cascadable interfaces.
  • Each of the interfaces is capable of providing a local data communication path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port.
  • the interfaces is further capable of providing a second ⁇ ary address signal at each of the plurality of output ports capable of driving a like cascadable interface, wherein the secondary address signal is derived from a previous address signal received at the input port.
  • the computer communicates with a selected one of the plural ⁇ ity of peripheral devices upon sending a global address signal containing the address signal for each local data communication path forming the cascade of the at least one of the one or more interfaces coupling the computer to the selected one of the peripheral devices.
  • the present invention yet still further provides a peripheral system having a communication port for interfacing with a communication port of a computer.
  • the system comprises a plurality of peripheral devices, each having a corre ⁇ sponding communication port, and one or more cascadable interfaces, each having an input port and a plurality of output ports.
  • the one or more cascadable interfaces are coupled in a tree-like configuration such that the corresponding communication port of each of the plurali ⁇ ty of peripheral devices is coupled to the communication port of the computer by a cascade of at least one of the one or more cascadable interfaces.
  • Each of the inter- faces is capable of providing a local data communication path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port.
  • Each of the interfaces is further capable of providing a secondary address signal at each of the plurality of output ports capable of driving a like cascadable interface, wherein the second ⁇ ary address signal is derived from a previous address signal received at the input port.
  • FIGURE 1 shows a plurality of peripheral devices interfaced to a computer
  • FIGURE 2 shows a block diagram of a general embodiment of an interface apparatus of the present invention
  • FIGURE 3 shows a block diagram of a more specific embodiment of the interface apparatus of the present invention.
  • FIGURE 4 shows a schematic drawing of a circuit embodiment of the present invention
  • FIGURE 5 shows a timing diagram for the circuit embodiment of the present invention
  • FIGURE 6 shows a timing diagram illustrating a presence detection aspect of the present invention
  • FIGURE 7 shows a flow chart of a method of addressing
  • FIGURE 8 shows a block diagram of the inter ⁇ faces cascaded in a tree-like structure to couple a computer to a plurality of remote devices
  • FIGURE 9 shows a flow chart of a method of global addressing
  • FIGURE 10 shows an interface card for instal ⁇ lation in an expansion port of a personal computer
  • FIGURE 11 shows a block diagram of an alterna ⁇ tive embodiment of the present invention.
  • FIGURE 12 shows a schematic drawing of an alternative embodiment of the present invention.
  • Figure 1 pictorially shows a representative plurality of remote peripheral devices comprising a digital thermometer 20, a digital voltmeter 22, a digital ammeter 24, a digital pressure meter 26, and a digital power meter 28 interfaced via an addressable computer interface 30 to a computer 32.
  • the computer 32 has a monitor 34 as an output interface to a user (not shown), and a keyboard 36 as a user input interface.
  • the addressable computer interface 30 receives an address signal from the computer 32 in order to deter- mine with which of the remote peripheral devices 20, 22, 24, 26, or 28 to establish a bidirectional data communi ⁇ cation path. It is noted that the remote peripheral devices need not have addressing circuitry since all addressing operations are performed within the address ⁇ able computer interface 30.
  • the interface 30 After receiving the address signal, the interface 30 establishes a bidirectional data communication path between the computer 32 and a selected peripheral device.
  • the voltmeter 22 is the device that was selected.
  • the computer 32 can then signal the voltmeter 22 to perform functions such as transmitting its present measurement, changing the scale of measurement, clearing its memories, or initiat ⁇ ing a calibration routine.
  • the extent of the functions which can be performed depend on the capabilities of the device. Supposing that the computer inquires the present voltage measurement from the voltmeter 22, the voltmeter 22 would then transmit a data signal which represents the measurement through the interface 30 for reception by the computer 32. After a step such as processing or storing the measurement, the computer 32 could either signal the voltmeter 22 to perform a further function or could transmit a further address signal in order to access another of the devices.
  • FIG. 1 A block diagram of a general embodiment of an addressable computer interface 40 for providing a data communication path between an input port 42 and a selected one of a plurality of output ports 44 is given in Figure 2.
  • the input port 42 and the plurality of output ports 44 each comprise means for transferring data signals, represented by data signal lines 46 and 48, and each comprise means for transferring address signals, represented by address signal lines 50 and 52.
  • This embodiment of the addressable computer interface 40 comprises a data selector circuit 54 and an address generator 56.
  • the data selector circuit 54 receives an - 15 -
  • the data selector circuit 54 establishes the data communica ⁇ tion path between the input port 42 and the selected one of the plurality of output ports 44.
  • the data communi ⁇ cation path is established by a coupling of the data signals at the input port 42, representatively present at data signal line 46, with the data signals at the selected one of the plurality of output ports 44; representatively present at data signal line 48 for the selected one of the output ports 44.
  • the address generator 56 responds to the address signal received at the input port 42 by provid ⁇ ing a secondary address signal, representatively trans ⁇ mitted along address lines 52, to each of the plurality of output ports 44 capable of driving a like addressable computer interface.
  • the secondary address signal is derived from a previous address signal, representatively received via address line 50, received at the input port 42.
  • the embodiment of Figure 2 is used for provid- ing the data communication path between a computer 58 having a computer port 60 coupled to the input port 42, and a selected one of a plurality of remote peripheral devices 62, wherein each remote peripheral device includes a port 64 for coupling to a corresponding output port.
  • the transmission of the secondary address signal allows the addressable computer interface 40 to be cascadably interfaced to a like addressable computer interface, wherein the input port 42 of the like ad ⁇ dressable computer interface is coupled to one of the plurality of output ports 44 of the interface 30. Further remote devices can then be coupled to the computer 58 by the output ports of the like addressable computer interface.
  • FIG. 3 A block diagram of an embodiment of the addressable computer interface for providing a serial data communication path between an input port 70 and a selected one output port 72 of a plurality of output ports 74 is given in Figure 3.
  • the input port 70 is a serial data port comprising a data receive line 76, a data transmit line 78, a first control line 80, and a second control line 82.
  • Each of the plurality of output ports 74 is a serial data port comprising a data trans ⁇ mit line 84, a data receive line 86, a first control line 88, and a second control line 90.
  • a shift register 92 having a data input 94, a clock input 96, and a plurality of outputs 98, is used for converting address signals received along the first and second control lines 80 and 82 to an address identi ⁇ fying the selected one output port 72.
  • the data input 94 is coupled to the first control line 80 of the input port 70 and the clock input 96 is coupled to the second control line of the input port 70.
  • the shift register 92 shifts the contents of the register by one bit position, thus shifting the values of the plurality of outputs 98 by one output position.
  • the shift register 92 then inserts a bit derived from a signal present at the first control line 80 of the input port 70 into a resulting open register position, which can be observed at a least significant bit output 99.
  • a multiplexer 100 having a plurality of multiplexer inputs 102, a multiplexer output 104, and a plurality of selection inputs 106, is used for providing a data transmission path between the data transmit line 84 of the selected one of the plurality of output ports 74 and the data receive line 76 of the input port 70.
  • Each of the plurality of multiplexer inputs 102 is coupled to a corresponding data transmit line 84 for each of the plurality of output ports 74.
  • the multi ⁇ plexer output 104 is coupled to the data receive line 76 of the input port 70.
  • Each of the plurality of selec ⁇ tion inputs 106 is coupled to a corresponding one of the plurality of outputs 98 of the shift register 92.
  • a demultiplexer 110 having a demultiplexer input 112, a plurality of demultiplexer outputs 114, and a plurality of selection inputs 116, is used for provid ⁇ ing a data transmission path between the data transmit line 78 of the input port 70 and the data receive line 86 of the selected one of the plurality of output ports 74.
  • the demultiplexer input 112 is coupled to the data transmit line 78 of the input port 70.
  • Each of the plurality of demultiplexer outputs 114 is coupled to a corresponding data receive line 86 for each of the plurality of output ports 74.
  • Each of the plurality of selection inputs 116 is coupled to a corresponding one of the plurality of outputs 98 of the shift register 92.
  • the data selector 54 is provided by the demultiplexer 110 and the multiplexer
  • the bidirectional data communication path between the input port 70 and the selected one 72 of the output ports 74 is formed by the unidirectional data transmission path provided by the demultiplexer 110 and the unidirectional data transmission path provided by the multiplexer 100.
  • the first control line 88 of each of the plurality of output ports 74 is coupled to a selected output 120 of the plurality of outputs 98, and the second control line 90 of each of the plurality of output ports 74 is coupled to the second control line 82 of the input port 70.
  • a most significant bit output 122 is chosen as the selected one of the plurali ⁇ ty of outputs coupled to the first control line 88.
  • FIG. 4 A schematic drawing of a circuit embodiment of the present invention is given in Figure 4.
  • This embodiment provides five serial output ports 130, 132, 134, 136, and 138, addressable from a single serial input port 140 in a manner to conform to the RS-232 information interchange specification.
  • the input port comprises a data receive line 142, a data transmit line 144, an address select line 146, an address shift line 148, and a common ground line 150.
  • Each of the five serial output ports 130, 132, 134, 136, and 138 compris- es a data transmit line 152, a data receive line 154, an address select line 156, an address shift line 158, and a common ground line 160.
  • the input port 140 is wired in the DCE configuration for coupling with a mating serial port wired in the DTE configuration.
  • each of the five output ports 130, 132, 134, 136, and 138 is wired in the DTE configuration for coupling with a mating serial port wired in the DCE configuration.
  • the embodiment is hermaphroditic in that the input port of an interface can be mated with one of the five output ports of a second identical interface.
  • the data receive line 142 is coupled to the received-data (RD) pin
  • the data transmit line 144 is coupled to the transmitted-data (TD) pin
  • the address select line 146 is coupled to the data-terminal-ready (DTR) pin
  • the address shift line 148 is coupled to the request-to-send (RTS) pin
  • the common ground line 150 is coupled to the signal ground pin.
  • the use of the words “transmit” and “receive” for describing a data line is referenced in terms of activi- ty of a device coupled to the port containing the line.
  • the data transmit line 144 of the input port is the line on which data is transmitted by the computer; and the data receive line 142 of the input port is the line on which data is received by the computer.
  • the data transmit line 152 of each of the five output ports is the line on which data is transmitted by a corresponding remote peripheral device; and the data receive line 154 of each of the five output ports is the line on which data is received by the corresponding remote peripheral device.
  • the data transmit line 144, the address select line 146, and the address shift line 148 are each applied to a corresponding one of RS-232 line receiver circuits 162, 164, and 166, respectively.
  • the RS-232 line receiver circuits 162, 164, and 166 convert RS-232 logic signals typically based on +12 V and -12 V levels, but generally based on ⁇ 3 V to ⁇ 25 V levels, to TTL logic signals based on 5 V and 0 V levels, and further provide the necessary termination impedance (i.e., input impedance) of between 3 k ⁇ to 7 k ⁇ for RS-232 lines.
  • the line receiver circuits are included to allow conven- tional TTL logic gates to be employed in processing signals received at the input port and the five output ports.
  • the output of line receiver 166 is applied to clock inputs 170, 172, and 174 of corresponding first, second, and third D-type flip-flop integrated circuits 176, 178, and 180, respectively.
  • the first, second, and third flip-flops 176, 178, and 180 are connected in cascade to form a three-bit shift register circuit.
  • the output of line receiver 164 is applied to a data input 182 of the first flip-flop 176, an output 184 of the first flip-flop 176 is connected to an input 186 of the second flip-flop 178, and an output 188 of the second flip-flop 178 is connected to an input 190 of the third flip-flop 180.
  • the resulting shift register shifts the contents of the register by one bit position, i.e., an output 192 of the third flip-flop 180 contains the previous signal at the output 188 of the second flip-flop 178, the output 188 of the second flip-flop 178 contains the previous signal at the output 184 of the first flip-flop 176, and the output 184 of the first flip-flop 176 contains an inverted value of the signal present at the address select line 146.
  • the flip-flop outputs 184, 188, and 192 are each connected to a corresponding one of selection inputs 200, 202, and 204 of a demultiplexer circuit 206.
  • the demultiplexer circuit 206 is of a one-of-eight data selector variety having a data input line 208 and eight output lines 210, 212, 214, 216, 218, 220, 222, and 224.
  • the demultiplexer input line 208 is coupled to the data transmit line 144 by the output of the .line receiver 162.
  • Each output lines 210, 212, 214, 216, and 218 of the eight demultiplexer output lines ⁇ 168 are each coupled to the data receive line 154 of a corresponding one of the five output ports by corresponding RS-232 line driver circuits 230, 232, 234, 236, and 238, respectively.
  • Each RS-232 line driver circuit converts the processed TTL logic signals, based on +5 V and 0 V, back into RS-232 logic signals based on +12 V and -12 V.
  • the demultiplexer circuit 206 provides a data transmission path from the data transmit line 144 of the input port 140 to the data receive line 154 of a selected one of the five output ports based upon a previous three bits clocked into the shift register.
  • the demultiplexer circuit 206 inhibits the transmission of data from the data transmit line 144 to the data receive line 154 of any of the four non-selected output ports. Further, the data transmis ⁇ sion path accepts RS-232 logic level signals at the input port and produces RS-232 logic level data signals at the selected one of the five output ports.
  • the flip-flop outputs 184, 188, and 192 are also each connected to a corresponding one of selection ⁇ 2 2 -
  • the multiplexer circuit 246 is of a 3-to-8 line decoder variety having eight data input lines 250, 252, 254, 256, 258, 260, 262, and 264 and an output line 266.
  • Five input lines 250, 252, 254, 256, and 258 of the eight multiplexer input lines are each coupled to the data transmit line 152 of a corresponding one of the five output ports by corresponding RS-232 line receiver circuits 270, 272, 274, 276, and 278, respectively.
  • Each of the RS-232 line receiver circuits converts RS-232 logic signals into TTL logic signals for process ⁇ ing by the multiplexer 246.
  • the multiplexer output line 266 is coupled to the data receive line 142 by a line driver 280 to produce RS-232 logic signals. Based upon the previous three bits clocked into the shift register, the multiplexer circuit 246 provides a data transmission path from the data transmit line 152 of the selected one of the five output ports to the data receive line 142 of the input port 140. Similar to the operation of the demultiplexer 206, the multiplexer circuit 246 inhibits the transmission of data from the data transmit line 152 of any of the four non-selected output ports to the data receive line 142 of the input port 140.
  • the address shift line 158 for each of the five output ports 130, 132, 134, 136, and 138 is coupled to the output of line receiver 166 by line driver circuits 290, 292, 294, 296, and 298, respectively. This produces, at each of the five output ports, a regenerated version of a clocking signal received at the address shift line 148 of the input port 140.
  • the address select line 156 for each of the five output ports 130, 132, 134, 136, and 138 is coupled to the output 192 of the third flip-flop 180 by line driver circuits 300, 302, 304, 306, and 308.
  • a regenerated version of a previous signal present at the address select line 156 is provided to each of the five output ports 130, 132, 134, 136, and 138.
  • the combination of the signals at address shift line 156 and the address select line 158 provide secondary address signaling for driving the input port of a like computer interface.
  • all of the five output ports are capable of driving a like computer interface. It should be emphasized that, although the address signals received at the input port direct data signals to and from only the selected one of the output ports, the secondary address signaling is provided to each of the output ports including the non-selected output ports.
  • the embodiment of the present invention in Figure 4 further has means for enabling a computer interfaced to its input port to detect its presence using standard data communication means.
  • a first means of detecting presence is produced by one output 224 of the demultiplexer 206 being coupled to one input 264 of the multiplexer 246.
  • the output 224 is selected from the three demultiplexer outputs 220, 222, and 224 that are not coupled to an output port, and the input 264 is similarly selected from one of the three multiplexer outputs 260, 262, and 264 that is not coupled to an output port. Further, the output 224 and input 264 are paired so that they are both enabled for the same selection inputs.
  • a second means of detect ⁇ ing presence is produced by leaving input 262 open.
  • the first and second means for detecting presence are employed as follows.
  • the computer trans ⁇ mits address signals to select the first presence detecting means.
  • the computer then sends data signals along the data transmit line and compares the sent data signals to the data signals at the data receive line. If the sent and received data signals are equivalent, then the computer concludes that either the TD pin of the computer is directly connected to the RD pin of the computer, or that the interface apparatus is connected to the port of the computer.
  • the computer follows by sending out data signals along the data transmit line.
  • the computer concludes that the interface apparatus is connected to the port of the computer, and further concludes that there is no exter ⁇ nal loopback between the TD pin and the RD pin of the computer other than the controlled loopback provided by the first presence detecting means. If the transmitted data signals were present for the second presence detecting means, then the computer would conclude that there is an external loopback between the TD pin and the RD pin.
  • the present invention is not limited to the circuit embodiment having five output ports.
  • the number of output ports can be increased by employing a greater number of cascaded flip-flops to form the shift register, and substituting a demultiplexer and a multi ⁇ plexer having a suitable number of selection lines.
  • TTL logic components in the circuit embodiment of the present invention is not to be construed as a limitation.
  • MOS-based logic components could be employed with substantially equivalent functionality. If an embodi ⁇ ment of the invention is to operate with a wide range of supply voltages, or with low power dissipation, then the MOS-based components would be preferred over TTL-based components.
  • a timing diagram illustrating the operation of the circuit embodiment of the present invention is shown in Figure 5.
  • the signals present on the data receive line (RXD) , data transmit line (TXD) , address select line (SELECT) , and address shift line (SHIFT) are shown for the input port 330 and each of the five output ports 332, 334, 336, 338, 340. Also shown are the signals present at the output of the first (Ql) , second (Q2) , and third (Q3) flip-flops 342.
  • Each signal is drawn to indicate logical values of "0" or "1" vs. time rather than the voltage of each signal vs. time.
  • output port 130 is channel number 1
  • output port 132 is channel number 2
  • output port 134 is channel number 3
  • output port 136 is channel number 4
  • output port 138 is channel number 5.
  • each of the first, second, and third flip-flops is assumed to be initially a binary "0" at time to.
  • a data communication path from the input port to channel 3, corresponding to output port 134, is desired.
  • the channel number "3" is reduced by 1, yielding "2”, and then converted into a three-bit binary number.
  • the three-bit representation for "2" base 10 is "010”.
  • the computer sets the RTS line to be logical "0", followed by setting the DTR line to be equal to the bit value, and finally raising the RTS line to logical "1".
  • this process acts to load the shift register with the three-bit representation of the channel number.
  • the rightmost "0” is loaded at time tl
  • the "1” is loaded at time t2
  • the leftmost "0” is loaded at time t3, resulting in the output (Ql, Q2, Q3) of the three flip-flops being "010".
  • the data communication path is established between the input port and the selected output port 134 at time t3.
  • the data communication path is illustrated by a first data signal 350, transmitted by the computer along the data transmit line of the input port, being present at the data receive line of the selected output port 134.
  • the first data signal 350 would represent a command to the device, such as activate data transmission, clear device memories, or transmit con ⁇ tents of device memories.
  • the instrumenta ⁇ tion device would transmit a second data signal 352 along the data transmit line of the selected output port 134.
  • the second data signal 352 typically would be representative of some measurement obtained by the device.
  • the computer can receive the second data signal 352 along the data receive line of the input port.
  • a third data signal 354 transmitted by the computer is shown to be receivable at the peripheral device at the data receive line of the selected output port 132, and simultaneously, a fourth data signal 356 transmitted by the peripheral device is shown to be receivable at the computer at the data receive line of the input port.
  • the third data signal 354 transmitted by the computer is receiv ⁇ able only by the peripheral device at the selected output port 132 as illustrated by the RXD line for each non-selected output port being inactive after time t6.
  • the preceding establishment of channel 2 further illustrates the generation of the secondary address signal at each of the output ports, wherein the secondary address signal is derived from a previous address signal received at the input port.
  • the SELECT line for each of the output ports is "0" and the SHIFT line for each of the output ports is a transi ⁇ tion from “0" to "1". This corresponds to the previous address signal received at the input port at time tl, namely the signal at the SELECT line being “0” and the signal at the SHIFT line being a transition from “0" to "1".
  • the SELECT line is "1” and the SHIFT line is a transition from "0" to "1” for each of the output ports, which is equivalent to the address signal received at the input port at time t2.
  • the secondary address signal at time t6, SELECT being “0" and SHIFT being a transition from “0” to "1”, is equivalent to the previous address signal received at the input port at time t3.
  • a timing diagram illustrating the operation of the presence detecting means in the circuit embodiment * of the present invention is shown in Figure 6.
  • the first means for detecting presence is assigned to channel number 8
  • the second means for detecting presence is assigned to channel number 7.
  • the computer transmits address signals along the SELECT and SHIFT lines of the input port 330, to enable channel number 8 at time t7.
  • the computer sends a fifth data signal 360 along the data transmit line of the input port.
  • the first presence detecting means directs the fifth data signal 360 back to the input port along the data receive line.
  • the computer enables the second presence detecting means by transmitting address signals along the SELECT and SHIFT lines to enable channel number 7.
  • the computer follows by sending out a sixth data signal 362 along the data transmit line of the input port .
  • the second presence detecting means inhibits the sixth data signal 362 from being directed to the data receive line of the input port. This is evident by the seventh data signal 364 directed back to the input port along the data receive line.
  • FIG. 7 A flow chart detailing a method of addressing the circuit embodiment of the present invention is shown in Figure 7. This method allows addressing based on either a base 10 channel number or a binary address.
  • conditional block 380 the method first determines whether a base 10 channel number or a binary address is given. If a base 10 channel number is given, then the base 10 channel number is reduced by one in block 382.
  • a block diagram in Figure 8 shows an example of a system for providing a communication path between a computer and a selected one of a plurality of periph ⁇ eral devices.
  • the system comprises one or more cascadable interfaces having an input port and a plurality of output ports.
  • Each of the interfaces is capable of providing a local data communication path between the input port and a selected one of the plural ⁇ ity of output ports based upon an address signal re ⁇ ceived at the input port.
  • each of the interfaces is capable of providing a secondary address signal at each of the plurality of output ports, the secondary address signal being based upon a previous address signal received at the input port.
  • the cascad ⁇ able interfaces are generally coupled in a tree-like configuration such that each of the plurality of periph ⁇ eral devices is coupled to the computer by a cascade of at least one of the one or more cascadable interfaces.
  • the example in Figure 8 shows eleven peripher ⁇ al devices 400, 402, 404, 406, 408, 410, 412, 414, 416, 418, and 420, interfaced with a computer 422 using three cascadable interfaces 424, 426, and 428.
  • the input port of the first interface 424 is coupled to the computer 422.
  • the five output ports of the first interface 424 are coupled to peripheral A 400, peripheral B 402, peripheral C 404, the input of the second interface 426, and peripheral D 406, respectively.
  • the five output ports of the second interface 426 are coupled to periph ⁇ eral E 408, the input of the third interface 428, peripheral F 410, peripheral G 412, and peripheral H 414, respectively.
  • peripheral I 416, peripheral J 418, and peripheral K 420 are employed for coupling peripheral I 416, peripheral J 418, and peripheral K 420, respectively, thereto.
  • the resulting configuration is tree-like in that each of the eleven peripheral devices is coupled to the computer by a single corre ⁇ sponding cascade of at least one of the three cascadable interfaces.
  • peripheral D 406 is coupled to the computer by the cascade of the first interface 424
  • peripheral E 408 is coupled to the computer 422 by the cascade of the first interface 424 and the second interface 426
  • peripheral J 418 is coupled to the computer by the cascade of the first, second, and third interfaces 424, 426, and 428.
  • a global address signal which initiates the data communication path between the computer and the selected one of the plural ⁇ ity of peripheral devices is a concatenation of a local address signal for each local communication path in the corresponding cascade.
  • the global address signal for peripheral E 408 is the local address to provide a local communication path from the input port to the channel 4 output port in the first interface, "011", concatenated with the local address which pro ⁇ vides a local communication path from the input port of the second interface 426 to the channel 1 output port, "000"; therefore, the resulting global address is "011000" .
  • FIG. 9 A flow chart illustrating a method of provid ⁇ ing a data communication path between a computer and a selected one of a plurality of peripheral devices is shown in Figure 9.
  • each of the peripheral devices is coupled to the computer by a tree-like configuration of cascadable interfaces.
  • a global address is formed for each of the periph ⁇ eral devices.
  • the global addresses are formed by concatenating the local address for each local communi ⁇ cation path which comprises the global path from the computer to the peripheral device.
  • the global address for each peripheral device is stored in the computer. It is noted that the steps in blocks 450, 452, and 454 can be performed off-line during an initial set-up of the system.
  • the computer selects one of the peripheral devices for communication therewith in block 456.
  • the computer follows by sending an address signal based on the stored global address for the selected device in block 458. After the address signal has been sent, the computer can communicate with the selected peripheral device using transmitted and received data signals in block 460. After communication between the computer and the selected peripheral device has completed, the method returns to block 456 enabling the computer to select another one of the peripheral devices with which to communicate.
  • FIG. 10 shows an interface card embodiment of the present invention.
  • An interface card 500 which contains circuitry for providing an addressable, cascad ⁇ able interface, can be connected to a computer 502 via an expansion slot 504.
  • the interface card 500 has five RS-232 connectors 506 accessible from the back of the computer 502 upon installation of the card 500 in the expansion slot 504.
  • Each of the connectors 506 is coupled to a corresponding one of the five output ports of the interface.
  • the connectors 506 can be of the D9, D25, or DIN variety.
  • any limitation to either the size of the connectors 506 or the number of connectors 506, imposed by the area available at the back of the interface card 500 can be overcome by providing a pigtail-type connection of the connectors 506 to the interface card 500.
  • embodiments of the present invention are not limited to the RS-232 interface standard.
  • the RS-422 interface standard which allows for an increased transmission rate and greater port-to-port cable lengths than with RS-232, could be the basis for an embodiment employing differential transmitter and receiver circuits.
  • embodiments of the present invention are not limited to serial communication ports, but could be applied to parallel communication ports.
  • FIG. 11 A block diagram of an alternative embodiment of an addressable computer interface 528 is shown in Figure 11.
  • the alternative embodiment provides a first data communication path between an input port 530 and each of a plurality of output ports 532, and provides a second data communication path between the input port 530 and a selected one of the plurality of output ports 532.
  • a fixed coupling 534 between a representative first data signal line 536 of the input port 530 and a representative first data signal line 538 of each of the plurality of output ports 532 provides the first data communication path.
  • a data selector circuit 540 re ⁇ ceives an address signal along a representative address signal line 542 of the input port 530 to identify the selected one of the plurality of output ports 532 to which the second data communication path is to be provided.
  • the data selector circuit 540 responds by providing the second data communication path between a representative second data signal line 544 of the input port 530 and a representative second data signal line 546 of the selected one of the output ports.
  • An address generator 548 provides a secondary address signal along a representative secondary address line 550 to each of the plurality of output ports capable of driving a like cascadable computer interface.
  • the secondary address signal is derived from a previous address signal received at the input port 530.
  • a generic represen ⁇ tative line can represent one or more wires for provid- ing signal transfer.
  • the alternative embodiment differs from aforementioned embodiments in that the first data communication path is continually provided between the input port and each of the output ports, in addition to the selectable second data communication path.
  • the transmission of the secondary address signal allows the addressable computer interface 528 to be cascadably interfaced to a like addressable computer interface, wherein the input port 530 of the like addressable computer interface is coupled to one of the output ports 532 of the interface 528.
  • a specific alternative embodiment is illus ⁇ trated by the schematic drawing in Figure 12.
  • the input port 530 and the output ports are parallel communica ⁇ tions ports, each comprising a plurality of data lines 560 and a plurality of control lines 562.
  • the distinc ⁇ tion between data lines and control lines is made with respect to operation of the interface 528, and not with respect to a common application of parallel communica- tions ports, namely, for control of a parallel printer.
  • data lines are used for communication via either the first or the second data communication path and control lines are employed for controlling the addressing of the interface 528.
  • the set of data lines and the set of control lines need not be mutually exclusive.
  • the coupling of the common ground lines of all ports is not shown in the schematic drawing of either Figure 12 or Figure 14.
  • a bus 564 provides a fixed, parallel coupling between eight parallel lines 566 of the input port 530 and eight parallel lines 568 of each of the output ports 532.
  • the eight parallel lines enable eight parallel bits of data to be sent and received at a time via the interface 528.
  • the bus 564 further provides a coupling between a strobe line 570 of the input port 530 and a strobe line 572 of each of the output ports 532.
  • the strobe line is typically employed for signaling when the eight parallel lines of a parallel port are set and valid for reading by the remote device.
  • the address generator 548 is formed by a shift register 574 having a data input 576, a clock input 578, and a plurality of outputs 580.
  • the data input 576 is coupled to a first control line 582 and the clock input is coupled to a second control line 584 of the input * port.
  • the shift register 574 shifts the values of the plurality of outputs 580 by one output position, and inserts a bit derived from a signal present at the first control line 582 into a resulting open output position.
  • a first control line 586 of each of the output ports 532 is coupled to a most significant bit output 588 of the shift register 574, and a second control line of each of the output ports 532 is coupled to the second control line 584 of the input port 530.
  • the shift register 574 is implemented by a cascaded connection of three flip-flops 592, 594, and 596.
  • the data selector 540 is provided by a first demultiplexer 600, a second demultiplexer 602, a first multiplexer 604, and a second multiplexer 606.
  • Each of the first demultiplexer 600, the second demultiplexer 602, the first multiplexer 604, and the second multiplexer 606 includes a plurality of selection inputs 610, 612, 614, and 616, respectively, for coupling with the outputs 580 of the shift register 574.
  • the first demultiplexer 600 further contains a demultiplexer input 618 coupled to a first selectable line 620 of the input port 530, and a plurality of demultiplexer outputs 622 coupled to a corresponding first selectable line 624 for each of the output ports 532.
  • the second demultiplexer 602 further contains a demultiplexer input 628 coupled to a second selectable line 630 of the input port 530, and a plurality of demultiplexer outputs 632 coupled to a corresponding second selectable line 634 for each of the output ports 532. Based upon the address signal received at the first and second control lines 582 and 584, the first and second demultiplexers 600 and 602 each provide a data transmission path from the input port 530 to the selected one of the output ports 532.
  • the first multiplexer 604 includes a multi- plexer output 638 coupled to a third selectable line 640 of the input port 530, and a plurality of multiplexer inputs 642 coupled to a corresponding third selectable line 644 for each of the output ports 532.
  • the second multiplexer 606 further contains a multiplexer output 648 coupled to a fourth selectable line 650 . of the input port 530 and a plurality of multiplexer inputs 652 coupled to a corresponding fourth selectable line 654 for each of the output ports 532.
  • the first and second multiplexers 604 and 606 each provide a data transmission path from the selected one of the output ports 532 to the input port 530.
  • the interface 528 of Figure 12 further includes presence detecting means as the embodiment of Figure 4.
  • a first means of detecting presence is produced by coupling a loopback input 656 of the first multiplexer 604 with a loopback output 658 of the first demultiplexer 600, wherein the loopback input 656 and loopback output 658 are enabled for the same selection inputs.
  • a second means of detecting presence is pro- pokerd by leaving input 660 of the first multiplexer 604 open.
  • the same method of presence detection used in the embodiment of Figure 4 is employed using the first selectable line 620 and the third selectable line 640 of the input port 530.
  • a different number of parallel lines can be included in the bus 564 for parallel ports which send and receive bytes comprising other than eight bits.
  • at least one of the parallel lines can ' be applied to the data selector circuit 540 rather than the bus 564 for the purpose of making the parallel lines selectable.
  • the strobe line can be applied to the data selector circuit 540 rather than the bus 564 to allow a selected remote device to signal the computer when the data lines are set and valid for reading in a bi-direc ⁇ tional parallel port.
  • the number of demulti ⁇ plexers and the number of multiplexers employed in the data selector circuit 540 are not limited to two; the data selector circuit 540 is said to generally contain at least one demultiplexer or at least one multiplexer.
  • remote peripheral devices need not have inherent addressing circuitry for use with embodiments of the invention.
  • the remote peripheral devices are addressed by the use of secondary address signals which produce global shift registers formed by individual local shift registers in each interface unit .
  • a further advantage of an embodiment of the present invention is that it is inexpensive to manufac- ture.
  • a demultiplexer By employing a demultiplexer, a multiplexer, and either a shift register or discrete flip-flops, embodi ⁇ ments of the cascadable interface can be economically constructed using conventional integrated circuits .

Abstract

A computer interface (30) comprising a demultiplexer (110), multiplexer (100), and shift registers (92) for providing a data communication path between an input port (42) and a selected one of a plurality of output ports (44). The data communication path is provided in response to an address signal (50) received at the input port (42). A secondary address signal (52), derived from a previous address signal, is provided to each of the plurality of output ports (44). The resulting interface is hermaphroditic in that a first interface can address a second interface coupled thereto. A tree-like cascading of one or more like interfaces (424, 426, 428) produces a system for interfacing a computer with a plurality of remote peripheral devices (400-420). Embodiments of the present invention for both serial input and output ports and parallel input and output ports are presented.

Description

ADDRESSABLE COMMUNICATION PORT EXPANDER
Technical Field
This invention generally relates to computer data communications, and more particularly, to comrnu- nication between a computer and a plurality of periph¬ eral devices .
Background Art
Transmission of digital data using serial communications is a long established practice in the art of data communication. With the advent of the digital computer, and specifically personal computers, the use of serial communications has become commonplace. Personal computers use serial communication to drive peripheral devices, such as printers, plotters, modems, and page scanners, via serial output ports located on each computer. The RS-232 standard, defined by specifi¬ cation EIA-232-D, is the predominant standard by which serial communication is performed using a personal computer. Hence, many personal computers contain at least one RS-232 serial port, wired in a data terminal equipment (DTE) configuration, for communication with peripheral devices containing an RS-232 serial port wired in a data circuit-terminating equipment (DCE) configuration. A difference between the DTE and DCE configurations is a result of reversing a data receive line (also known as an RD line or an RXD line) with a data transmit line (also known as a TD line or a TXD line) . - 2 -
In many industrial applications, the monitor¬ ing and recording of measurements made from electronic instrumentation devices are of interest. Such electron¬ ic instrumentation devices include digital voltmeters, ammeters, power meters, pressure meters, flow meters, and thermometers . To facilitate the use of computers to automatically monitor, record, and process measurements, many electronic.instrumentation devices have incorporat¬ ed RS-232 serial ports therein to enable data to be transferred to a computer.
Although the RS-232 protocol has been favor¬ ably employed for interfacing conventional peripheral devices to computers, its scope of application is limited by its inherent design for communication between a single sending device and a single receiving device, namely, a single computer and a single peripheral device. Therefore, an unaccompanied use of a single RS-232 port presents an obstacle in applications where a large number of peripheral devices are to be inter- faced to the computer, such as a power plant or any general process control application wherein many instru¬ mentation devices are to be monitored.
One method of interfacing a plurality of peripheral devices to a single RS-232 port on a computer is by wiring, in parallel, the RS-232 ports on the peripheral devices to the RS-232 port on the computer. Although parallel wiring does allow the same serial data to be sent to the plurality of peripheral devices, difficulties arise when the peripheral devices attempt to transmit data to the computer. Moreover, damage to either a peripheral device or the computer can result when two peripheral devices simultaneously attempt to impress different voltages on the same parallel-wired line.
An improved approach to handling data from multiple RS-232 devices is to employ one RS-232 computer port for each device. Many personal computers have software provision for four serial ports (C0M1, COM2, COM3, and COM4), although only two of these ports have operating-system-specified software interrupts. Hence, when using an unmodified, off-the-shelf personal comput- er, this approach is currently limited to applications having no greater than four peripheral devices.
Another approach is to install a multi-port expansion board in an internal computer slot. In currently-available multi-port expansion boards, the number of serial ports can be extended up to eight. However, the multi-port board approach suffers in that the number of peripheral devices is limited to the number of output ports on the board. This limitation is significant in applications such as power plant monitor- ing, where the number of devices that need to be ac¬ cessed can be more than a dozen, with 16 or 32 peripher¬ al devices being common.
A more flexible method for communication between a single computer port and many remote peripher- al devices is based on a serial communication standard defined by EIA specification RS-485. The RS-485 stan¬ dard utilizes tri-state outputs on the sending units of each remote device, in other words, each device output is either high, low, or off. When the computer needs to exchange data with a specific device, the computer first sends an address for a selected peripheral device of interest on a transmit line of the computer. To be RS-485 compatible, each peripheral device must have inherent addressing circuitry so that it can recognize its own address code. Typically, the individual address code for each peripheral device is set by the positions of a number of DIP switches on the device. After the selected peripheral device has recognized that its address code was sent on the transmit line of the computer, the device activates its output and seizes a receive line of the computer. When the receive line of the computer is seized, other devices on the system must release the receive line of the computer by putting their respective device output in the off state to avoid incapacitating any messages sent from the addressed device. All devices that are not sending data to the computer must be in the off state so that there is no contention for the computer's receive line. A shortcom¬ ing of the RS-485 protocol is that if identical address codes are assigned to more than one remote device, the possibility exists of a system malfunction caused by two devices forcing two different voltage levels on the receive line of the computer. Moreover, many peripheral devices are not equipped to communicate using the RS-485 standard.
A method of providing parallel communications between a computer and a plurality of peripheral devices employs the IEEE-488 interface bus. IEEE-488 has been applied to a wide variety of conventional peripherals, such as disk drives, printers, and plotters, along with programmable instrumentation devices such as data recorders, oscilloscopes, and digital voltmeters." Hewlett-Packard has combined the IEEE-488 standard with a communication system that allows devices on the IEEE-488 bus to communicate with one another, the combination being known as HPIB. However, the HPIB interface is currently limited to no more than 15 devices being connected in parallel on an HPIB bus.
Another method of providing parallel communi¬ cations between a computer and a plurality of peripheral devices employs a Small Computer Systems Interface (SCSI) . SCSI was developed by the American National Standards Institute (ANSI) in response to a need for a sophisticated, high-speed parallel interface capable of serving multiple intelligent peripheral devices. A SCSI bus is designed to support up to eight devices (includ¬ ing the computer) with up to 2,048 addressable units per device. Data may be transferred using SCSI not only to and from the host computer, but between peripheral devices as well. A shortcoming of SCSI is in its general unavailability as an option for instrumentation devices. Further, the cost of providing the intelli¬ gence mandated by the SCSI protocol can be prohibitive for some applications.
Summary of the Invention
For the foregoing reasons, there is a need for a computer interface that is capable of providing an unlimited number of addressable multiplexed output ports to interface with remote peripheral devices, wherein the remote peripheral devices need not have inherent ad¬ dressing circuitry, and wherein the computer interface can be inexpensively manufactured. It is thus an object of the present invention to increase the number of addressable multiplexed output ports in a computer interfacing system.
Another object of the present invention is to provide the multiplexed output ports to remote peripher¬ al devices not having inherent addressing circuitry.
A further object is to provide a computer interfacing system which can be constructed using conventional integrated circuit components.
A still further object is to include presence detectability in a computer interface, wherein the presence can be detected by a computer using routine transmitted and received data signals.
In carrying out the above objects, the present invention provides a cascadable computer interface apparatus for providing a data communication path between an input port and a selected one of a plurality of output ports. The apparatus comprises a data selec¬ tor circuit which provides the data communication path between the input port and the selected one of the plurality of output ports based upon a received signal indicating the selected one of the plurality of output ports. The apparatus further comprises a secondary signal generator responsive to the received signal, which provides a secondary signal to each of the plural¬ ity of output ports capable of driving a like cascadable computer interface apparatus, wherein the secondary signal is derived from a previous received signal. In carrying out the above objects, the present invention further provides a computer interface appara¬ tus for providing a data communication path between an input port and a selected one of a plurality of output ports, wherein the input port and each of the plurality of output ports is a RS-232 port having a data transmit line, a data receive line, a first control line, and a second control line. The apparatus comprises a shift register having a data input, a clock input, and a plurality of outputs. The data input is responsive to a first control signal received from the -first control line of the input port, and the clock input is respon¬ sive to a second control signal received from the second control line, so that the plurality of outputs identi- fies the selected one of the plurality of output ports. The apparatus further comprises a multiplexer which responds to the plurality of outputs of the shift register to provide a first data transmission path between the data transmit line of the selected one of the plurality of output ports and the data receive line of the input port. The apparatus further comprises a demultiplexer with responds to the plurality of outputs of the shift register to provide a second data transmis¬ sion path between the data transmit line of the input port and the data receive line of the selected one of the plurality of output ports. The first control line of each of the plurality of output ports is coupled to a selected one of plurality of output ports, and the second control line of each of the plurality of output ports is coupled to the second control line of the input port.
In carrying out the above objects, the present invention still further provides a system for providing a data communication path between a computer and a selected one of a plurality of peripheral devices. One or more cascadable interfaces, wherein each of the interfaces has an input port and a plurality of output ports, are coupled in a tree-like configuration such that each of the plurality of peripheral devices is coupled to the computer by a cascade of at least one of the one or more cascadable interfaces. Each of the interfaces is capable of providing a local data communi- cation path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port. Each of the inter¬ faces is further capable of providing a secondary address signal at each of the plurality of output ports capable of driving a like cascadable interface, wherein the secondary address signal is derived from a previous address signal received at the input port. The data communication path is provided in response to a global address signal generated by the computer, wherein the global address signal contains the address signal for each local data communication path forming the cascade of the at least one of the one or more interfaces coupling the selected one of the peripheral devices to the computer.
In carrying out the above objects, the present invention yet further provides a cascadable computer interface apparatus for providing a first data communi¬ cation path between an input port and each of a plurali¬ ty of output ports, and for providing a second data communication path between the input port and a selected one of the plurality of output ports. The first data communication path is provided by coupling means between the input port and each of the plurality of output - 9 -
ports. A data selector circuit provides the second data communication path between the input port and the selected one of the plurality of output ports based upon a received signal indicating the selected one of the plurality of output ports. A secondary signal generator provides a secondary signal, derived from a previous received signal, to each of the plurality of output ports capable of driving a like cascadable computer interface apparatus.
In carrying out the above objects, the present invention yet still further provides a computer inter¬ face apparatus for providing a first data communication path between an input port and each of a plurality of output ports, and for providing a second data communica- tion path between the input port and a selected one of the plurality of output ports, wherein the input port and each of the plurality of output ports is a parallel communications port having at least one selectable data line, at least one fixed data line, a first control line, and a second control line. A bus provides the first data communication path by coupling in parallel the at least one fixed data line of the input port to the at least one fixed data line of each of the plurali¬ ty of output ports. A plurality of outputs of a shift register having a data input responsive to a first control signal received from the first control line of the input port, and a clock input responsive to a second control signal received from the second control line, identifies the selected one of the plurality of output ports. At least one multiplexer provides at least one data transmission path from the at least one selectable data line of the selected one of the plurality of output ports to the at least one selectable data line of the 10 -
input port, in response to the plurality of outputs of the shift register. The first control line of each of the plurality of output ports is coupled to a selected one of the plurality of outputs of the shift register, and the second control line of each of the plurality of output ports is coupled to the second control line of the input port.
In carrying out the above objects, the present invention further provides a computer interface appara- tus. The apparatus comprises a serial input port, a plurality of serial output ports, and a data selector which provides a data communication path between the serial input port and a selected one of the plurality of serial output ports in response to a received signal indicating the selected one of the plurality of serial output ports.
In carrying out the above objects, the present invention still further provides a computer system. The computer system comprises a computer having a communica- tion port, a plurality of peripheral devices each having a corresponding communication port, and one or more cascadable interfaces each having an input port and a plurality of output ports. The one or more cascadable interfaces are coupled in a tree-like configuration such that the corresponding communication port of each of the plurality of peripheral devices is coupled to the communication port of the computer by a cascade of at least one of the one or more cascadable interfaces. Each of the interfaces is capable of providing a local data communication path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port. Each of l i ¬
the interfaces is further capable of providing a second¬ ary address signal at each of the plurality of output ports capable of driving a like cascadable interface, wherein the secondary address signal is derived from a previous address signal received at the input port. The computer communicates with a selected one of the plural¬ ity of peripheral devices upon sending a global address signal containing the address signal for each local data communication path forming the cascade of the at least one of the one or more interfaces coupling the computer to the selected one of the peripheral devices.
In carrying out the above objects, the present invention yet still further provides a peripheral system having a communication port for interfacing with a communication port of a computer. The system comprises a plurality of peripheral devices, each having a corre¬ sponding communication port, and one or more cascadable interfaces, each having an input port and a plurality of output ports. The one or more cascadable interfaces are coupled in a tree-like configuration such that the corresponding communication port of each of the plurali¬ ty of peripheral devices is coupled to the communication port of the computer by a cascade of at least one of the one or more cascadable interfaces. Each of the inter- faces is capable of providing a local data communication path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port. Each of the interfaces is further capable of providing a secondary address signal at each of the plurality of output ports capable of driving a like cascadable interface, wherein the second¬ ary address signal is derived from a previous address signal received at the input port. The computer commu- 12 -
nicates with a selected one of the plurality of peri¬ pheral devices upon sending a global address signal containing the address signal for each local data communication path forming the cascade of at least one of the one or more interfaces coupling the computer to the selected one of the peripheral devices.
These and other features, aspects, and advan¬ tages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings.
Brief Description of the Drawings
FIGURE 1 shows a plurality of peripheral devices interfaced to a computer;
FIGURE 2 shows a block diagram of a general embodiment of an interface apparatus of the present invention;
FIGURE 3 shows a block diagram of a more specific embodiment of the interface apparatus of the present invention;
FIGURE 4 shows a schematic drawing of a circuit embodiment of the present invention;
FIGURE 5 shows a timing diagram for the circuit embodiment of the present invention;
FIGURE 6 shows a timing diagram illustrating a presence detection aspect of the present invention; FIGURE 7 shows a flow chart of a method of addressing;
FIGURE 8 shows a block diagram of the inter¬ faces cascaded in a tree-like structure to couple a computer to a plurality of remote devices;
FIGURE 9 shows a flow chart of a method of global addressing;
FIGURE 10 shows an interface card for instal¬ lation in an expansion port of a personal computer;
FIGURE 11 shows a block diagram of an alterna¬ tive embodiment of the present invention; and
FIGURE 12 shows a schematic drawing of an alternative embodiment of the present invention.
Detailed Description of the Invention
Figure 1 pictorially shows a representative plurality of remote peripheral devices comprising a digital thermometer 20, a digital voltmeter 22, a digital ammeter 24, a digital pressure meter 26, and a digital power meter 28 interfaced via an addressable computer interface 30 to a computer 32. The computer 32 has a monitor 34 as an output interface to a user (not shown), and a keyboard 36 as a user input interface. The addressable computer interface 30 receives an address signal from the computer 32 in order to deter- mine with which of the remote peripheral devices 20, 22, 24, 26, or 28 to establish a bidirectional data communi¬ cation path. It is noted that the remote peripheral devices need not have addressing circuitry since all addressing operations are performed within the address¬ able computer interface 30. After receiving the address signal, the interface 30 establishes a bidirectional data communication path between the computer 32 and a selected peripheral device. Suppose that the voltmeter 22 is the device that was selected. The computer 32 can then signal the voltmeter 22 to perform functions such as transmitting its present measurement, changing the scale of measurement, clearing its memories, or initiat¬ ing a calibration routine. The extent of the functions which can be performed depend on the capabilities of the device. Supposing that the computer inquires the present voltage measurement from the voltmeter 22, the voltmeter 22 would then transmit a data signal which represents the measurement through the interface 30 for reception by the computer 32. After a step such as processing or storing the measurement, the computer 32 could either signal the voltmeter 22 to perform a further function or could transmit a further address signal in order to access another of the devices.
A block diagram of a general embodiment of an addressable computer interface 40 for providing a data communication path between an input port 42 and a selected one of a plurality of output ports 44 is given in Figure 2. The input port 42 and the plurality of output ports 44 each comprise means for transferring data signals, represented by data signal lines 46 and 48, and each comprise means for transferring address signals, represented by address signal lines 50 and 52. This embodiment of the addressable computer interface 40 comprises a data selector circuit 54 and an address generator 56. The data selector circuit 54 receives an - 15 -
address signal, representatively received along the address signal line 50, which identifies the selected one of the plurality of output ports 44 to which the data communication path is to be provided. In response to the address signal received at the input port 42, the data selector circuit 54 establishes the data communica¬ tion path between the input port 42 and the selected one of the plurality of output ports 44. The data communi¬ cation path is established by a coupling of the data signals at the input port 42, representatively present at data signal line 46, with the data signals at the selected one of the plurality of output ports 44; representatively present at data signal line 48 for the selected one of the output ports 44.
The address generator 56 responds to the address signal received at the input port 42 by provid¬ ing a secondary address signal, representatively trans¬ mitted along address lines 52, to each of the plurality of output ports 44 capable of driving a like addressable computer interface. The secondary address signal is derived from a previous address signal, representatively received via address line 50, received at the input port 42.
The embodiment of Figure 2 is used for provid- ing the data communication path between a computer 58 having a computer port 60 coupled to the input port 42, and a selected one of a plurality of remote peripheral devices 62, wherein each remote peripheral device includes a port 64 for coupling to a corresponding output port. The transmission of the secondary address signal allows the addressable computer interface 40 to be cascadably interfaced to a like addressable computer interface, wherein the input port 42 of the like ad¬ dressable computer interface is coupled to one of the plurality of output ports 44 of the interface 30. Further remote devices can then be coupled to the computer 58 by the output ports of the like addressable computer interface.
A block diagram of an embodiment of the addressable computer interface for providing a serial data communication path between an input port 70 and a selected one output port 72 of a plurality of output ports 74 is given in Figure 3. The input port 70 is a serial data port comprising a data receive line 76, a data transmit line 78, a first control line 80, and a second control line 82. Each of the plurality of output ports 74 is a serial data port comprising a data trans¬ mit line 84, a data receive line 86, a first control line 88, and a second control line 90.
A shift register 92, having a data input 94, a clock input 96, and a plurality of outputs 98, is used for converting address signals received along the first and second control lines 80 and 82 to an address identi¬ fying the selected one output port 72. The data input 94 is coupled to the first control line 80 of the input port 70 and the clock input 96 is coupled to the second control line of the input port 70. In response to a clock pulse received at the input port 70 along the second control line 82, the shift register 92 shifts the contents of the register by one bit position, thus shifting the values of the plurality of outputs 98 by one output position. The shift register 92 then inserts a bit derived from a signal present at the first control line 80 of the input port 70 into a resulting open register position, which can be observed at a least significant bit output 99.
A multiplexer 100, having a plurality of multiplexer inputs 102, a multiplexer output 104, and a plurality of selection inputs 106, is used for providing a data transmission path between the data transmit line 84 of the selected one of the plurality of output ports 74 and the data receive line 76 of the input port 70. Each of the plurality of multiplexer inputs 102 is coupled to a corresponding data transmit line 84 for each of the plurality of output ports 74. The multi¬ plexer output 104 is coupled to the data receive line 76 of the input port 70. Each of the plurality of selec¬ tion inputs 106 is coupled to a corresponding one of the plurality of outputs 98 of the shift register 92.
A demultiplexer 110, having a demultiplexer input 112, a plurality of demultiplexer outputs 114, and a plurality of selection inputs 116, is used for provid¬ ing a data transmission path between the data transmit line 78 of the input port 70 and the data receive line 86 of the selected one of the plurality of output ports 74. The demultiplexer input 112 is coupled to the data transmit line 78 of the input port 70. Each of the plurality of demultiplexer outputs 114 is coupled to a corresponding data receive line 86 for each of the plurality of output ports 74. Each of the plurality of selection inputs 116 is coupled to a corresponding one of the plurality of outputs 98 of the shift register 92.
In this embodiment, the data selector 54 is provided by the demultiplexer 110 and the multiplexer
100, wherein the bidirectional data communication path between the input port 70 and the selected one 72 of the output ports 74 is formed by the unidirectional data transmission path provided by the demultiplexer 110 and the unidirectional data transmission path provided by the multiplexer 100.
To provide secondary address signals, the first control line 88 of each of the plurality of output ports 74 is coupled to a selected output 120 of the plurality of outputs 98, and the second control line 90 of each of the plurality of output ports 74 is coupled to the second control line 82 of the input port 70. In order, both, to employ all of the plurality of outputs 18 for addressing and to provide for independent ad¬ dressing of a like interface cascadably connected to the cascadable computer interface, a most significant bit output 122 is chosen as the selected one of the plurali¬ ty of outputs coupled to the first control line 88. Hence, this configuration is preferred, although alter¬ native embodiments are generally not limited thereto.
A schematic drawing of a circuit embodiment of the present invention is given in Figure 4. This embodiment provides five serial output ports 130, 132, 134, 136, and 138, addressable from a single serial input port 140 in a manner to conform to the RS-232 information interchange specification. The input port comprises a data receive line 142, a data transmit line 144, an address select line 146, an address shift line 148, and a common ground line 150. Each of the five serial output ports 130, 132, 134, 136, and 138 compris- es a data transmit line 152, a data receive line 154, an address select line 156, an address shift line 158, and a common ground line 160. The input port 140 is wired in the DCE configuration for coupling with a mating serial port wired in the DTE configuration. Similarly, each of the five output ports 130, 132, 134, 136, and 138 is wired in the DTE configuration for coupling with a mating serial port wired in the DCE configuration. As a result, the embodiment is hermaphroditic in that the input port of an interface can be mated with one of the five output ports of a second identical interface. In terms of the RS-232 specification, the data receive line 142 is coupled to the received-data (RD) pin, the data transmit line 144 is coupled to the transmitted-data (TD) pin, the address select line 146 is coupled to the data-terminal-ready (DTR) pin, the address shift line 148 is coupled to the request-to-send (RTS) pin, and the common ground line 150 is coupled to the signal ground pin.
For the purpose of clarity, it is noted that the use of the words "transmit" and "receive" for describing a data line is referenced in terms of activi- ty of a device coupled to the port containing the line. Specifically, the data transmit line 144 of the input port is the line on which data is transmitted by the computer; and the data receive line 142 of the input port is the line on which data is received by the computer. Similarly, the data transmit line 152 of each of the five output ports is the line on which data is transmitted by a corresponding remote peripheral device; and the data receive line 154 of each of the five output ports is the line on which data is received by the corresponding remote peripheral device.
The data transmit line 144, the address select line 146, and the address shift line 148 are each applied to a corresponding one of RS-232 line receiver circuits 162, 164, and 166, respectively. The RS-232 line receiver circuits 162, 164, and 166, convert RS-232 logic signals typically based on +12 V and -12 V levels, but generally based on ± 3 V to ± 25 V levels, to TTL logic signals based on 5 V and 0 V levels, and further provide the necessary termination impedance (i.e., input impedance) of between 3 kΩ to 7 kΩ for RS-232 lines. The line receiver circuits are included to allow conven- tional TTL logic gates to be employed in processing signals received at the input port and the five output ports.
The output of line receiver 166 is applied to clock inputs 170, 172, and 174 of corresponding first, second, and third D-type flip-flop integrated circuits 176, 178, and 180, respectively. The first, second, and third flip-flops 176, 178, and 180 are connected in cascade to form a three-bit shift register circuit. Specifically, the output of line receiver 164 is applied to a data input 182 of the first flip-flop 176, an output 184 of the first flip-flop 176 is connected to an input 186 of the second flip-flop 178, and an output 188 of the second flip-flop 178 is connected to an input 190 of the third flip-flop 180. In response to a clock pulse received at the address shift line 148 of the input port, the resulting shift register shifts the contents of the register by one bit position, i.e., an output 192 of the third flip-flop 180 contains the previous signal at the output 188 of the second flip-flop 178, the output 188 of the second flip-flop 178 contains the previous signal at the output 184 of the first flip-flop 176, and the output 184 of the first flip-flop 176 contains an inverted value of the signal present at the address select line 146.
The flip-flop outputs 184, 188, and 192 are each connected to a corresponding one of selection inputs 200, 202, and 204 of a demultiplexer circuit 206. The demultiplexer circuit 206 is of a one-of-eight data selector variety having a data input line 208 and eight output lines 210, 212, 214, 216, 218, 220, 222, and 224. The demultiplexer input line 208 is coupled to the data transmit line 144 by the output of the .line receiver 162. Five output lines 210, 212, 214, 216, and 218 of the eight demultiplexer output lines ■ 168 are each coupled to the data receive line 154 of a corresponding one of the five output ports by corresponding RS-232 line driver circuits 230, 232, 234, 236, and 238, respectively. Each RS-232 line driver circuit converts the processed TTL logic signals, based on +5 V and 0 V, back into RS-232 logic signals based on +12 V and -12 V. As a result, the demultiplexer circuit 206 provides a data transmission path from the data transmit line 144 of the input port 140 to the data receive line 154 of a selected one of the five output ports based upon a previous three bits clocked into the shift register. Moreover, the demultiplexer circuit 206 inhibits the transmission of data from the data transmit line 144 to the data receive line 154 of any of the four non-selected output ports. Further, the data transmis¬ sion path accepts RS-232 logic level signals at the input port and produces RS-232 logic level data signals at the selected one of the five output ports.
The flip-flop outputs 184, 188, and 192 are also each connected to a corresponding one of selection 2 2 -
inputs 240, 242, and 244 of a multiplexer circuit 246. The multiplexer circuit 246 is of a 3-to-8 line decoder variety having eight data input lines 250, 252, 254, 256, 258, 260, 262, and 264 and an output line 266. Five input lines 250, 252, 254, 256, and 258 of the eight multiplexer input lines are each coupled to the data transmit line 152 of a corresponding one of the five output ports by corresponding RS-232 line receiver circuits 270, 272, 274, 276, and 278, respectively. Each of the RS-232 line receiver circuits converts RS-232 logic signals into TTL logic signals for process¬ ing by the multiplexer 246. The multiplexer output line 266 is coupled to the data receive line 142 by a line driver 280 to produce RS-232 logic signals. Based upon the previous three bits clocked into the shift register, the multiplexer circuit 246 provides a data transmission path from the data transmit line 152 of the selected one of the five output ports to the data receive line 142 of the input port 140. Similar to the operation of the demultiplexer 206, the multiplexer circuit 246 inhibits the transmission of data from the data transmit line 152 of any of the four non-selected output ports to the data receive line 142 of the input port 140.
The address shift line 158 for each of the five output ports 130, 132, 134, 136, and 138 is coupled to the output of line receiver 166 by line driver circuits 290, 292, 294, 296, and 298, respectively. This produces, at each of the five output ports, a regenerated version of a clocking signal received at the address shift line 148 of the input port 140. The address select line 156 for each of the five output ports 130, 132, 134, 136, and 138 is coupled to the output 192 of the third flip-flop 180 by line driver circuits 300, 302, 304, 306, and 308. As a result, a regenerated version of a previous signal present at the address select line 156, specifically the signal present three clock pulses in the past, is provided to each of the five output ports 130, 132, 134, 136, and 138. The combination of the signals at address shift line 156 and the address select line 158 provide secondary address signaling for driving the input port of a like computer interface. Thus, in the embodiment of Figure 4, all of the five output ports are capable of driving a like computer interface. It should be emphasized that, although the address signals received at the input port direct data signals to and from only the selected one of the output ports, the secondary address signaling is provided to each of the output ports including the non-selected output ports.
The embodiment of the present invention in Figure 4 further has means for enabling a computer interfaced to its input port to detect its presence using standard data communication means. A first means of detecting presence is produced by one output 224 of the demultiplexer 206 being coupled to one input 264 of the multiplexer 246. The output 224 is selected from the three demultiplexer outputs 220, 222, and 224 that are not coupled to an output port, and the input 264 is similarly selected from one of the three multiplexer outputs 260, 262, and 264 that is not coupled to an output port. Further, the output 224 and input 264 are paired so that they are both enabled for the same selection inputs. Similarly, a second means of detect¬ ing presence is produced by leaving input 262 open. The first and second means for detecting presence are employed as follows. The computer trans¬ mits address signals to select the first presence detecting means. The computer then sends data signals along the data transmit line and compares the sent data signals to the data signals at the data receive line. If the sent and received data signals are equivalent, then the computer concludes that either the TD pin of the computer is directly connected to the RD pin of the computer, or that the interface apparatus is connected to the port of the computer. Next, the computer trans¬ mits address signals to select the second presence detecting means. The computer follows by sending out data signals along the data transmit line. If the transmitted data signals are not present at the data receive line, then the computer concludes that the interface apparatus is connected to the port of the computer, and further concludes that there is no exter¬ nal loopback between the TD pin and the RD pin of the computer other than the controlled loopback provided by the first presence detecting means. If the transmitted data signals were present for the second presence detecting means, then the computer would conclude that there is an external loopback between the TD pin and the RD pin.
One with ordinary skill in the art will recognize that the present invention is not limited to the circuit embodiment having five output ports. The number of output ports can be increased by employing a greater number of cascaded flip-flops to form the shift register, and substituting a demultiplexer and a multi¬ plexer having a suitable number of selection lines. Moreover, it is obvious that a discrete shift register - 25 -
integrated circuit can be substituted for the cascaded flip-flops .
Further, it would be obvious to one with ordinary skill in the art that the use of TTL logic components in the circuit embodiment of the present invention is not to be construed as a limitation. MOS-based logic components could be employed with substantially equivalent functionality. If an embodi¬ ment of the invention is to operate with a wide range of supply voltages, or with low power dissipation, then the MOS-based components would be preferred over TTL-based components.
A timing diagram illustrating the operation of the circuit embodiment of the present invention is shown in Figure 5. The signals present on the data receive line (RXD) , data transmit line (TXD) , address select line (SELECT) , and address shift line (SHIFT) are shown for the input port 330 and each of the five output ports 332, 334, 336, 338, 340. Also shown are the signals present at the output of the first (Ql) , second (Q2) , and third (Q3) flip-flops 342. Each signal is drawn to indicate logical values of "0" or "1" vs. time rather than the voltage of each signal vs. time. This conven¬ tion is selected since a negative logic is employed in the RS-232 specification, while a positive logic is used in the demultiplexer, multiplexer, and flip-flops. The voltage polarity of the RS-232 signals can be determined based on Figure 5 by simply inverting the RXD, TXD, SELECT, and SHIFT signals. For ease in designating each of the output ports, a unique channel number from 1 to
5 is assigned to each output port. Specifically, output port 130 is channel number 1, output port 132 is channel number 2, output port 134 is channel number 3, output port 136 is channel number 4, and output port 138 is channel number 5.
For illustration, the output of each of the first, second, and third flip-flops is assumed to be initially a binary "0" at time to. Suppose that a data communication path from the input port to channel 3, corresponding to output port 134, is desired. Within the computer, the channel number "3" is reduced by 1, yielding "2", and then converted into a three-bit binary number. The three-bit representation for "2" base 10 is "010". Next, for each of the bits in reverse order (i.e., from right to left), the computer sets the RTS line to be logical "0", followed by setting the DTR line to be equal to the bit value, and finally raising the RTS line to logical "1". Since the DTR line is coupled to the SELECT line of the interface, and the RTS line is coupled to the SHIFT line of the interface, this process acts to load the shift register with the three-bit representation of the channel number. Referring back to Figure 5, the rightmost "0" is loaded at time tl, the "1" is loaded at time t2, and the leftmost "0" is loaded at time t3, resulting in the output (Ql, Q2, Q3) of the three flip-flops being "010". As a result, the data communication path is established between the input port and the selected output port 134 at time t3.
The data communication path is illustrated by a first data signal 350, transmitted by the computer along the data transmit line of the input port, being present at the data receive line of the selected output port 134. If an instrumentation device is coupled to the output port 134, the first data signal 350 would represent a command to the device, such as activate data transmission, clear device memories, or transmit con¬ tents of device memories. In response, the instrumenta¬ tion device would transmit a second data signal 352 along the data transmit line of the selected output port 134. The second data signal 352 typically would be representative of some measurement obtained by the device. The computer can receive the second data signal 352 along the data receive line of the input port.
Next, suppose that after a length of data transmitted by the peripheral device coupled to the output port 134, it is desired to communicate with a peripheral device coupled to output port 132, corres¬ ponding to channel 2. Once again, the channel number "2" is reduced by 1 and converted into a three-bit representation. The resulting three bits, "001", are loaded into the shift register in reverse order; a "1" is loaded at time t4, a "0" is loaded at time t5, and another "0" is loaded at t6. At time t6, a data commu- nication path is established between the input port and the selected output port 132 corresponding to channel 2. In order to further illustrate the bidirectional nature of the communication path, a third data signal 354 transmitted by the computer is shown to be receivable at the peripheral device at the data receive line of the selected output port 132, and simultaneously, a fourth data signal 356 transmitted by the peripheral device is shown to be receivable at the computer at the data receive line of the input port. Moreover, the third data signal 354 transmitted by the computer is receiv¬ able only by the peripheral device at the selected output port 132 as illustrated by the RXD line for each non-selected output port being inactive after time t6. The preceding establishment of channel 2 further illustrates the generation of the secondary address signal at each of the output ports, wherein the secondary address signal is derived from a previous address signal received at the input port. At time t4, the SELECT line for each of the output ports is "0" and the SHIFT line for each of the output ports is a transi¬ tion from "0" to "1". This corresponds to the previous address signal received at the input port at time tl, namely the signal at the SELECT line being "0" and the signal at the SHIFT line being a transition from "0" to "1". Similarly, at time t5, the SELECT line is "1" and the SHIFT line is a transition from "0" to "1" for each of the output ports, which is equivalent to the address signal received at the input port at time t2. Finally, the secondary address signal at time t6, SELECT being "0" and SHIFT being a transition from "0" to "1", is equivalent to the previous address signal received at the input port at time t3. Hence, if a second cascad- able computer interface is coupled to any of the output ports, a bidirectional communication path will be established between the input port of the second inter¬ face and the output port of the second interface corre¬ sponding to channel 3. Moreover, if the second cascad- able computer interface is coupled to channel 2 of the first interface, a bidirectional data communication path is established between the input port of the first interface and the output port corresponding to channel 3 of the second cascadable interface.
A timing diagram illustrating the operation of the presence detecting means in the circuit embodiment* of the present invention is shown in Figure 6. The first means for detecting presence is assigned to channel number 8, and the second means for detecting presence is assigned to channel number 7. The computer transmits address signals along the SELECT and SHIFT lines of the input port 330, to enable channel number 8 at time t7. After time t7, the computer sends a fifth data signal 360 along the data transmit line of the input port. The first presence detecting means directs the fifth data signal 360 back to the input port along the data receive line. Next, the computer enables the second presence detecting means by transmitting address signals along the SELECT and SHIFT lines to enable channel number 7. The computer follows by sending out a sixth data signal 362 along the data transmit line of the input port . The second presence detecting means inhibits the sixth data signal 362 from being directed to the data receive line of the input port. This is evident by the seventh data signal 364 directed back to the input port along the data receive line.
A flow chart detailing a method of addressing the circuit embodiment of the present invention is shown in Figure 7. This method allows addressing based on either a base 10 channel number or a binary address. In conditional block 380, the method first determines whether a base 10 channel number or a binary address is given. If a base 10 channel number is given, then the base 10 channel number is reduced by one in block 382.
Next, the reduced base 10 channel number is converted to a three-bit binary representation in block 384. Block
386, in which the address signaling is performed, is executed if a binary address was given in block 380 or after the conversion of the base 10 channel member in block 384. The address signaling is performed as follows. For each of the bits from right to left in the binary address, DTR is set to "0", RTS is set to the bit value, followed by DTR being set to "1".
A block diagram in Figure 8 shows an example of a system for providing a communication path between a computer and a selected one of a plurality of periph¬ eral devices. In general, the system comprises one or more cascadable interfaces having an input port and a plurality of output ports. Each of the interfaces is capable of providing a local data communication path between the input port and a selected one of the plural¬ ity of output ports based upon an address signal re¬ ceived at the input port. Furthermore, each of the interfaces is capable of providing a secondary address signal at each of the plurality of output ports, the secondary address signal being based upon a previous address signal received at the input port. The cascad¬ able interfaces are generally coupled in a tree-like configuration such that each of the plurality of periph¬ eral devices is coupled to the computer by a cascade of at least one of the one or more cascadable interfaces.
The example in Figure 8 shows eleven peripher¬ al devices 400, 402, 404, 406, 408, 410, 412, 414, 416, 418, and 420, interfaced with a computer 422 using three cascadable interfaces 424, 426, and 428. The input port of the first interface 424 is coupled to the computer 422. The five output ports of the first interface 424 are coupled to peripheral A 400, peripheral B 402, peripheral C 404, the input of the second interface 426, and peripheral D 406, respectively. The five output ports of the second interface 426 are coupled to periph¬ eral E 408, the input of the third interface 428, peripheral F 410, peripheral G 412, and peripheral H 414, respectively. Three of the five output ports of the third interface 428 are employed for coupling peripheral I 416, peripheral J 418, and peripheral K 420, respectively, thereto. The resulting configuration is tree-like in that each of the eleven peripheral devices is coupled to the computer by a single corre¬ sponding cascade of at least one of the three cascadable interfaces. For example, peripheral D 406 is coupled to the computer by the cascade of the first interface 424, peripheral E 408 is coupled to the computer 422 by the cascade of the first interface 424 and the second interface 426, and peripheral J 418 is coupled to the computer by the cascade of the first, second, and third interfaces 424, 426, and 428.
The following table shows the resulting addresses for each of the eleven peripheral devices shown in Figure 8. From the table, it is immediately apparent that the number of bits in the address is not the same for each device. In general, a global address signal which initiates the data communication path between the computer and the selected one of the plural¬ ity of peripheral devices is a concatenation of a local address signal for each local communication path in the corresponding cascade. For example, the global address signal for peripheral E 408 is the local address to provide a local communication path from the input port to the channel 4 output port in the first interface, "011", concatenated with the local address which pro¬ vides a local communication path from the input port of the second interface 426 to the channel 1 output port, "000"; therefore, the resulting global address is "011000" . Table I
PERIPHERAL ADDRESS DTR BIT SEQUENCE
A 000 000
B 001 100
C 010 010
D 100 001
E Oil 000 000110
F Oil 010 010110
G Oil Oil 110110
H Oil 100 001110
I Oil 010 000 ooobioiio
J Oil 010 001 100010110
K Oil 010 010 010010110
One with ordinary skill in the art will recognize that the configuration of the system presented in Figure 8 is merely for illustrative purposes, and is not limiting with respect to the number of interfaces nor number of peripheral devices that can be configured using embodiments of the present invention. Moreover, systems for providing the data communication path between the computer and the selected one of the plural¬ ity of peripheral devices are not limited to cascadable interfaces having five output ports, nor limited to the specific protocol of secondary addressing employed.
A flow chart illustrating a method of provid¬ ing a data communication path between a computer and a selected one of a plurality of peripheral devices is shown in Figure 9. In block 450, each of the peripheral devices is coupled to the computer by a tree-like configuration of cascadable interfaces. Next, in block 452, a global address is formed for each of the periph¬ eral devices. The global addresses are formed by concatenating the local address for each local communi¬ cation path which comprises the global path from the computer to the peripheral device. In block 454, the global address for each peripheral device is stored in the computer. It is noted that the steps in blocks 450, 452, and 454 can be performed off-line during an initial set-up of the system. The computer then selects one of the peripheral devices for communication therewith in block 456. The computer follows by sending an address signal based on the stored global address for the selected device in block 458. After the address signal has been sent, the computer can communicate with the selected peripheral device using transmitted and received data signals in block 460. After communication between the computer and the selected peripheral device has completed, the method returns to block 456 enabling the computer to select another one of the peripheral devices with which to communicate.
Figure 10 shows an interface card embodiment of the present invention. An interface card 500, which contains circuitry for providing an addressable, cascad¬ able interface, can be connected to a computer 502 via an expansion slot 504. The interface card 500 has five RS-232 connectors 506 accessible from the back of the computer 502 upon installation of the card 500 in the expansion slot 504. Each of the connectors 506 is coupled to a corresponding one of the five output ports of the interface. The connectors 506 can be of the D9, D25, or DIN variety. Of course, any limitation to either the size of the connectors 506 or the number of connectors 506, imposed by the area available at the back of the interface card 500 can be overcome by providing a pigtail-type connection of the connectors 506 to the interface card 500.
It is obvious to one with ordinary skill in the art that embodiments of the present invention are not limited to the RS-232 interface standard. For example, the RS-422 interface standard, which allows for an increased transmission rate and greater port-to-port cable lengths than with RS-232, could be the basis for an embodiment employing differential transmitter and receiver circuits. Moreover, embodiments of the present invention are not limited to serial communication ports, but could be applied to parallel communication ports.
A block diagram of an alternative embodiment of an addressable computer interface 528 is shown in Figure 11. The alternative embodiment provides a first data communication path between an input port 530 and each of a plurality of output ports 532, and provides a second data communication path between the input port 530 and a selected one of the plurality of output ports 532. A fixed coupling 534 between a representative first data signal line 536 of the input port 530 and a representative first data signal line 538 of each of the plurality of output ports 532 provides the first data communication path. A data selector circuit 540 re¬ ceives an address signal along a representative address signal line 542 of the input port 530 to identify the selected one of the plurality of output ports 532 to which the second data communication path is to be provided. The data selector circuit 540 responds by providing the second data communication path between a representative second data signal line 544 of the input port 530 and a representative second data signal line 546 of the selected one of the output ports. An address generator 548 provides a secondary address signal along a representative secondary address line 550 to each of the plurality of output ports capable of driving a like cascadable computer interface. The secondary address signal is derived from a previous address signal received at the input port 530.
The use of the expression "representative line" in describing means for transferring signals is not to be construed as limiting with regard to the mode of signal transfer nor the number of interconnections provided by the line. For example, a generic represen¬ tative line can represent one or more wires for provid- ing signal transfer.
The alternative embodiment differs from aforementioned embodiments in that the first data communication path is continually provided between the input port and each of the output ports, in addition to the selectable second data communication path. In a similar manner as with the aforementioned embodiments, the transmission of the secondary address signal allows the addressable computer interface 528 to be cascadably interfaced to a like addressable computer interface, wherein the input port 530 of the like addressable computer interface is coupled to one of the output ports 532 of the interface 528.
A specific alternative embodiment is illus¬ trated by the schematic drawing in Figure 12. The input port 530 and the output ports are parallel communica¬ tions ports, each comprising a plurality of data lines 560 and a plurality of control lines 562. The distinc¬ tion between data lines and control lines is made with respect to operation of the interface 528, and not with respect to a common application of parallel communica- tions ports, namely, for control of a parallel printer. Specifically, data lines are used for communication via either the first or the second data communication path and control lines are employed for controlling the addressing of the interface 528. In general, the set of data lines and the set of control lines need not be mutually exclusive. For the sake of clarity, the coupling of the common ground lines of all ports is not shown in the schematic drawing of either Figure 12 or Figure 14.
A bus 564 provides a fixed, parallel coupling between eight parallel lines 566 of the input port 530 and eight parallel lines 568 of each of the output ports 532. The eight parallel lines enable eight parallel bits of data to be sent and received at a time via the interface 528. The bus 564 further provides a coupling between a strobe line 570 of the input port 530 and a strobe line 572 of each of the output ports 532. The strobe line is typically employed for signaling when the eight parallel lines of a parallel port are set and valid for reading by the remote device.
The address generator 548 is formed by a shift register 574 having a data input 576, a clock input 578, and a plurality of outputs 580. The data input 576 is coupled to a first control line 582 and the clock input is coupled to a second control line 584 of the input * port. In response to a clock pulse received at the input port 530 along the second control line 584, the shift register 574 shifts the values of the plurality of outputs 580 by one output position, and inserts a bit derived from a signal present at the first control line 582 into a resulting open output position. To make the interface 528 cascadable by providing secondary address signals, a first control line 586 of each of the output ports 532 is coupled to a most significant bit output 588 of the shift register 574, and a second control line of each of the output ports 532 is coupled to the second control line 584 of the input port 530. As with the aforementioned embodiments, the shift register 574 is implemented by a cascaded connection of three flip-flops 592, 594, and 596.
The data selector 540 is provided by a first demultiplexer 600, a second demultiplexer 602, a first multiplexer 604, and a second multiplexer 606. Each of the first demultiplexer 600, the second demultiplexer 602, the first multiplexer 604, and the second multiplexer 606 includes a plurality of selection inputs 610, 612, 614, and 616, respectively, for coupling with the outputs 580 of the shift register 574. The first demultiplexer 600 further contains a demultiplexer input 618 coupled to a first selectable line 620 of the input port 530, and a plurality of demultiplexer outputs 622 coupled to a corresponding first selectable line 624 for each of the output ports 532. Similarly, the second demultiplexer 602 further contains a demultiplexer input 628 coupled to a second selectable line 630 of the input port 530, and a plurality of demultiplexer outputs 632 coupled to a corresponding second selectable line 634 for each of the output ports 532. Based upon the address signal received at the first and second control lines 582 and 584, the first and second demultiplexers 600 and 602 each provide a data transmission path from the input port 530 to the selected one of the output ports 532.
The first multiplexer 604 includes a multi- plexer output 638 coupled to a third selectable line 640 of the input port 530, and a plurality of multiplexer inputs 642 coupled to a corresponding third selectable line 644 for each of the output ports 532. In a similar manner, the second multiplexer 606 further contains a multiplexer output 648 coupled to a fourth selectable line 650. of the input port 530 and a plurality of multiplexer inputs 652 coupled to a corresponding fourth selectable line 654 for each of the output ports 532. The first and second multiplexers 604 and 606 each provide a data transmission path from the selected one of the output ports 532 to the input port 530.
The interface 528 of Figure 12 further includes presence detecting means as the embodiment of Figure 4. A first means of detecting presence is produced by coupling a loopback input 656 of the first multiplexer 604 with a loopback output 658 of the first demultiplexer 600, wherein the loopback input 656 and loopback output 658 are enabled for the same selection inputs. A second means of detecting presence is pro- duced by leaving input 660 of the first multiplexer 604 open. The same method of presence detection used in the embodiment of Figure 4 is employed using the first selectable line 620 and the third selectable line 640 of the input port 530.
One with ordinary skill in the art will recognize that many alternative embodiments of the interface of Figure 12 can be devised. For example, a different number of parallel lines can be included in the bus 564 for parallel ports which send and receive bytes comprising other than eight bits. Further, at least one of the parallel lines can ' be applied to the data selector circuit 540 rather than the bus 564 for the purpose of making the parallel lines selectable. Likewise, the strobe line can be applied to the data selector circuit 540 rather than the bus 564 to allow a selected remote device to signal the computer when the data lines are set and valid for reading in a bi-direc¬ tional parallel port. Also, the number of demulti¬ plexers and the number of multiplexers employed in the data selector circuit 540 are not limited to two; the data selector circuit 540 is said to generally contain at least one demultiplexer or at least one multiplexer.
The previously described versions of the present invention have many advantages. One such advantage is that the use of secondary addressing allows identical embodiments of the interface to be cascaded, thus providing any number of addressable multiplexed output ports necessary for the application of interest .
Another advantage is that remote peripheral devices need not have inherent addressing circuitry for use with embodiments of the invention. The remote peripheral devices are addressed by the use of secondary address signals which produce global shift registers formed by individual local shift registers in each interface unit .
A further advantage of an embodiment of the present invention is that it is inexpensive to manufac- ture. By employing a demultiplexer, a multiplexer, and either a shift register or discrete flip-flops, embodi¬ ments of the cascadable interface can be economically constructed using conventional integrated circuits .
While the best mode for carrying out the invention has been described in detail, those familiar with the art to which this invention relates will recognize various alternative designs and embodiments for practicing the invention defined by the following claims.

Claims

What is Claimed is:
1. A cascadable computer interface apparatus for providing a data communication path between an input port and a selected one of a plurality of output ports, the apparatus comprising: a data selector circuit, responsive to a received signal indicating the selected one of the plurality of output ports, for providing the data commu¬ nication path between the input port and the selected one of the plurality of output ports; and a secondary signal generator, responsive to the received signal, which provides a secondary signal to each of the plurality of output ports capable of driving a like cascadable computer interface apparatus, wherein the secondary signal is derived from a previous received signal.
2. The apparatus of claim 1 wherein the re¬ ceived signal is an address signal.
3. The apparatus of claim 1 wherein the secondary signal is a secondary address signal.
4. The apparatus of claim 1 wherein the re¬ ceived signal is received at the input port.
5. The apparatus of claim 1 wherein the data selector circuit comprises a multiplexer, responsive to the received signal, for providing a first data trans¬ mission path from the selected one of the plurality of . output ports to the input port.
6. The apparatus of claim 1 wherein the data selector circuit comprises a demultiplexer, responsive to the received signal, for providing a second data transmission path from the input port to the selected one of the plurality of output ports.
7. The apparatus of claim 1 wherein the input port is a parallel communications port.
8. The apparatus of claim 1 wherein the input port is a RS-232 serial communications port.
9. The apparatus of claim 8 wherein the input port comprises a data transmit line, a data receive line, a first control line, and a second control line.
10. The apparatus of claim 8 further compris¬ ing line receiver means for converting RS-232 logic signals at the input port to TTL logic signals.
11. The apparatus of claim 1 wherein each of the plurality of output ports is a RS-232 serial commu¬ nications port.
12. The apparatus of claim 11 wherein each of the plurality of output ports comprises a data transmit line, a data receive line, a first control line, and a second control line.
13. The apparatus of claim 11 further com¬ prising line driver means for converting TTL logic signals to RS-232 logic signals for application at each of the plurality of output ports.
14. The apparatus of claim 1 wherein the re¬ ceived signal and the secondary signal are digital signals .
15. The apparatus of claim 14 wherein the received signal and the secondary signal each comprise a first control signal and a second control signal.
16. The apparatus of claim 15 wherein the data selector circuit comprises a shift register having a data input, a clock input, and a plurality of outputs wherein the data input is responsive to the first control signal, the clock input is responsive to the second control signal, and the plurality of outputs identifies the selected one of the plurality of output ports.
17. The apparatus of claim 1 further compris¬ ing presence detecting means, responsive to the received signal, for providing a presence signal to the input port.
18. The apparatus of claim 17 wherein the presence detecting means comprises: data inhibit means for inhibiting transmission of data signals from each of the plurality of output ports to the input port .
19. The apparatus of claim 17 wherein the presence detecting means comprises: first presence means for returning a data signal received at the input port back to the input port in response to a first selected received signal.
20. The apparatus of claim 17 wherein the presence detecting means comprises: second presence means for inhibiting transmis¬ sion of a data signal received at the input port back to the input port in response to a second selected received signal .
21. The apparatus of claim 1 wherein the secondary signal generator provides the secondary signal to each of the plurality of output ports.
22. A computer interface apparatus for providing a data communication path between an input port and a selected one of a plurality of output ports, wherein the input port and each of the plurality of output ports is a RS-232 serial communications port having a data transmit line, a data receive line, a first control line, and a second control line, the apparatus comprising: a shift register having a data input, a clock input, and a plurality of outputs, wherein the data input is responsive to a first control signal received from the first control line of the input port, and wherein the clock input is responsive to a second control signal received from the second control line, so that the plurality of outputs identifies the selected one of the plurality of output ports; a multiplexer responsive to the plurality of outputs of the shift register, for providing a first data transmission path from the data transmit line of the selected one of the plurality of output ports to the data receive line of the input port; and a demultiplexer, responsive to the plurality of outputs of the shift register, for providing a second data transmission path from the data transmit line of the input port to the data receive line of the selected one of the plurality of output ports; wherein the first control line of each of the plurality of output ports is coupled to a selected one of the plurality of outputs of the shift register, and the second control line of each of the plurality of output ports is coupled to the second control line of the input port.
23. A system for providing a data communica¬ tion path between a computer and a selected one of a plurality of peripheral devices, the system comprising: one or more cascadable interfaces having an input port and a plurality of output ports, each of the interfaces capable of providing a local data communica¬ tion path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port, each of the interfac¬ es further capable of providing a secondary address signal at each of the plurality of output ports capable of driving a like cascadable interface, the secondary address signal being derived from a previous address signal received at the input port, wherein the one or more cascadable interfaces are coupled in a tree-like configuration such that each of the plurality of periph¬ eral devices is coupled to the computer by a cascade of at least one of the one or more cascadable interfaces; wherein the data communication path is provid¬ ed in response to a global address signal generated by the computer, the global address signal containing the address signal for each local data communication path forming the cascade of the at least one of the one or more interfaces coupling the selected one of the periph¬ eral devices to the computer.
24. The system of claim 23 wherein the one or more cascadable interfaces are all of identical design.
25. The system of claim 23 wherein the global address signal is a concatenation of the local address signal for each local communication path in the cascade of the at least one of the one or more interfaces coupling the selected one of the peripheral devices to the computer.
26. A method of providing a data communica¬ tion path between a computer and a selected one of a plurality of peripheral devices, the method comprising the steps of: coupling each of the plurality of peripheral devices to the computer by a tree-like coupling of one or more cascadable interfaces, each of the interfaces having an input port and a plurality of output ports, each of the interfaces being capable of providing a local data communication path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port, such that each of the plurality of peripheral devices is coupled to the computer by a cascade of at least one of the one or more cascadable interfaces; and sending a global address signal containing a local address signal for each local data communication path in the cascade of at least one of the one or more cascadable interfaces coupling the selected one of the peripheral devices to the computer; wherein the data communication path is provid¬ ed by an aggregation of each local data communication path forming the cascade coupling the selected one of the peripheral devices to the computer in response to a global address signal generated by the computer.
27. A cascadable computer interface apparatus for providing a first data communication path between an input port and each of a plurality of output ports, and for providing a second data communication path between the input port and a selected one of the plurality of output ports, the apparatus comprising: coupling means for providing the first data communication path between the input port and each of the plurality of output ports; a data selector circuit, responsive to a received signal indicating the selected one of the plurality of output ports, for providing the second data communication path between the input port and the selected one of the plurality of output ports; and a secondary signal generator, responsive to the received signal, which provides a secondary signal to each of the plurality of output ports capable of driving a like cascadable computer interface apparatus, wherein the secondary address signal is derived from a previous received signal.
28. A computer interface apparatus compris¬ ing: a serial input port; a plurality of serial output ports; and a data selector providing a data communication path between the serial input port and a selected one of the plurality of serial output ports in response to a received signal indicating the selected one of the plurality of serial output ports.
29. The apparatus of claim 28 wherein the received signal is an address signal.
30. The apparatus of claim 28 wherein the received signal is received at the serial input port.
31. The apparatus of claim 28 wherein the data selector comprises a multiplexer, responsive to the received signal, for providing a first data transmission path from the selected one of the plurality of serial output ports to the serial input port.
32. The apparatus of claim 28 wherein the data selector comprises a demultiplexer, responsive to the received signal, for providing a second data trans- mission path from the serial input port to the selected one of the plurality of serial output ports.
33. The apparatus of claim 28 wherein the serial input port is a RS-232 serial port.
34. The apparatus of claim 33 wherein the serial input port comprises a data transmit line, a data receive line, a first control line, and a second control line.
35. The apparatus of claim 33 further com¬ prising line receiver means for converting RS-232 logic signals at the serial input port to TTL logic signals.
36. The apparatus of claim 28 wherein each of the plurality of serial output ports is a RS-232 serial port .
37. The apparatus of claim 36 wherein each of the plurality of serial output ports comprises a data transmit line, a data receive line, a first control line, and a second control line.
38. The apparatus of claim 36 further com¬ prising line driver means for converting TTL logic signals to RS-232 logic signals for application at each of the plurality of serial output ports.
39. The apparatus of claim 28 wherein the received signal is a digital signal.
40. The apparatus of claim 28 wherein the received signal comprises a first control signal and a second control signal.
41. The apparatus of claim 40 wherein the data selector comprises a shift register having a data input, a clock input, and a plurality of outputs, wherein the data input is responsive to the first control signal, the clock input is responsive to the second control signal, and the plurality of outputs identifies the selected one of the plurality of serial output ports .
42. The apparatus of claim 28 further com¬ prising presence detecting means, responsive to the received signal, for providing a presence signal to the serial input port .
43. The apparatus of claim 42 wherein the presence detecting means comprises: data inhibit means for inhibiting transmission of data signals from each of the plurality of serial output ports to the serial input port .
44. The apparatus of claim 42 wherein the presence detecting means comprises: first presence means for returning a data signal received at the serial input port back to the serial input port in response to a first selected received signal.
45. The apparatus of claim 42 wherein the presence detecting means comprises: second presence means for inhibiting transmis- sion of a data signal received at the serial input port back to the serial input port in response to a second selected received signal.
46. A computer system comprising: a computer having a communication port; a plurality of peripheral devices, each of the plurality of peripheral devices having a corresponding communication port; and one or more cascadable interfaces having an input port and a plurality of output ports, each of the interfaces capable of providing a local data communica¬ tion path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port, each of the interfac¬ es further capable of providing a secondary address signal at each of the plurality of output ports capable of driving a like cascadable interface, the secondary address signal being derived from a previous address signal received at the input port, wherein the one or more cascadable interfaces are coupled in a tree-like configuration such that the corresponding communication port of each of the plurality of peripheral devices is coupled to the communication port of the computer by a cascade of at least one of the one or more cascadable interfaces; wherein the computer communicates with a selected one of the plurality of peripheral devices upon sending a global address signal containing the address signal for each local data communication path forming the cascade of the at least one of the one or more interfaces coupling the computer to the selected one of the peripheral devices.
47. A peripheral system for a computer having a communication port, the peripheral system having a communication port for interfacing with the communica¬ tion port of the computer, the peripheral system com- prising: a plurality of peripheral devices, each of the plurality of peripheral devices having a corresponding communication port; and one or more cascadable interfaces having an input port and a plurality of output ports, each of the interfaces capable of providing a local data communica¬ tion path between the input port and a selected one of the plurality of output ports based upon an address signal received at the input port, each of the interfac- es further capable of providing a secondary address signal at each of the plurality of output ports capable of driving a like cascadable interface, the secondary address signal being derived from a previous address signal received at the input port, wherein the one or more cascadable interfaces are coupled in a tree-like configuration such that the corresponding communication port of each of the plurality of peripheral devices is coupled to the communication port of the computer by a cascade of at least one of the one or more cascadable interfaces; wherein the computer communicates with a selected one of the plurality of peripheral devices upon sending a global address signal containing the address signal for each local data communication path forming the cascade of the at least one of the one or more interfaces coupling the computer to the selected one of the peripheral devices.
PCT/US1995/000323 1994-01-18 1995-01-09 Addressable communication port expander WO1995019596A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US183,223 1994-01-18
US08/183,223 US5619722A (en) 1994-01-18 1994-01-18 Addressable communication port expander

Publications (1)

Publication Number Publication Date
WO1995019596A1 true WO1995019596A1 (en) 1995-07-20

Family

ID=22671965

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/000323 WO1995019596A1 (en) 1994-01-18 1995-01-09 Addressable communication port expander

Country Status (2)

Country Link
US (1) US5619722A (en)
WO (1) WO1995019596A1 (en)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768615A (en) * 1995-11-30 1998-06-16 Compaq Computer Corp. Method and apparatus for functional expansion through predefined signal interfaces
KR0152228B1 (en) * 1995-12-23 1998-11-02 양승택 Method for transmitting and receiving data by using dispersed routine control in data switching system
US5822548A (en) * 1996-01-16 1998-10-13 Vlsi Technology, Inc. Programming interface for a universal asynchronous receiver/transmitter
US5832244A (en) * 1996-02-20 1998-11-03 Iomega Corporation Multiple interface input/output port for a peripheral device
US5761534A (en) * 1996-05-20 1998-06-02 Cray Research, Inc. System for arbitrating packetized data from the network to the peripheral resources and prioritizing the dispatching of packets onto the network
US5901325A (en) * 1996-05-20 1999-05-04 Hewlett-Packard Company Extended addressing to multiple devices on a single parallel I/O port
US7043543B2 (en) * 1996-07-23 2006-05-09 Server Technology, Inc. Vertical-mount electrical power distribution plugstrip
US5884102A (en) * 1997-05-30 1999-03-16 Intel Corporation Method and apparatus for a configurable means of connection between an embedded processor and a personal computer
US6112258A (en) * 1998-03-19 2000-08-29 3Com Corporation Multi-cycle I/O ASIC communication system having an arbiter circuit capable of updating address table associated with each I/O ASIC on bus
US6085260A (en) * 1998-06-08 2000-07-04 Ford Motor Company Method and circuit for multiplexing an input port and an output port of a microprocessor into a single external interface
US6330246B1 (en) 1998-08-21 2001-12-11 International Business Machines Corporation Method and system for switching SCSI devices utilizing an analog multiplexor
KR100406967B1 (en) * 1998-12-11 2004-03-26 엘지전자 주식회사 Parallel Port Multiple Input Expansion Unit
US6370652B1 (en) 1999-06-21 2002-04-09 Visteon Global Technologies, Inc. Control of I.C.'s having different command protocols via common communication lines from a controlling I.C. on a different circuit board
US7080319B1 (en) * 1999-09-29 2006-07-18 Lucent Technologies Inc. Technology to translate non-text display generation data representing an indicator into text variables
JP4553279B2 (en) * 2000-03-09 2010-09-29 インターナショナル・ビジネス・マシーンズ・コーポレーション Data transfer system, data transfer terminal, controller, and interface method
US6981086B2 (en) * 2000-12-21 2005-12-27 National Instruments Corporation Instrumentation system including a backplane having a switched fabric bus and instrumentation lines
US6804737B2 (en) 2000-12-26 2004-10-12 Lsi Logic Corporation Methods and systems for intelligent I/O controller with channel expandability via master/slave configuration
KR100498499B1 (en) * 2003-05-15 2005-07-01 삼성전자주식회사 Apparatus for testing hard disk driver
KR100518572B1 (en) * 2003-05-15 2005-10-04 삼성전자주식회사 Method and appartus for communicating in serial multi port, and recording medium
US7414329B2 (en) 2003-10-30 2008-08-19 Server Technology, Inc. Polyphase power distribution and monitoring apparatus
US7368830B2 (en) * 2003-10-30 2008-05-06 Server Technology, Inc. Polyphase power distribution and monitoring apparatus
US7171506B2 (en) * 2003-11-17 2007-01-30 Sony Corporation Plural interfaces in home network with first component having a first host bus width and second component having second bus width
US8543723B2 (en) * 2004-07-27 2013-09-24 Sony Corporation Home network system with transmission error recovery
EP1884769B1 (en) * 2006-08-04 2018-12-05 Medica S.p.A. Conductivity probe and dialysis machine comprising the probe
FR2913155B1 (en) * 2007-02-26 2009-04-24 Sagem Defense Securite SELECTIVE CONNECTION DEVICE FOR CONNECTING AT LEAST ONE DEVICE TO A TARGET COMPUTER AND A SELECTIVE CONTROL SYSTEM COMPRISING SUCH A DEVICE
US7904566B2 (en) * 2008-03-14 2011-03-08 Silicon Image, Inc. Method, apparatus, and system for employing an enhanced port multiplier
US8625586B2 (en) 2010-12-31 2014-01-07 Stmicroelectronics International N.V. Generic bus de-multiplexer/port expander with inherent bus signals as selectors
KR101819235B1 (en) * 2011-06-08 2018-01-16 엘에스산전 주식회사 Parallel communication device
TWI453605B (en) * 2012-11-13 2014-09-21 Askey Computer Corp Data transmission selection circuit and method
US10055376B1 (en) * 2015-01-15 2018-08-21 Maxim Integrated Products, Inc. Serial peripheral interface system with slave expander
JP2019159471A (en) * 2018-03-08 2019-09-19 キヤノン株式会社 Storage system, control method thereof and program
RU188797U1 (en) * 2018-07-12 2019-04-23 Акционерное общество "Саратовский электроприборостроительный завод имени Серго Орджоникидзе" DEVICE INPUT AND OUTPUT OF SINGLE COMMANDS
CN111462681B (en) * 2020-04-21 2024-01-30 深圳天源中芯半导体有限公司 Multipath cascade application system and control method for detecting and receiving correct data thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079452A (en) * 1976-06-15 1978-03-14 Bunker Ramo Corporation Programmable controller with modular firmware for communication control
US4390967A (en) * 1980-10-14 1983-06-28 Interface Systems, Inc. Interface system wherein the interface is addressed before data transfer from a selected device
US4968977A (en) * 1989-02-03 1990-11-06 Digital Equipment Corporation Modular crossbar interconnection metwork for data transactions between system units in a multi-processor system
US5138703A (en) * 1988-03-31 1992-08-11 Kabushiki Kaisha Toshiba Method of and apparatus for expanding system bus
US5274783A (en) * 1991-06-28 1993-12-28 Digital Equipment Corporation SCSI interface employing bus extender and auxiliary bus
US5313589A (en) * 1991-05-15 1994-05-17 Ibm Corporation Low level device interface for direct access storage device including minimum functions and enabling high data rate performance

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3597743A (en) * 1969-03-26 1971-08-03 Digital Applic Inc Expander for real-time communication between a computer and external devices
US3648252A (en) * 1969-11-03 1972-03-07 Honeywell Inc Multiprogrammable, multiprocessor computer system
US3902162A (en) * 1972-11-24 1975-08-26 Honeywell Inf Systems Data communication system incorporating programmable front end processor having multiple peripheral units
US4254473A (en) * 1979-01-29 1981-03-03 Allen-Bradley Company Rack adapter for serially connected I/O interface racks
US4264954A (en) * 1979-09-04 1981-04-28 Ncr Corporation Distributed function communication system for remote devices
JPS5750049A (en) * 1980-09-09 1982-03-24 Toshiba Corp Shifting circuit
US4443884A (en) * 1982-03-18 1984-04-17 Protocol Computers, Inc. Data line interface
US4504927A (en) * 1982-09-08 1985-03-12 Allen-Bradley Company Programmable controller with expandable I/O interface circuitry
JPS6075903A (en) * 1983-09-30 1985-04-30 Matsushita Electric Works Ltd Sequence controller
US4794525A (en) * 1984-06-07 1988-12-27 Motorola, Inc. External interface control circuitry for microcomputer systems
US4607170A (en) * 1985-03-01 1986-08-19 Digitel, Inc. Data communication interconnect device
IT1184933B (en) * 1985-03-28 1987-10-28 Olivetti & Co Spa INTEGRATION CIRCUIT FOR DATA TRANSMISSION AND RECEPTION
US5062076A (en) * 1985-07-12 1991-10-29 Wang Laboratories, Inc. Cascadable, high-bandwidth, multi-channel image transfer controller
US5134691A (en) * 1986-04-01 1992-07-28 Westinghouse Electric Corp. Bidirectional communication and control network with programmable microcontroller interfacing digital ICs transmitting in serial format to controlled product
US4794520A (en) * 1987-03-30 1988-12-27 C-Guard Laboratories, Inc. Interface system for computer port sharing of multiple devices
US5191655A (en) * 1987-10-13 1993-03-02 Standard Microsystems Corporation Interface arrangement for facilitating data communication between a computer and peripherals
US5060134A (en) * 1988-05-12 1991-10-22 Motorola, Inc. Action direction port expansion circuit and system
US5261057A (en) * 1988-06-30 1993-11-09 Wang Laboratories, Inc. I/O bus to system interface
US5051980A (en) * 1988-08-11 1991-09-24 El Paso Natural Gas Company Data communication interface device
US5014193A (en) * 1988-10-14 1991-05-07 Compaq Computer Corporation Dynamically configurable portable computer system
US5243700A (en) * 1988-12-30 1993-09-07 Larsen Robert E Port expander architecture for mapping a first set of addresses to external memory and mapping a second set of addresses to an I/O port
US5263141A (en) * 1989-01-31 1993-11-16 Brother Kogyo Kabushiki Kaisha Microprocessor with an exclusive address terminal for selecting at least one part of a peripheral device
US5045675A (en) * 1989-05-15 1991-09-03 Dallas Semiconductor Corporation Serial port interface to low-voltage low-power data module
US5239629A (en) * 1989-12-29 1993-08-24 Supercomputer Systems Limited Partnership Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system
US5175819A (en) * 1990-03-28 1992-12-29 Integrated Device Technology, Inc. Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer
US5175820A (en) * 1990-08-31 1992-12-29 Advanced Micro Devices, Inc. Apparatus for use with a computing device controlling communications with a plurality of peripheral devices including a feedback bus to indicate operational modes
JPH04141896A (en) * 1990-10-02 1992-05-15 Nec Corp Serial-parallel conversion circuit
US5280586A (en) * 1991-10-03 1994-01-18 Compaq Computer Corp. Expandable communication system using data concentration

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079452A (en) * 1976-06-15 1978-03-14 Bunker Ramo Corporation Programmable controller with modular firmware for communication control
US4390967A (en) * 1980-10-14 1983-06-28 Interface Systems, Inc. Interface system wherein the interface is addressed before data transfer from a selected device
US5138703A (en) * 1988-03-31 1992-08-11 Kabushiki Kaisha Toshiba Method of and apparatus for expanding system bus
US4968977A (en) * 1989-02-03 1990-11-06 Digital Equipment Corporation Modular crossbar interconnection metwork for data transactions between system units in a multi-processor system
US5313589A (en) * 1991-05-15 1994-05-17 Ibm Corporation Low level device interface for direct access storage device including minimum functions and enabling high data rate performance
US5274783A (en) * 1991-06-28 1993-12-28 Digital Equipment Corporation SCSI interface employing bus extender and auxiliary bus

Also Published As

Publication number Publication date
US5619722A (en) 1997-04-08

Similar Documents

Publication Publication Date Title
US5619722A (en) Addressable communication port expander
EP0522764B1 (en) Multiplexing scheme for modem control signals
US5758073A (en) Serial interface between DSP and analog front-end device
US5768546A (en) Method and apparatus for bi-directional transfer of data between two buses with different widths
US4048673A (en) Cpu - i/o bus interface for a data processing system
US5416909A (en) Input/output controller circuit using a single transceiver to serve multiple input/output ports and method therefor
US4106091A (en) Interrupt status indication logic for polled interrupt digital system
US4417320A (en) Interface for data communication systems using serial biphase data transmissions
EP1816570A3 (en) Integrated circuit I/O using a high performance bus interface
US7177965B2 (en) Linking addressable shadow port and protocol for serial bus networks
EP0589499B1 (en) A multistation communication bus system, and a master station and a slave station for use in such system
KR100309082B1 (en) Multistation communication bus system, main station and slave station
US5142556A (en) Data transfer system and method of transferring data
US4047246A (en) I/O bus transceiver for a data processing system
US6487620B1 (en) Combined low speed and high speed data bus
US4823305A (en) Serial data direct memory access system
US6535522B1 (en) Multiple protocol interface and method for use in a communications system
JPS6239580B2 (en)
US4047201A (en) I/O Bus transceiver for a data processing system
US4604620A (en) Information transmission system
US6470404B1 (en) Asynchronous communication device
US6360290B1 (en) Commercial standard digital bus interface circuit
US5504911A (en) Bus system servicing plural module requestors with module access identification
US4910509A (en) Bus expander for digital TV receiver
US4040032A (en) Peripheral device controller for a data processing system

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA DE GB JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: CA

122 Ep: pct application non-entry in european phase