WO1993016535A1

WO1993016535A1 - Pointer jitter suppression in a desynchronizer

Info

Publication number: WO1993016535A1
Application number: PCT/FI1993/000045
Authority: WO
Inventors: Reino Urala
Original assignee: Nokia Telecommunications Oy
Priority date: 1992-02-14
Filing date: 1993-02-12
Publication date: 1993-08-19
Also published as: SE9402708L; FI920643A; SE9402708D0; FI920643A0; FI90709B; GB2279522A; DE4390463T1; GB9416172D0; GB2279522B; AU3500693A; SE518361C2; FI90709C

Abstract

The invention relates to an arrangement for suppressing pointer justification jitter in a desynchronizer in a digital transmission system, the desynchronizer comprising a data buffer (1); a data buffer write address counter (2) controlled by a write clock (CLK1); a data buffer read address counter (3) controlled by a read clock (CLK2); and a phase-locked loop comprising a phase comparator (4), a loop filter (A1) and a voltage-controlled oscillator (5) for adjusting said read clock on the basis of the phase difference between the read and write clocks. According to the invention, the arrangement comprises means (A2, 71, 81) for positively controlling the phase-locked loop so as to limit, in synchronization with the time of occurrence of each pointer justification, the maximum amplitude of the phase jitter induced in an output signal (DATA OUT) of the desynchronizer by said pointer justification.

Description

Pointer jitter suppression in a desynchronizer

Field of the Invention

The invention relates to an arrangement for suppressing pointer justification jitter in a de¬ synchronizer in a digital transmission system, the desynchronizer comprising a data buffer means; a data buffer write address counter controlled by a write clock; a data buffer read address counter controlled by a read clock; and a phase-locked loop comprising a phase comparator means, a loop filter means and a voltage-controlled oscillator means for adjusting said read clock on the basis of the phase difference between the read and write clocks.

Background of the Invention

The CCITT recommendations G.707, G.708 and G.709 specify a synchronous digital hierarchy SDH, which enables the multiplexing of the signals of e.g. existing PCM systems, such as 2, 8, 34 and 140 Mbit/s, into a synchronous frame of 155 Mbit/s called STM-1 (synchronous transfer module). The structure of the STM-1 frame is illustrated in Figure 1. The frame is usually shown as a unit comprising nine lines each having 270 bytes. The first nine bytes on each line contain a section overhead and AU pointer bytes. The remaining portion of the transfer frame STM-1 con¬ tains one or more administration units AU. In this specific case, there is an administration unit AU-4 of the highest level, in which a virtual container VC-4 similarly of the highest level is placed, and e.g. a 139264 kbit/s plesiochronous information signal can be mapped directly in the virtual container VC-4. Alternatively, the transfer frame STM-1 may contain several lower-level administration units AU in each one of which a corresponding virtual container VC of the lowest level is placed. In Figure 1, the VC-4 comprises a 1-byte path overhead POH and a 240-byte information bit group at the start of both of which a special control byte is placed. Some of the control bytes are used e.g. for performing inter¬ face justification in connection with mapping when the rate of the information signal to be mapped devi¬ ates to some extent from its nominal value. Mapping of the information signal into the transfer frame STM-1 is described e.g. in the patent applications AU-B-34639/89 and FI-914746.

Each byte in the unit AU-4 has a position number. The above-mentioned AU pointer contains the position of the first byte of the container VC-4 in the unit AU-4. In addition, by means of the pointers, so-called positive or negative pointer justifications can be performed at different locations in the SDH network. If a VC having a certain clock frequency is applied to a network node operating at a clock fre¬ quency lower than the above-mentioned clock frequency of the VC, the data buffer will be filled up. This requires negative justification: one byte is trans¬ ferred from the received VC into the overhead section while the pointer value is decreased by one.

If the rate of the received VC is lower than the clock rate of the node, the data buffer tends to be emptied, which calls for positive justification in which a stuff byte is added to the VC and the pointer value is incremented by one.

Bit justification (interface justification) used in mapping as well as pointer justification cause phase jitter, which should be compensated for by the desynchronizer on leaving the SDH network. Phase jitter and its compensation are described e.g. in Simulation Results and Field Trial Experience of Justification Jitter, Ralph Urbansky, 6th World Tele¬ communication Forum, Geneva, 10-15 October 1991, International Telecommunication Union, Part 2, Vol III, p. 45 to 49.

For this purpose the prior art desynchronizers comprise a data buffer with an associated analog phase-locked loop (P L) which phase-locks the read clock of the data buffer to the write clock. As the PLL operates in the same way as a lowpass filter, it removes jitter except for the most low-frequency jitter components. For instance, the pointer justi¬ fication of the SDH typically generates much more intensive jitter components than bit justification as individual phase discontinuities in the pointer jus¬ tification are e.g. 8 or 24 frame intervals UI and as the frequency of occurrence of phase discontinuities induced by pointer justifications may represent a very low frequency difficult to filter in the PLL of the desynchronizer. Adequate suppression of pointer jitter by filtering would require that the bandwidth of the loop should be very low (the absolute value depends on the rate of the interface) . Figures 2 and 3 show how the jitter peaks induced by two pointer justifications of 24 UI (measured from the output of the desynchronizer through a measuring filter spe¬ cified by the CCITT) can be reduced to an acceptable maximum level of about 0.2 UI by drastic filtering when the bandwidth of the PLL at e.g. 140 Mbit/s is about 2 Hz. However, no pointer justifications are needed in normal operation, and only interface bit justifications are active. Accordingly, the dimen¬ sioning of the PLL of the desynchronizer on the basis of pointer justifications is unreasonable as the bandwidth of the PLL could be even ten times higher from the viewpoint of bit justification. The locking of the PLL would thereby also be more reliable and the locking time would be substantially shorter.

One prior art solution to the problem is bit leaking, in which pointer induced phase discontinu¬ ities are removed by a non-linear process (in the time domain), whereby incoming data bits are process¬ ed by a separate serial buffer so that the phase of the write clock and data applied to the buffer of the desynchronizer is advanced (or retarded) periodical¬ ly, and so a stepwise phase shift is converted into a linear phase shift taking place over a longer period of time. The pointer justifications are thereby pro¬ cessed separately by a bit leaking buffer so that the bandwidth of the phase-locked loop of the desynchron¬ izer itself can be increased so as to meet the re¬ quirements of the bit justifications. A problem with bit leaking is the bit-level serial data processing and the relatively complicated logic. It is further to be noted that it is not adequate that one pointer at a time can be processed but, in the worst case, the logic should be able to operate with tens of overlapping pointer justifications at different decay stages. Therefore the use of this technique in a high-rate 140 Mbit/s desynchronizer is not advisable due to the increased power consumption, for instance.

Disclosure of the Invention

The object of the invention is to provide a simple and economical arrangement for suppressing pointer jitter peaks, which is also suitable for the rate of 140 Mbit/s and even higher rates.

This is achieved by an arrangement according to the invention, which is characterized in that the arrangement comprises means for positively con- trolling the phase-locked loop so as to limit, in synchronization with the time of occurrence of each pointer justification, the maximum amplitude of the phase jitter induced in an output signal of the de- synchronizer by said pointer justification.

The basic idea of the invention is that a com¬ pensation adjustment timed to coincide with the pointer justification is performed in the phase- locked loop itself so as to limit the abrupt phase jitter amplitude induced by the pointer justification and to "spread" the jitter. In the preferred embodi¬ ment of the invention the compensation adjustment is performed by summing a voltage pulse the front edge of which is coincident with the pointer justification with the input signal of the loop filter or with the control voltage of the loop oscillator. The compens¬ ating voltage pulse is preferably integrated so that its front edge is coincident with but opposite to the voltage change caused by the pointer justification, whereas the back edge of the pulse falls slowly, e.g. exponentially. The rising (or falling) front edge of the compensating pulse limits efficiently the abrupt jitter amplitude while the long exponentially falling (or rising) back edge "spreads" the phase jitter in- duced by the phase discontinuity over a longer period of time, e.g. over 1 second.

In another embodiment of the invention, the phase-locked loop comprises means for limiting the amplitude of the control voltage of the voltage- controlled oscillator for a predetermined period of time beginning from the time of occurrence of each pointer justification. The limiting of amplitude level also inherently involves limiting the maximum amplitude of the pointer jitter at the output of the desynchronizer within predetermined maximum values. A further embodiment of the invention comprises means for reducing the open loop gain of the phase- locked loop for a predetermined period of time beginning from the time of occurrence of each pointer. Due to the reduction of the gain the closed- loop bandwidth is instantaneously limited to such a low value that the phase jitter induced by the pointer justification is removed adequately.

According to still another aspect of the invention the arrangement also performs the compensa¬ tion of phase discontinuities induced by bit justi¬ fication. In one embodiment of the invention, this is carried out by summing to the phase-locked loop a compensation pulse timed to coincide with each bit justification and similar to but shorter than the compensation pulse used in pointer justification.

Brief Description of the Drawings

The invention will be described more closely in the following by means of illustrating embodiments with reference to the attached drawings, in which

Figure 1 illustrates the transfer frame STM-1 of the SDH system;

Figures 2 and 3 illustrate a phase discontinu- ity occurring in the input of a prior art desynchron¬ izer and phase jitter present in the output, respectively, when the bandwidth of the phase-locked loop is about 2 Hz;

Figure 4 shows the schematic diagram of a desynchronizer according to the invention;

Figures 5 and 6 are signal diagrams illustrat¬ ing a phase discontinuity at the input of the de¬ synchronizer of Figure 4 and a corresponding phase jitter at the output of the desynchronizer; and Figure 7 is a schematic diagram illustrating two alternative ways of connecting the compensation signal to the phase-locked loop.

Detailed Description of the Invention In the following the invention will be de¬ scribed in connection with signals complying with the synchronous digital hierarchy SDH defined in the CCITT recommendations G.707, G.708 and G.709, but it can also be applied to other similar digital signals employing the justification technique, such as the synchronous optical network SONET.

The frame structure STM-1 of the SDH system, the framing and the pointer and bit justifications were described above with reference to Figure 1. In addition, the above-mentioned CCITT recommendations, the above-mentioned article by Ralph Urbansky, and the patent applications FI-914746 and AU-B-34639/89 are referred to. The SONET system is described e.g. in To Know Your Sonet , Know Your VTs by Stephen Fleming, TE&M, June 15, 1989, p. 62 to 75.

Figure 4 shows a desynchronizer according to the invention. A digital serial synchronous signal, such as an SDH signal consisting of STM-1 frames, is received at the input of a buffer memory 1, from where it is written byte by byte in accordance with addresses generated by a write address counter 2 to the buffer memory 1, and further read byte by byte in accordance with addresses generated by a read address counter 3 out of the buffer 1 so that a digital serial output signal DATA OUT with a desired trans¬ mission rate, e.g. 140 Mbit/s, is obtained from the desynchronizer. The write address counter 2 generates write addresses in synchronization with a write clock CLK1. Correspondingly, the read address counter 3 generates read addresses in synchronization with a read clock CLK2. The read clock CLK2 is phase-locked to the write clock CLK1 by a phase-locked loop (PLL) comprising a phase detector, a loop filter and a voltage-controlled oscillator. Signals CLK1/N and CLK2/N proportional to the write and read clocks are applied to the phase detector 4 from the counters 2 and 3, where N is a divisor dimensioned in accordance with the length of the buffer and the active range of the phase detector. The phase detector 4 produces a voltage signal V_: proportional to the phase difference between the signals CLK1/N and CLK2/N, and this volt¬ age signal is applied through a resistor R3 to an operational amplifier Al. The operational amplifier Al with associated resistors R3, R5, R6, R7, C3 and condenser C4 forms a loop filter which determines the loop gain of the phase-locked loop. The loop gain is selected so that an appropriate bandwidth is obtained. The operational amplifier Al generates a control voltage V₃ applied to the control input of the voltage-controlled oscillator 5 so as to determine the frequency of the read clock CLK2 generated by the oscillator 5. The phase-locked loop tends to adjust the frequency of the read clock CLK2 so that the phase difference between the clocks CLK1 and CLK2 is sufficiently small. A desynchronizer circuit of this type and different variations thereof are well-known to one skilled in the art.

The phase-locked loop (PLL) of the desynchron¬ izer shown in Figure 4, however, is not as such able to sufficiently suppress phase discontinuities, called pointer justifications herein, induced by the pointer justifications occurring in the incoming digital signal DATA IN. As mentioned above in con¬ nection with Figures 2 and 3, the pointer jitter in the output of the desynchronizer can be suppressed satisfactorily by limiting the bandwidth of the PLL but the speed and reliability of the locking of the PLL are deteriorated at the same time.

For this purpose the desynchronizer comprises a suppression circuit according to the invention, which positively controls the PLL in synchronization with the time of occurrence of each pointer justification so that the PLL limits the maximum amplitude of the phase jitter induced by said pointer justification, in the output signal of the desynchronizer. The digital section of the desynchronizer produces signals indicating the times of occurrence and directions of the pointer justifications for its internal use, and these signals can also be utilized in the control of the compensation connection accord¬ ing to the invention.

Figure 4 shows the preferred embodiment of the invention, in which the CMOS logic of the desynchron¬ izer generates a three-level compensation pulse volt- age V₄ in which the front edges of the pulses coincide with the pointer justifications. In the preferred embodiment of the invention, the positive pulse of the voltage V₄ corresponds to the positive pointer justification and the negative pulse corresponds to the negative pointer justification. The pulse voltage V₄ is integrated by an AC-coupled integrator com¬ prising an operational amplifier A2 with associated external components Rl, R2, Cl and C2. The integrator A2 integrates and inverts each pulse of the voltage V₄, thus forming an exponential pulse having a rapidly rising front edge timed to coincide with the time of occurrence of the pointer justification but opposite in direction in relation to it, and a slowly exponen¬ tially falling back edge. The output voltage V₂ of the integrator is summed by a resistor R4 with a voltage V_x at the input of the lowpass filter Al .

In the case of Figure 4, the voltage V₂ can also be applied to some other point in the phase-locked loop, such as the control voltage V₃ of the VCO, as shown by the broken line 6. In such a case, however, the compensation has to be done so as to limit the rate of change of the voltage V₃ over a predetermined period of time. In other words, the shape of the pulse V₂ has to be adapted to the output voltage of the filter Al at each specific point of addition.

The timing diagrams of Figures 5 and 6 illustrate the effect of the jitter compensation ac¬ cording to the invention on the desynchronizer of Figure 4. Figure 5 illustrates the phase jitter in the input signal DATA IN, in which a phase discon¬ tinuity of 24 time intervals (UI) induced by a positive pointer justification occurs at a time instant T = 50 s. This causes a phase difference to occur between the clock signals CLK1 and CLK2 and a corresponding change in the voltage V.. The same pointer justification causes a concurrent positive pulse to occur in the voltage V₄, which is integrated and added to the input of the filter Al as a voltage pulse V₂ opposite in direction in relation to the change of the voltage V-, so that the voltage pulse limits the maximum amplitude of the change of the control voltage V₃ of the oscillator means 5 caused by said pointer justification and thus also the jitter amplitude in the output signal of the desynchronizer measured through a measuring filter specified by the CCITT, as illustrated in the simulation of Figure 6. In Figure 6, the maximum amplitude of the phase jitter at the output at the time of occurrence of the pointer justification is clearly lower than e.g. in the case of Figure 3. In addition, the long exponen- tially falling back edge of the compensation pulse V₂ "stretches" the phase jitter over a long period of time. At the time instant T = 400 ms, there occurs in Figure 5 a phase discontinuity of opposite direction induced by a negative pointer justification and caus¬ ing voltages otherwise similar to the above-described voltages but opposite in direction to occur in the circuit of Figure 4. In Figure 6, this second pointer justification also occurs as phase jitter of opposite direction. In the example of Figures 4 to 6, the rate of the desynchronizer is 140 Mbit/s, the bandwidth of the phase lock is about 10 Hz and the pulse length of the voltage V₄ is 250 ms. This corresponds to two frame lengths and one half of the smallest possible interval between pointers (4 STM-1 transfer frames). The AC coupling of the integrator A2 is accomplished by a serial capacitor C2 in order that the dynamic range of the data buffer 1 would not be exceeded due to a plurality of successive pointers (for instance, one of the elements of the SDH network utilizes a local standby clock and thereby produces tens of pointer justifications per second). The time constant of the AC coupling also shortens the total time constant to some extent. The justification frequency in bit justifica¬ tion may represent the worst possible jitter fre¬ quency passing through the phase-locked loop, but as the duration of the phase discontinuities in bit justification is only one time interval, the low phase jitter induced by them has been insignificant as compared with the pointer jitter. In the compen¬ sation circuit according to the invention, the pointer jitter is suppressed, and so the jitter caused by bit justification may also become problem- atic. The circuit of Figures 4 and 6 may also be used for compensating the jitter induced by bit justifica¬ tion. The CMOS logic would thereby provide not only pointer compensation pulses corresponding to the pointer justifications but also bit compensation pulses timed to coincide with bit justifications and having a duration precisely 1/8 or 1/24 of the pointer compensation pulses ( 8-bit or 24-bit pointer justification) .

Figure 7 shows another embodiment of the inven- tion, in which the phase-locked loop contains a clamping circuit positioned between the amplifier Al and the voltage-controlled oscillator 5. The clamping circuit is controlled by the voltage V₄ so as to limit the control voltage V₃ between predetermined limit values for a predetermined period of time beginning from the time of occurrence of each pointer justification.

Alternatively, the open loop gain of the phase- locked loop can be decreased for a predetermined period of time beginning from the time of occurrence of each pointer justification. The block 71 in Figure 7 may thereby be an amplifier or an attenuator the gain of which is adjusted by the voltage V₄ in syn¬ chronization with the occurrence of pointer justifications.

A drawback of the two last-mentioned embodi¬ ments is that they interfere with the removal of bit justification jitter the more the higher the number of pointer justifications. Therefore the operation of the circuits 71 and 81 would obviously be prevented during high-frequency pointer sequences. This problem, however, is avoided in the compensation con¬ nection according to Figure 4, which allows the clamping circuit to operate normally all the time. The figures and the description related to them are only intended to illustrate the present inven¬ tion. In its details, the arrangement according to the invention may vary within the scope of the attached claims.

Claims

Claims:

1. Arrangement for suppressing pointer jus¬ tification jitter in a desynchronizer in a digital transmission system, the desynchronizer comprising a data buffer means (1 ) ; a data buffer write address counter (2) controlled by a write clock (CLK1 ) ; a data buffer read address counter (3) controlled by a read clock (CLK2); and a phase-locked loop comprising a phase comparator means (4), a loop filter means (Al) and a voltage-controlled oscillator means (5) for adjusting said read clock on the basis of the phase difference between the read and write clocks, c h a r a c t e r i z e d in that the arrangement comprises means (A2, 71, 81) for positively con¬ trolling the phase-locked loop so as to limit, in synchronization with the time of occurrence of each pointer justification, the maximum amplitude of the phase jitter induced in an output signal (DATA OUT) of the desynchronizer by said pointer justification.

2. Arrangement according to claim 1, c h a r ¬ a c t e r i z e d in that said means (A2, 71, 81) positively control the phase-locked loop in synchron¬ ization with the time of occurrence of each pointer justification so as to limit the maximum rate of change of a control voltage (V₃) of the oscillator means (5) induced by said pointer justification.

3. Arrangement according to claim 1 or 2, c h a r a c t e r i z e d in that the compensation means comprise means for generating a compensation pulse signal (V₄, V₂) in which the times of occurrence of the pulses coincide with the times of occurrence of the pointer justifications.

4. Arrangement according to claim 1 or 2, c h a r a c t e r i z e d in that the compensation means further comprise means for generating another compensation pulse signal in which the times of occurrence of the pulses coincide with the times of occurrence of phase discontinuities induced by the bit justifications.

5. Arrangement according to claim 2, 3 or 4, c h a r a c t e r i z e d in that the pulses of the compensation pulse signal (V₂) are exponential pulses having a rapidly rising front edge timed to coincide with the pointer justification but being opposite in direction in relation to it, and a slowly falling back edge.

6. Arrangement according to claim 5, c h a r¬ a c t e r i z e d in that the compensation means further comprise an AC connected integrator means (A2) having an input signal which is a rectangular compensation pulse signal (V₄) and an output signal which is an exponential compensation pulse signal (V₂) controlling the phase-locked loop.

7. Arrangement according to any of claims 2 to

6, c h a r a c t e r i z e d in that the arrangement comprises means for summing the compensation pulse signal (V₂) to the input signal (V-^ of the loop filter.

8. Arrangement according to any of claims 2 to

6, c h a r a c t e r i z e d in that the arrangement comprises means for summing the compensation voltage (V₂) to the control signal (V₃) of the voltage- controlled oscillator.

9. Arrangement according to any of claims 1 to

4, c h a r a c t e r i z e d in that the arrangement comprises means (71) for limiting the amplitude of the control signal (V₃) of the voltage-controlled oscillator for a predetermined period of time beginn- ing from the time of occurrence of each pointer.

10. Arrangement according to any of claims 1 to 4, c h a r a c t e r i z e d in that the arrangement comprises means (81) for decreasing the open loop gain of the phase-locked loop for a predetermined period of time beginning from the time of occurrence of each pointer.