WO1991003871A1 - Fully integrated digital fm discriminator - Google Patents
Fully integrated digital fm discriminator Download PDFInfo
- Publication number
- WO1991003871A1 WO1991003871A1 PCT/US1990/004305 US9004305W WO9103871A1 WO 1991003871 A1 WO1991003871 A1 WO 1991003871A1 US 9004305 W US9004305 W US 9004305W WO 9103871 A1 WO9103871 A1 WO 9103871A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- phase
- signal
- information signal
- discriminator
- digital
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D1/00—Demodulation of amplitude-modulated oscillations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
- H03K9/06—Demodulating pulses which have been modulated with a continuously-variable signal of frequency- or rate-modulated pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
- H03D3/009—Compensating quadrature phase or amplitude imbalances
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
- H04L27/156—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width
- H04L27/1566—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width using synchronous sampling
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/006—Demodulation of angle-, frequency- or phase- modulated oscillations by sampling the oscillations and further processing the samples, e.g. by computing techniques
Definitions
- This invention relates generally to radio frequency data communication signal receivers, and more particularly to radio frequency processing and discrimination principles.
- DSPs Digital signal processors
- DSPs began to impact the industrial and communication areas in the 1970's and 1980's due to their improved sensitivity and the characteristic of generally widespread compatibility of digital devices.
- DSPs are noted for their linearity in conversion of information signals, general imperviousness to age and temperature, and relative independence of sampling rates with concomitant reduction of chip area requirements and associated time demands pursuant thereto.
- DSPs often contain sophisticated programmable circuitry that necessitates significant microprocessor or microcomputer memory; this aspect often is costly.
- the programmable aspect of DSPs is very power-consuming.
- an FM discriminator is provided as a single integrated circuit. Unlike DSP-based discriminator embodiments, the integrated circuit of the invention is substantially non-programmable.
- This invention takes advantage of the fact that total integration of a digital frequency discriminator provides numerous desirable performance characteristics, including lower current drain, substantially perfect linearity, and little age or temperature-induced drift. By careful selection of the number of bits and devices necessary for each signal processing step, chip area and current drain can be limited. At the same time, full integration of the elements of the discriminator allows implementation of a system with low power requirements, and because this fully integrated discriminator's use does not depend on the sampling rate of the information signals, it facilitates a highly flexible demodulation system.
- Figure 1 is a block diagram of a digital FM discriminator according to the invention.
- FIG. 2 is a more detailed block diagram of the discriminator depicted in Figure 1;
- Figure 3 is a block diagram of the phase correction factor determining unit.
- FIG 4 is a set of phase analysis relationships. Best Mode For Carrying Out The Invention Figure 1 generally depicts a digital FM discriminator (10).
- a frequency modulated information signal (12) is transmitted to an input (14) that digitizes the signal, yielding an in-phase (1) amplitude data signal and a quadrature (Q) amplitude data signal.
- the input (14) is connected to a phase determining unit (15), which consists of a signal processor (16), a coarse phase determining unit (18), and a phase correction factor determining unit (20), all of which utilize I and Q.
- the signal processor (16) compares unsigned values of I and Q to obtain an equivalent phase position.
- the coarse phase determining unit (18) determines a unit multiple of ⁇ f /2 for the equivalent phase position obtained.
- the phase correction factor determining unit (20) provides division information as to I and Q, which is converted to a fine phase correction factor less than or equal to IT /4 radians.
- the output of the phase determining unit (15) connects to an adder (22), which substantially reproduces the actual phase of the received frequency modulated information signal.
- the adder (22) is connected to a differentiator circuit (24) which converts the phase information to a demodulated information signal (26).
- FIG. 2 depicts the over-all discriminator circuit (10) in greater detail.
- the frequency modulated information signal (12) is transmitted to the input (14) which digitizes the information signal, producing at least one matched pair (I, Q) of data words.
- the matched pairs (I,Q) of data words are stored in data registers (118, 120).
- the data registers (118, 120) are connected to a subtractor (122), a set of gates (124), a coarse phase determining unit (108); and a phase correction factor determining unit (20).
- the matched pairs (I,Q) of data words are compared in the subtractor (122) to obtain an equivalent phase position.
- the coarse phase determining unit (108) is connected to an adder (22) and utilizes a coarse phase logic unit (126) to compare the matched pairs (I,Q) of data words with the equivalent phase position determined by the subtractor (122), obtaining a coarse phase for each matched pair, and ultimately storing this coarse phase in the coarse phase data register (128) (a register of relatively small size, one workable size being 2 bits).
- a set of gates (124) is connected to the phase correction factor determining unit (20). This set of gates (124) selects a division operation as between each matched set of I and Q.
- the phase correction factor determining unit (20) is connected to the adder (22), and obtains the division information selected, causing the division information to be converted to a fine phase correction factor, which is stored in a suitably sized fine phase ROM register (212) (one workable size being 5 bits).
- the adder (22) combines the coarse phase and the fine phase correction factor expeditiously due to the small field sizes. The limited field sizes also produce significantly smaller current drains and chip sizes than current DSP units.
- the adder (22) is connected to a differentiator circuit (24).
- the differentiator circuit (24) is connected to an output (26), and provides a demodulated information signal output.
- Figure 3 shows the phase correction factor determining unit (20) in greater detail.
- Gated outputs A (202) and B (204) from the signal processor (16) are inputs to a divider circuit (206).
- Gated input A (202) connects to a divisor register (214) and gated input B (204) connects to an accummulator register (216).
- Both the divisor register (214) and the accummulator- MQ register (216, 218) are limited in size to reduce current drain (16 bits being one of the workable bit sizes for the registers).
- the divisor register (214) and accummulator register (216) connect to an add/subtract unit (220) that circulates its data computation result back to the accummulator register (216) and also to the MQ register (218).
- the MQ register (218) stores an accumulated quotient value for each data pair calculation.
- Data signals C (222) and D 224) represent the matched pairs of I and Q, respectively, which are transmitted to an exclusive-or unit (226).
- the quotient inverter (208) is connected do a fine phase data address register (210) which is connected to a suitably sized fine phase ROM (212) (a 32 x 5 fine phase ROM being one of the workable sizes).
- the fine phase ROM (212) generates the fine phase value in radians and connects to the adder (22).
- Figure 4 is a set of phase analysis relationships setting forth phase computation information with respect to the equivalent phase position, including the first set of phase analysis relationships listing available sign bits of the in-phase amplitude data signal (I), the quadrature amplitude data signal (Q), and the absolute value of the difference between the two data signals pursuant to the equivalent phase position; the second set of phase analysis relationships listing the division operation and quotient inversion characteristics of each equivalent phase position; and the third set of phase analysis relationships listing a coarse phase value and sign for a fine phase correction factor for each equivalent phase position. Accordingly what is claimed is:
Abstract
A single substantially non-programmable fully integrated circuit for a digital frequency modulated discriminator is provided whereby frequency variations of a digitized frequency modulated information signal (12) are linearly converted to amplitude variations. Matched pairs of data words from the digitized information signal are used to obtain a phase octant, one of eight equal sectors of the 360 degree spectrum. Further manipulations of the pairs of data words provide a coarse phase measurement (18) being some integral multiple of $g(p)/2, and a fine phase correction factor (20) less than or equal to $g(p)/4 radians. The coarse phase measurement is combined with the fine phase correction factor (22). The sum is differentiated (24) and demodulated, yielding the original information signal (26).
Description
FULLY INTEGRATED DIGITAL FM DISCRIMINATOR
Background of the Invention
This invention relates generally to radio frequency data communication signal receivers, and more particularly to radio frequency processing and discrimination principles.
Analog implementations of signal processing have long been used in radio receivers. Although analog integrated circuits are often referred to as linear, such circuits are completely dependent on a variety of manufacturing technologies which generate a product, often producing outputs which are only analogous or similar to the input signals. Digital signal processors (DSPs) began to impact the industrial and communication areas in the 1970's and 1980's due to their improved sensitivity and the characteristic of generally widespread compatibility of digital devices. DSPs are noted for their linearity in conversion of information signals, general imperviousness to age and temperature, and relative independence of sampling rates with concomitant reduction of chip area requirements and associated time demands pursuant thereto. DSPs, however, often contain sophisticated programmable circuitry that necessitates significant microprocessor or microcomputer memory; this aspect often is costly. In addition, the programmable aspect of DSPs is very power-consuming.
Although digital signal processing technology has been combined with analog implementation to achieve a result for discriminators which far improves the analog system alone, it is desirable to have the advantages of digital discrimination without the associated present costs.
Summary of the Invention
The need for significant performance improvement is substantially met by the device and method of the present invention. Pursuant to this invention, an FM discriminator is provided as a single integrated circuit. Unlike DSP-based discriminator embodiments, the integrated circuit of the invention is substantially non-programmable.
This invention takes advantage of the fact that total integration of a digital frequency discriminator provides numerous desirable performance characteristics, including lower current drain, substantially perfect linearity, and little age or temperature-induced drift. By careful selection of the number of bits and devices necessary for each signal processing step, chip area and current drain can be limited. At the same time, full integration of the elements of the discriminator allows implementation of a system with low power requirements, and because this fully integrated discriminator's use does not depend on the sampling rate of the information signals, it facilitates a highly flexible demodulation system.
Brief Description Of The Pra-flings
Figure 1 is a block diagram of a digital FM discriminator according to the invention;
Figure 2 is a more detailed block diagram of the discriminator depicted in Figure 1;
Figure 3 is a block diagram of the phase correction factor determining unit; and
Figure 4 is a set of phase analysis relationships. Best Mode For Carrying Out The Invention Figure 1 generally depicts a digital FM discriminator (10).
A frequency modulated information signal (12) is transmitted to an input (14) that digitizes the signal, yielding an in-phase (1) amplitude data signal and a quadrature (Q) amplitude data signal. The input (14) is connected to a phase determining unit
(15), which consists of a signal processor (16), a coarse phase determining unit (18), and a phase correction factor determining unit (20), all of which utilize I and Q. The signal processor (16) compares unsigned values of I and Q to obtain an equivalent phase position. The coarse phase determining unit (18) determines a unit multiple of τf /2 for the equivalent phase position obtained. The phase correction factor determining unit (20) provides division information as to I and Q, which is converted to a fine phase correction factor less than or equal to IT /4 radians. The output of the phase determining unit (15) connects to an adder (22), which substantially reproduces the actual phase of the received frequency modulated information signal. The adder (22) is connected to a differentiator circuit (24) which converts the phase information to a demodulated information signal (26).
Figure 2 depicts the over-all discriminator circuit (10) in greater detail. The frequency modulated information signal (12) is transmitted to the input (14) which digitizes the information signal, producing at least one matched pair (I, Q) of data words. The matched pairs (I,Q) of data words are stored in data registers (118, 120). The data registers (118, 120) are connected to a subtractor (122), a set of gates (124), a coarse phase determining unit (108); and a phase correction factor determining unit (20). The matched pairs (I,Q) of data words are compared in the subtractor (122) to obtain an equivalent phase position. The coarse phase determining unit (108) is connected to an adder (22) and utilizes a coarse phase logic unit (126) to compare the matched pairs (I,Q) of data words with the equivalent phase position determined by the subtractor (122), obtaining a coarse phase for each matched pair, and ultimately storing this coarse phase in the coarse phase data register (128) (a register of relatively small size, one workable size being 2 bits). A set of gates (124) is connected to the phase correction factor determining unit (20).
This set of gates (124) selects a division operation as between each matched set of I and Q. The phase correction factor determining unit (20) is connected to the adder (22), and obtains the division information selected, causing the division information to be converted to a fine phase correction factor, which is stored in a suitably sized fine phase ROM register (212) (one workable size being 5 bits). The adder (22) combines the coarse phase and the fine phase correction factor expeditiously due to the small field sizes. The limited field sizes also produce significantly smaller current drains and chip sizes than current DSP units. The adder (22) is connected to a differentiator circuit (24). The differentiator circuit (24) is connected to an output (26), and provides a demodulated information signal output. Figure 3 shows the phase correction factor determining unit (20) in greater detail. Gated outputs A (202) and B (204) from the signal processor (16) are inputs to a divider circuit (206). Gated input A (202) connects to a divisor register (214) and gated input B (204) connects to an accummulator register (216). Both the divisor register (214) and the accummulator- MQ register (216, 218) are limited in size to reduce current drain (16 bits being one of the workable bit sizes for the registers). The divisor register (214) and accummulator register (216) connect to an add/subtract unit (220) that circulates its data computation result back to the accummulator register (216) and also to the MQ register (218). The MQ register (218) stores an accumulated quotient value for each data pair calculation. Data signals C (222) and D 224) represent the matched pairs of I and Q, respectively, which are transmitted to an exclusive-or unit (226). The MQ register (218) output, together with an invert control signal computed by the exclusive-or unit (226), feed into the quotient inverter (208) which inverts the quotient according to certain predetermined characteristics set forth in the second set of
phase analysis relationships of Figure 4. The quotient inverter (208) is connected do a fine phase data address register (210) which is connected to a suitably sized fine phase ROM (212) (a 32 x 5 fine phase ROM being one of the workable sizes). The fine phase ROM (212) generates the fine phase value in radians and connects to the adder (22).
Figure 4 is a set of phase analysis relationships setting forth phase computation information with respect to the equivalent phase position, including the first set of phase analysis relationships listing available sign bits of the in-phase amplitude data signal (I), the quadrature amplitude data signal (Q), and the absolute value of the difference between the two data signals pursuant to the equivalent phase position; the second set of phase analysis relationships listing the division operation and quotient inversion characteristics of each equivalent phase position; and the third set of phase analysis relationships listing a coarse phase value and sign for a fine phase correction factor for each equivalent phase position. Accordingly what is claimed is:
Claims
1. A digital FM discriminator comprising:
A) a first means for receiving and processing a non- quantized signal that includes a frequency modulated information signal having a phase with an equivalent phase position to determine a coarse phase value and a fine phase value;
B) a second means responsive to the first means for outputing a demodulated information signal; and wherein the first means and second means are formed integrally in a common substantially non-programmable integrated circuit.
2. A digital FM discriminator comprising:
A) input means for receiving a frequency modulated information signal sample having a phase;
B) signal processing means for processing the frequency modulated information signal sample from the input to obtain an equivalent phase position determination;
Q coarse phase determining means operably coupled to the signal processing means, for providing a coarse phase component from the equivalent phase position for the sample; D) fine phase determining means operably coupled to the signal processing means, for providing a fine phase correction factor from the equivalent phase position for the sample;
E) phase recovery means that receives the coarse phase component and the fine phase correction factor for providing a recovered phase value for the sample; and
F) computation means for converting the recovered phase value to a demodulated information signal sample; wherein the input means, signal processing means, coarse phase determining means, fine phase determining means, phase recovery means and computation means are all formed integrally in a common substantially non-programmable integrated circuit.
3. A digital FM discriminator as described in claim 2 wherein the input means comprises: sampling means for transforming the frequency modulated information signal sample to at least one set of (I,Q) data word pairs; wherein the input means, sampling means, signal processing means, coarse phase determining means, fine phase determining means, and phase recovery means are all formed integrally in a common substantially non-programmable integrated circuit.
4. A digital FM discriminator as described in claim 3 wherein the signal processing means comprises:
A) storage means for tabulating at least some of the set of (I,Q) data word pairs; B) computation means for obtaining difference information as between the data word pairs, absent their respective sign bits; and
Q gating means for selecting from division operations Q/I and I/Q.
5. A digital FM discriminator as described in claim 3 wherein the coarse phase determining means comprises:
A) phase magnitude determining means for selecting a unit multiple of τf /2 radians; and
B) storage means for tabulating said unit multiple of *rt 12 radians.
6. A digital FM discriminator as described in claim 3 wherein the fine phase determining means comprises:
A) first storage means for storing a value;
B) second storage means for storing a second value, including subsequent changes due to an aggregation of values determined by subsequent computations of at least one sum/difference information; computation means for obtaining at least one sum/difference information as between the first storage means and the second storage means;
D) third storage means for storing a final aggregation of values determined by computations of sum/difference information;
E) selection means for determining necessity of inversion of the final aggregation of values;
F) manipulation means for inverting the final aggregation of values to obtain an intermediate value; and
G) conversion means for changing the intermediate value to radians.
7. A method for discriminating a digital frequency modulated signal, wherein a substantially non-programmable circuit is essentially integrated, comprising the steps of:
A) receiving a signal for processing that includes a frequency modulated information signal; and
B) having a phase with an equivalent phase position to determine a coarse phase value and a fine phase value utilizing a quotient of the coarse phase value and the fine phase value to output a demodulated information signal.
8. A method for discriminating a digital frequency modulated signal, wherein a substantially non-programmable circuit is essentially integrated, comprising the steps of:
A) receiving a signal that includes a frequency modulated information signal;
B) determining an equivalent phase position for the frequency modulated information signal;
Q determining a coarse phase component from the equivalent phase position; D) determining a fine phase correction factor from the equivalent phase position;
E) providing a recovered phase value from combining the coarse phase component and the fine phase correction factor; and F) converting the recovered phase value to a demodulated information signal sample.
9. A digital FM discriminator comprising:
A) a first means for receiving and processing a non- scaled signal that includes a frequency modulated information signal having a phase with an equivalent phase position to determine a coarse phase value and a fine phase value; and
B) a second means responsive to the first means for outputting a demodulated information signal; and wherein the first means and second means are formed integrally in a common substantially non-programmable integrated circuit.
10. A digital FM discriminator as described in claim 9 wherein the non-scaled signal in (A) is also non-quantized.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910700416A KR950005160B1 (en) | 1989-08-31 | 1990-08-02 | Integrated digital fm discriminator |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US402,118 | 1989-08-31 | ||
US07/402,118 US4985684A (en) | 1989-08-31 | 1989-08-31 | Fully integrated digital FM discriminator |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1991003871A1 true WO1991003871A1 (en) | 1991-03-21 |
Family
ID=23590600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1990/004305 WO1991003871A1 (en) | 1989-08-31 | 1990-08-02 | Fully integrated digital fm discriminator |
Country Status (5)
Country | Link |
---|---|
US (1) | US4985684A (en) |
EP (1) | EP0450001A4 (en) |
JP (1) | JPH04501646A (en) |
KR (1) | KR950005160B1 (en) |
WO (1) | WO1991003871A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996020540A2 (en) * | 1994-12-23 | 1996-07-04 | Qualcomm Incorporated | Dual-mode fm/cdma communication system |
CN1063890C (en) * | 1994-01-27 | 2001-03-28 | 艾利森·Ge·流动通讯有限公司 | Method and system for demodulation of downlink CDMA signals |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5008900A (en) * | 1989-08-14 | 1991-04-16 | International Mobile Machines Corporation | Subscriber unit for wireless digital subscriber communication system |
US5146473A (en) * | 1989-08-14 | 1992-09-08 | International Mobile Machines Corporation | Subscriber unit for wireless digital subscriber communication system |
US5220275A (en) * | 1991-07-26 | 1993-06-15 | Ericsson Ge Mobile Communication Holding, Inc. | Accumulator phase digitizer |
GB2286950B (en) * | 1994-02-22 | 1998-06-17 | Roke Manor Research | A direct conversion receiver |
US5982821A (en) * | 1996-01-16 | 1999-11-09 | L-3 Communications | Frequency discriminator and method and receiver incorporating same |
GB2313262A (en) * | 1996-05-18 | 1997-11-19 | Northern Telecom Ltd | A Frequency Selective Noise Canceller |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4675882A (en) * | 1985-09-10 | 1987-06-23 | Motorola, Inc. | FM demodulator |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS587859B2 (en) * | 1977-08-30 | 1983-02-12 | 酒井 一義 | Elliptical motion mechanism |
JPH0777329B2 (en) * | 1986-10-02 | 1995-08-16 | 松下電器産業株式会社 | FM signal demodulator |
JPS6394707A (en) * | 1986-10-09 | 1988-04-25 | Toshiba Corp | Arc tangent type fm demodulator |
JPS63285771A (en) * | 1987-05-18 | 1988-11-22 | Pioneer Electronic Corp | Tan type fm modulator |
-
1989
- 1989-08-31 US US07/402,118 patent/US4985684A/en not_active Expired - Lifetime
-
1990
- 1990-08-02 EP EP19900911573 patent/EP0450001A4/en not_active Withdrawn
- 1990-08-02 WO PCT/US1990/004305 patent/WO1991003871A1/en not_active Application Discontinuation
- 1990-08-02 JP JP2511332A patent/JPH04501646A/en active Pending
- 1990-08-02 KR KR1019910700416A patent/KR950005160B1/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4675882A (en) * | 1985-09-10 | 1987-06-23 | Motorola, Inc. | FM demodulator |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1063890C (en) * | 1994-01-27 | 2001-03-28 | 艾利森·Ge·流动通讯有限公司 | Method and system for demodulation of downlink CDMA signals |
WO1996020540A2 (en) * | 1994-12-23 | 1996-07-04 | Qualcomm Incorporated | Dual-mode fm/cdma communication system |
WO1996020540A3 (en) * | 1994-12-23 | 1996-09-06 | Qualcomm Inc | Dual-mode fm/cdma communication system |
US5757858A (en) * | 1994-12-23 | 1998-05-26 | Qualcomm Incorporated | Dual-mode digital FM communication system |
Also Published As
Publication number | Publication date |
---|---|
JPH04501646A (en) | 1992-03-19 |
EP0450001A4 (en) | 1992-01-22 |
US4985684A (en) | 1991-01-15 |
KR950005160B1 (en) | 1995-05-19 |
KR920702074A (en) | 1992-08-12 |
EP0450001A1 (en) | 1991-10-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5052050A (en) | Direct conversion FM receiver | |
US4985684A (en) | Fully integrated digital FM discriminator | |
US5844943A (en) | Method and converter for converting rectangular signals to phase signals | |
US5668749A (en) | Circuit for performing arithmetic operations in a demodulator | |
US4099245A (en) | Transducer signalling apparatus | |
US4862098A (en) | Continuous-wave-modulation detectors using prediction methods | |
US5521559A (en) | Signal oscillator, FM modulation circuit using the same, and FM modulation method | |
US5517689A (en) | Phase detecting method and phase detector and FM receiver using phase detecting method | |
Abramovitch | Low latency demodulation for atomic force microscopes, Part II: Efficient calculation of magnitude and phase | |
US4567442A (en) | Method and apparatus for demodulating time-discrete frequency-modulated signals | |
US5079513A (en) | Demodulator and radio receiver having such a demodulator | |
JPH01151307A (en) | Digital fm demodulator | |
US6526110B1 (en) | Embedded RAM based digital signal processor | |
TWI376633B (en) | Method of cordic computing vector angle and electronic apparatus using the same | |
US4584652A (en) | Apparatus and method for determining in-phase and quadrature-phase components | |
US4736334A (en) | Circuit for calculating the value of a complex digital variable | |
JP2579321B2 (en) | Binary processing unit | |
US20020101939A1 (en) | Fixed-point DSP implementation of FM demodulation and decoding | |
Palomaki et al. | Methods to improve the performance of quadrature phase-to-amplitude conversion based on Taylor series approximation | |
US5889822A (en) | Signal processor with reduced complexity, and receiver comprising such a signal processor | |
US5039987A (en) | Circuit for converting a phase signal to an amplitude signal | |
JPS5836868B2 (en) | Signal vector determination circuit for 8-phase phase modulation | |
JP3092377B2 (en) | Data receiving device | |
JPH07212428A (en) | Circuit for restoring carrier wave by judgement with phase error sensor | |
JP2003018228A (en) | Symbol synchronizing circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1990911573 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1990911573 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1990911573 Country of ref document: EP |