WO1991003066A1 - Self-aligned gate process for fabricating field emitter arrays - Google Patents
Self-aligned gate process for fabricating field emitter arrays Download PDFInfo
- Publication number
- WO1991003066A1 WO1991003066A1 PCT/US1990/002184 US9002184W WO9103066A1 WO 1991003066 A1 WO1991003066 A1 WO 1991003066A1 US 9002184 W US9002184 W US 9002184W WO 9103066 A1 WO9103066 A1 WO 9103066A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- photoresist
- field emitter
- oxide
- depositing
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
- H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
Definitions
- the present invention relates generally to field emitter arrays, and more particularly to a process for fabricating self-aligned micron-sized field emitter arrays.
- Field emitter arrays typically comprise a metal/insulator/metal film sandwich with a cellular array of holes through the upper metal and insulator layers, leaving the edges of the upper metal layer (which serves as an accelerator electrode) effectively exposed to the upper surface of the lower metal layer (which serves as an emitter electrode) .
- a number of conically-shaped electron emitter elements are mounted on the lower metal layer and extend upwardly therefrom such that their respective tips are located in respective holes in the upper metal layer. If appropriate voltages are applied between the emitter electrode, accelerator electrode, and an anode located above the accelerator electrode, electrons are caused to flow from the respective cone tips to the anode. Further details regarding these devices may be found in the papers by C. A. Spindt, "A Thin-Film Field-Emission Cathode", Journal of Applied Physics. Vol. 39, No. 7, June 1986, pages 3504-3505, C. A. Spindt et al., “Physical Properties of Thin-Film Field Emission Cathodes with Molybdenum Cones", Journal of Applied Physics. Vol.
- the present invention fabricates the arrays in accordance with the following process steps.
- Substantially conical field emitter elements are formed on a surface of a substrate, after which a layer of oxide is deposited on the substrate surface and over the field emitter elements.
- a layer of metal is then deposited over the layer of oxide to form a gate metal layer.
- a layer of photoresist is then deposited over the gate metal layer.
- the layer of photoresist is then plasma etched in an oxygen atmosphere to cause portions of the photoresist above respective field emitter elements to be removed and thereby provide self-aligned holes in the photoresist over each of the field emitter elements.
- the exposed gate metal layer above the field emitter elements is then etched using the layer of photoresist as a mask.
- the photoresist layer is removed, and the layer of oxide is etched to expose the field emitter elements.
- further processing may be performed to provide a second oxide layer and an anode metal layer in field emission triode devices.
- FIGS. 1 through 8 illustrate a preferred process of fabricating a field emitter array in accordance with the principles of the present invention.
- FIGS. 9 and 10 illustrate additional processing steps employed in fabricating a field emission triode.
- FIGS. 1 and 2 show side and top views, respectively, of a substrate 11 having field emitter elements 12 formed on a surface of the substrate.
- the substrate 11 and the field emitter elements 12 may be of polysilicon, for example.
- the substrate 11 is fabricated in a conventional manner to provide an array of emitter elements thereon, with FIG. 2 showing a typical field emitter array.
- the substrate 11 and the field emitter elements 12 have a metal layer 20 disposed thereover.
- This metal layer 20 may be of molybdenum, for example.
- the metal layer 20 is typically deposited over elements 12 and substrate 11 to a thickness of from about 250A to about 2000A, for example. It should be understood, however, that the metal layer 20 may be eliminated in some applications.
- a layer of oxide 13 is deposited over the surface of the substrate 11 and the field emitter elements 12 (or the metal layer 20 if it is employed) .
- the oxide layer 13 is typically formed using a chemical vapor deposition process.
- the oxide layer 13 is deposited to a thickness of from about 5000A to about 15000A, for example.
- the chromium layer may have a thickness of from about 300A to about lOOOA, while the gold layer may have a thickness of from about 2000A to about 5000A, for example.
- a layer of photoresist 15 is then deposited over the gate metal layer 14.
- the layer of photoresist 15 is typically deposited using a conventional spin-on procedure employing Hoechst AZ 1370 photoresist spun on at 4000 RPM for about 20 seconds, for example.
- the structure of FIG. 4 is then processed to cause portions of the layer of photoresist 15 above respective field emitter elements 12 to be removed, as shown in FIG. 5, and thereby expose respective portions of the gate metal layer 14 above respective tip regions of the field emitter elements 12. This may be accomplished by plasma etching the layer of photoresist 15 in an oxygen environment.
- the plasma etching operation may be carried out in a plasma discharge stripping and etching system Model No. PDS/PDE- 301 manufactured by LFE Corporation, Waltham,
- the aforementioned plasma discharge system may be initially evacuated to a pressure of about 0.1 torr, after which a regulated flow of oxygen gas may be passed through the system at a flow rate of about 240 cc per minute and at a pressure of about 3 torr before commencement of the plasma discharge.
- a plasma discharge is then established in the system for a predetermined time to achieve the desired photoresist removal.
- precisely-aligned openings 16 are formed directly over respective field emitter elements 12 of the array.
- the size of the openings 16 may be controlled by appropriately controlling process parameters, including time and power setting of the plasma discharge apparatus and/or the initial thickness of the layer of photoresist 15.
- the field emitter elements 12 that have been exposed via openings 16 in the preceding step are then etched by means of a conventional etching procedure, for example, using the layer of photoresist 15 as a mask.
- a mixture of water and potassium iodide may be employed for a time duration of from about 1 minute to about 5 minutes to etch the gold, for example, and potassium permanganate for about 7 seconds, and oxalic for about 7 seconds may be employed to etch the chromium, for example.
- the layer of photoresist 15 is then removed, and the layer of oxide 13 is etched using a conventional etching procedure using buffered hydrogen fluoride, for example, to expose the field emitter elements 12. This results in a self-aligned cathode structure as shown in FIG. 8.
- FIGS. 9 and 10 additional processing steps are illustrated that enable fabrication of a self-aligned anode structure above the field emission cathode structure fabricated pursuant to the process of FIGS. 1-8.
- a second layer of oxide 17 is deposited on top of the gate metal layer 14, after which an additional layer of metal 18, which may serve as an anode metal layer in the resultant device, is deposited over the second layer of oxide 17.
- FIG. 9 is processed in a manner described above with respect to FIGS. 4-8.
- a layer of photoresist is applied to the top surface of the anode metal layer 18 and is then plasma etched to remove portions of the layer of photoresist above the elements 12.
- the anode metal layer 18 is then etched using the layer of photoresist as a mask.
- the layer of photoresist is then removed, and the first and second oxide layers 13,17 are etched to expose the field emitter elements 12, resulting in the structure shown in FIG. 10.
- metal may be used instead of polysilicon to form the substrate and the emitter elements.
- dry etching- of the oxide and metal layers may be employed where anisotropic etching is critical.
- the gate metal layer may be comprised of metal alloys other than chromium and gold, such as by molybdenum, for example.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50750190A JPH04505073A (en) | 1989-08-14 | 1990-04-23 | Self-aligned gate method for manufacturing field emitter arrays |
EP90907546A EP0438544B1 (en) | 1989-08-14 | 1990-04-23 | Self-aligned gate process for fabricating field emitter arrays |
DE69016397T DE69016397D1 (en) | 1989-08-14 | 1990-04-23 | METHOD FOR PRODUCING A FIELD EMITTER ARRANGEMENT WITH AUTOMATIC GATE ADJUSTMENT. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US393,199 | 1989-08-14 | ||
US07/393,199 US4943343A (en) | 1989-08-14 | 1989-08-14 | Self-aligned gate process for fabricating field emitter arrays |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1991003066A1 true WO1991003066A1 (en) | 1991-03-07 |
Family
ID=23553689
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1990/002184 WO1991003066A1 (en) | 1989-08-14 | 1990-04-23 | Self-aligned gate process for fabricating field emitter arrays |
Country Status (6)
Country | Link |
---|---|
US (1) | US4943343A (en) |
EP (1) | EP0438544B1 (en) |
CA (1) | CA2034481C (en) |
DE (1) | DE69016397D1 (en) |
IL (1) | IL94199A0 (en) |
WO (1) | WO1991003066A1 (en) |
Cited By (3)
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EP0525764A2 (en) * | 1991-08-01 | 1993-02-03 | Texas Instruments Incorporated | Method of forming a vacuum micro-chamber for encapsulating a microelectronics device |
US5354714A (en) * | 1991-08-01 | 1994-10-11 | Texas Instruments Incorporated | Method of forming a vacuum micro-chamber for encapsulating a microelectronics device |
FR2709206A1 (en) * | 1993-06-14 | 1995-02-24 | Fujitsu Ltd | Cathode device having a small aperture and its method of manufacture |
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GB9101723D0 (en) * | 1991-01-25 | 1991-03-06 | Marconi Gec Ltd | Field emission devices |
US5312514A (en) * | 1991-11-07 | 1994-05-17 | Microelectronics And Computer Technology Corporation | Method of making a field emitter device using randomly located nuclei as an etch mask |
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US5266530A (en) * | 1991-11-08 | 1993-11-30 | Bell Communications Research, Inc. | Self-aligned gated electron field emitter |
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US5669801A (en) * | 1995-09-28 | 1997-09-23 | Texas Instruments Incorporated | Field emission device cathode and method of fabrication |
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-
1989
- 1989-08-14 US US07/393,199 patent/US4943343A/en not_active Expired - Lifetime
-
1990
- 1990-04-23 CA CA002034481A patent/CA2034481C/en not_active Expired - Fee Related
- 1990-04-23 EP EP90907546A patent/EP0438544B1/en not_active Expired - Lifetime
- 1990-04-23 WO PCT/US1990/002184 patent/WO1991003066A1/en active IP Right Grant
- 1990-04-23 DE DE69016397T patent/DE69016397D1/en not_active Expired - Lifetime
- 1990-04-25 IL IL94199A patent/IL94199A0/en not_active IP Right Cessation
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US4008412A (en) * | 1974-08-16 | 1977-02-15 | Hitachi, Ltd. | Thin-film field-emission electron source and a method for manufacturing the same |
EP0306173A1 (en) * | 1987-09-04 | 1989-03-08 | THE GENERAL ELECTRIC COMPANY, p.l.c. | Field emission devices |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0525764A2 (en) * | 1991-08-01 | 1993-02-03 | Texas Instruments Incorporated | Method of forming a vacuum micro-chamber for encapsulating a microelectronics device |
EP0525764A3 (en) * | 1991-08-01 | 1993-11-24 | Texas Instruments Inc | Method of forming a vacuum micro-chamber for encapsulating a microelectronics device |
US5354714A (en) * | 1991-08-01 | 1994-10-11 | Texas Instruments Incorporated | Method of forming a vacuum micro-chamber for encapsulating a microelectronics device |
FR2709206A1 (en) * | 1993-06-14 | 1995-02-24 | Fujitsu Ltd | Cathode device having a small aperture and its method of manufacture |
US5576594A (en) * | 1993-06-14 | 1996-11-19 | Fujitsu Limited | Cathode device having smaller opening |
US6140760A (en) * | 1993-06-14 | 2000-10-31 | Fujitsu Limited | Cathode device having smaller opening |
Also Published As
Publication number | Publication date |
---|---|
CA2034481A1 (en) | 1991-02-15 |
EP0438544B1 (en) | 1995-01-25 |
DE69016397D1 (en) | 1995-03-09 |
EP0438544A1 (en) | 1991-07-31 |
US4943343A (en) | 1990-07-24 |
CA2034481C (en) | 1993-10-05 |
IL94199A0 (en) | 1991-01-31 |
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