WO1990003004A1 - Multiport memory system - Google Patents

Abstract

A local area network which includes a plurality of computers (A, B, C, D) and a gateway device (100). The gateway device (100) includes a multiported memory and mailbox logic. Each of the ports (310) connects to different ones of the computers (A, B, C, D) through its corresponding data interface (120).

Description

MDLTIPORT MEMOKY SYSTEM BACKGROUND AND SUMMARY OF THE INVENTION The present invention relates to interfaces between different computer systems, and more particularly to multiported memory interface architectures. Establishing an interface between different computer systems is one of the basic types of problems in the art of computer engineering. Needs of this kind occur in a wide variety of system contexts, and a correspondingly wide variety of approaches have been used.

At one extreme, many high-speed computer designs use multiprocessing, where several (or many) different CPUs simultaneously run different instruction streams which implement different parts of a single program. In such architecture, a close interface between the different processors is obviously necessary.

At another extreme, various communications and signalling standards (such as are used for modem communication) provide general-purpose formats and protocols, which can be used by any general-purpose computer.

Bus protocols (such as VME bus, VersaBus, or NuBus) are another class of approaches, where control bits and addressing bits are used to select one device on a bus to receive data, interrupts, or commands.

Networking protocols (such as Ethernet or DECnet) are yet another class of approaches, but normally require some significant constraints on the computers which participate in the network. Local-area networks (LANs) for microcomputers are an area of tremendous activity, but the demands on the microcomputers involved are usually significant. Typically an additional card is used, to interface to a serial communications link and to buffer incoming messages.

In general, if the computer systems are separate they will be operating asynchronously. This means that timing is one of the inherent problems. Moreover if the interface is to be flexible, it must allow for the possibility that the computers may be operating at very different speeds. For example if an 80386 operating at 24 MHz is communicating with an 8088 in a standard IBM PC operating at 4.77 MHz it is desirable not to have to slow the 80386 down during the communications.

'Handshaking" logic is commonly used to permit reliable communication

SUBSTITUTE SHEET between asynchronous systems. For example such logic may require that the sending system sends out a "Request to Send" control signal, and then waits to receive a "Clear to Send" control signal from the receiving system, before any data transmission begins. However, handshaking logic is easiest to implement in two-way communication, and implementation in a multi-node network may impose delays or risk of lockup. Moreover, in a microcomputer network, the use of handshaking logic with sufficient flexibility to accommodate a multi-node network may risk an excessive time burden on the main CPU. In general one of the easiest ways to build an interface between two separate systems is with a master slave relationship. However, this requires that one of the systems be subordinated, and this would therefore interfere somewhat with the flexibility of the individual computers if such a paradigm were used as the basis of a network architecture. That is, a master/slave relationship normally requires that the slave processor (1) can only speak when spoken to and (2) must respond instantly. These 30 constraints mean that a master/slave paradigm is not well suited for use in a multitasking environment such as is becoming increasing common on personal computers.

Various mailbox architectures are commonly implemented in software to implement communications between computers. Such architectures will commonly use for example a set of flags to indicate for each of the addressable nodes, that incoming mail is available, that an interrupt has been generated by some other node, etc.

Multiported memories are frequently used by system designers to help provide a flexible interface. For example, U.S. Patents 4,652,993 4,654,788, and 4,604,683 (hereby incorporated by reference) provide examples of such use of multiported memory.

One embodiment of the present invention provides an improved small local-area network, using a compact gateway which includes: multiport memory, wherein each port has full read/write access to only one area of memory, but all ports have read access to all areas of memory; multiple ports for data interface; and mailbox logic. In the presently preferred embodiment, a software structure which performs data transfers in background is also provided.

SUBSTITUTE SHEET The innovative ideas of this embodiment provide the advantages of: 1) very small hardware cost, 2) minimal software load on the participating computers, 3) great flexibility in the type of computers which can be used, 4) ease of physical connection, and 5) no consumption of card capacity nor of port allocation of the participating microcomputers. However, it should be recognized that some of the inventive teachings set forth herein are much more broadly applicable.

Another specific innovative teaching set forth herein is an economical battery backed small module, accessible through multiple serial ports, which can act as a gateway between different computer processes.

Another specific innovative teaching set forth herein is an integrated circuit memory which is highly multiported and also compact and power- efficient.

In the presently preferred embodiment, a gateway module is connected to as many as four microcomputers by a simple wire link preferably using standard telephone cords. The gateway provides mailbox logic, so that each computer can send messages to any or all of the other computers. The computers are fully asynchronous, and may even operate at very different speeds. This system embodiment provides a very simple LAN. In many

LAN applications, certain communications paths will obviously be highly favored. For example frequent communication may obviously be needed between coworkers in the same group. Therefore, providing local interconnection between such frequently linked stations can satisfy much of the demand for networking. This can provide a more economical solution no networking needs in some environments, and can also supplement a larger network by reducing the communications load on the larger network.

Such a small network can also be a very advantageous way to link machines which are used by a single user. This provides a very flexible and convenient pathway for data transfer. Regardless of whether a larger network provides interface to other users, the flexibility of the small network may still be an efficient way to link machines.

The system and gateway of the presently preferred embodiment also contain safeguards against data corruption due to contention. At the end of every read operation the computer which is reading will also receive a trailing status byte. If data contention occurs logic in the gateway chip will change the trailing status byte to indicate that data corruption may have occurred. The receiving computer can therefore detect that data corruption has occurred and request a retransmission.

In the presently preferred embodiment, the hardware connections into the computers are made through the printer port. (A standard printer may also be connected to this port and the use of this port does not interfere with print operations.)

The use of this smart gateway permits the software structure to operate very simply. The routine manipulations needed for data handling are, in the presently preferred embodiment, performed in background so that the mechanics of communication can be made transparent to the user. The gateway chip includes a highly multiported memory and mailbox logic. In the presently preferred embodiment the memory is four ported. Each cell of the memory array is read-accessible to all four ports, but is write- accessible to only one port. (Each port has one quadrant of the memory array allocated to it.) Thus, write-access contention is impossible. One way to regard the advantages of the disclosed system is that it provides the advantages of a master/master interface, while retaining the smooth functioning of a master/slave type interface. In effect the gateway module provides a group of four slave processes, so that each computer is operating as the master end of a master/slave relationship. In the system of the presently preferred embodiment, each processor can have two processes running to handle communications over the local- area network. If the user wishes to initiate a transfer, a master communication-handling process can be activated to perform this. However, an additional communication-handling process is also provided, which runs in background. This background process is a slave process, which can be controlled by control signals coming in from the local-area network or by the master process. This slave communication-handling process handles routing and other such communications management tasks. For example if the user at Computer A wants to transfer a file XI on A's disk over to a file Yl on B's disk he commands the master communication-handling process on computer A to initiate this file transfer. The file transfer request and then the data bits of the file are transferred out of A's serial data port into the memory area into the gateway and are read in by computer B from the gateway. The background communication- handling process in computer B operating as a slave process manages this transfer until it is complete. Meanwhile, if a user or a non-interactive process on computer B wishes to transfer a different file X2 on computer A to file Y2 on computer B's hard disk, the master communication-handling process is commanded to initiate this transfer. The master communication-handling process on computer B then communicates, through the gateway with the slave communication-handling process on computer A. The two transfers then process essentially independently (subject to the limitations imposed by access to the single serial data link 110). The maser communication-handling process on computer A will be sending out file XI (through the gateway to the slave process on B) while at essentially the same time the slave communication- handling process on computer A will be sending out file X2 (through the gateway to the master process on B). Thus, the relationship of the communication process is approximately a master-slave-slave relationship but again it should be recognized that the flexibility of the gateway, and its ability to act in a slave mode, greatly facilitate implementation of this convenient communications architecture.

Note that the gateway can provide an interface between significantly different systems. For example a slow eight bit microprocessor (e.g. a Z80) can be interfaced with a fast thirty-two bit processor (e.g. an 80386) if needed.

A more straightforward approach is simply to let the individual memory chips be multiported. This would avoid the need for extra overhead logic circuits or software. However, it is not easy to construct memory devices which are fully multiported.

Even in a fully multiported device, some conflicts are possible. For example, if two computers attempt to write to the same memory cells at the same time, an inherent conflict exists. Less obviously, if one computer is

SUBSTITUTE SHEET attempting to write a memory cell at the same time as another computer is attempting to read that cell, the read-access may yield bad data since it may not be known whether old data or new data is being read.

Multiported memory cells, like conventional SRAM cells (static random access memory cells) normally store one bit of data in a latch. The latch has two nodes which are always in opposite data states. In a normal SRAM, the two nodes of the latch can be connected to a pair of bitlines by opening a pair of pass transistors. The two pass transistors are controlled by a common word line, which runs along a row of cells. One bitline pair runs along each column of cells in the memory array. When a cell is being read, a sense amplifier amplifies the weak signal on the bitlines to attain full digital signal levels.

A multiported cell, in a typical architecture, differs from a normal SRAM cell in having multiple pass-transistor pairs per cell, multiple wordlines per row of cells, and multiple bitline pair per column of cell. Each port can access one wordline for each row of cells. Each wordline controls one of the pass-transistor pairs in each cell. Each of the pass-transistor pairs connects the cell's latch node to one of the bitline pairs. The provision of separate wordlines per row of cell means that any two ports can access wordlines for any two rows at the same time, even if both ports want to access the same row. The provision of multiple bitline pairs per column of cells means that any two ports can access cells in any two columns simultaneously, even if both ports are accessing the same column. Thus, the different ports can access memory completely independently. Multiported memory cells are often designed using bipolar technologies. This is particularly convenient, since NPN drivers with high drive current capabilities can be used to drive the bitlines. However, in many applications, the low power consumption of CMOS is preferable to the speed of bipolar logic (or even of biCMOS), due to CMOS's advantages of low power and low-cost fabrication- Design of multiported memory cells in CMOS (and particularly low- power CMOS) is more difficult. In highly multiported memory cells, the operation of the memory cell must be much more carefully considered than with a memory cell which is not multiported. For example if two ports are trying to write data into the same cell at the same time, a contention obviously

TE SHEET exits. However, the potential for access by multiple processes can affect the cell design in other ways. Consider the case where two or three ports try to read the cell simultaneously. If each pair of bitlines is directly cormected to the cell's latch (through its own pair of pass transistors), the cell latch will see a dramatically different load impedance than would appear during a single- port access.

The importance of this can be seen by reviewing the factors in design of a conventional SRAM cell.

1) The ratio of the driver transistor width ( e. the width of the puD-down transistors in the latch) to the pass transistor width must be small enough that the driver transistors can be overpowered, when data is being written, by the current they receive through the pass transistors from the write voltages on the bitline pair.

2) A larger driver transistor can provide faster read operation, but will tend to result in slower write operation, and may increase the cell area.

3) A larger pass transistor provides faster read and write operations, but may increase the cell area.

U.S. Patent 4,742,487 to Bernstein discloses the problem of read-access collisions in multiport memory cells, and also discusses some background art in this area. Multiport memories are frequently used by system designers to help provide a flexible interface. For example, U.S. Patents 4,652,993,

4,654,788, and 4,604,683 (hereby incorporated by reference) provide examples of such use of multiported memory. The present invention provides an improved CMOS multiport memory cell. This cell uses uncomplemented buffer transistors to drive secondary nodes in each cell so that the secondary nodes follow the primary latch nodes. In each cell, the bitline pairs for some ports are connected (through the pair of pass transistors which correspond to that port) to the primary latch nodes (and therefore have full read-and-write access). Other bitline pairs are connected

(through their port's pass transistor pair) to the secondary nodes (and therefore have only read-only access rather than read-and-write access).

A further sub-point of novelty is that the bitline pairs which have only read access include cross-coupled active devices of opposite type to the uncomplemented buffer transistors.

A further sub-point of novelty is that, in place of the normal sense amplifier, a precharged latch is preferably used. This latch is activated only when valid data is expected to appear on a bitline pair.

The present invention also provides further innovative teachings, regarding the architecture of multiport memories generally, which are not only applicable to low-power CMOS multiport memories, but are also applicable to integrated circuit memories in biCMOS, ECL, or other technologies. Among these generally applicable teachings is an architecture, for highly multiported memories, where every port has read and write access to some cells, and read-only access to other cells.

A further sub-point of novelty is that preferably, each cell is write- accessible by only one port, so that write-write conflicts are totally avoided. A further sub-point of novelty is that, preferably, blocks of multiple cells are sequentially accessed at every read or write operation, and overhead logic is used to provide a check signal, at the end of every read operation from a given block, confirming that no write operation has been initiated on the same block of cells. These innovative teachings advantageously provide an integrated circuit memory which is highly multiported, and also reasonably compact.

These innovative teachings advantageously provide an integrated circuit memory which is highly multiported, and also highly power-efficient.

These innovative teachings advantageously provide an integrated circuit memory which is highly multiported, and also reasonably fast.

These innovative teachings advantageously provide an integrated circuit memory which is highly multiported and has almost no need for access arbitration in software or external logic.

The present invention provides a highly multiported memory. (In the presently preferred embodiment, the memory is four-ported, but of course the innovative principles disclosed can be adapted to memories with more or fewer ports.) Each cell of the memory array is read-accessible to all four ports, but is write-accessible to only one port. (Each port has one quadrant

SUBSTITUTE SHEET of the memory array allocated to it.) Thus, write-access contention is impossible.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:

Figure 1 schematically shows an innovative system wherein multiple computers are linked by an asynchronous four-way gateway.

Figure 2 is a schematic representation of an innovative adapter which permits data communication to occur over the printer port of a common microprocessor-based computer.

Figure 3 shows the general architecture of an integrated circuit used to implement a novel asynchronous four-way gateway which can be used in a system like that of Figure 1.

Figure 4 shows a high-level view of the physical layout of the integrated circuit of Figure 3.

Figure 5A shows the memory cell used to provide multiport memory in the presently preferred embodiment of the gateway of Figure 3. Figures 5B-5C show peripheral logic which is preferably used with an array of memory cells like that of Figure 5A.

Figure 6 shows key parts of the layout of the memory cell of figure 5, in the presently preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment, wherein these innovative teachings are advantageously applied to the particular problems of a compact LAN to interface between PC- or PS/2-compatible computers. However, it should be understood that this embodiment is only one example of the many advantageous uses of the innovative teachings herein. For example, the various types of innovative teachings disclosed can optionally

SUBSTIT be applied to LANs where the computers involved are not all PCs, or to LANs of other types, or to gateways for use in higher-speed systems. In general statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.

General System Organization

Figure 1 shows an innovative local-area network system, which uses the multiport memory enabled by the present invention. Four computers (A,B,C, and D) are linked by common modular phone cables 110 to an asynchronous four-way gateway 100. A special port adapter 120 (described in detail below) is preferably used at the interface to each computer. This low cost network, in the presently preferred embodiment can link up to four personal (or other) computers. Interface to the personal computer is established via the parallel printer port by connecting the port adapter 120. This adapter connection is external to the computer cabinet, and does not affect either the computer or printer operation. Connection from the port adapters 120 to the Gateway 100 is made with standard four wire telephone cable terminated with standard RJ-11 modular plugs (preferably six position type - but a four position type could optionally be used instead).

Hardware installation begins with connection of a port adapter 120 to the printer port of each personal computer in the network, as shown in Figure 2. If a printer cable is connected to the computer printer port, the port adapter is simply plugged in between the computer and the printer cable. (Preferably the port adapter is marked to indicate both computer side and printer side, to help avoid incorrect installation.) This is done for each PC to be used in the system (up to four.)

Once the port adapters are installed, they must be connected to the Gateway. Standard six-position four-wire jacketed phone cables 110, terminated with six-position modular plugs at each end are used to connect the Gateway 100 at any physical location between computers. (However, in the presently preferred embodiment, the total length of wire between any computer and the gateway must be limited to 100 feet.) Connection to the Gateway 100 is made by inserting the modular plug at one end of the wire 110 into the modular jack on the port adapter. The modular plug at the other end of the wire 110 can then be inserted into any of the four modular jacks marked A through D residing within the Gateway 100. Note that any PC may be connected to any port of the Gateway 100, and will automatically assume the correct identification upon network activation.

The gateway 100 contains a single large integrated circuit. This integrated circuit performs all of the crucial elements of the gateway's operation and will therefore be referred to as the gateway integrated circuit to distinguish it from the gateway module. The gateway integrated circuit contains multiported memory array, and also contains logic to implement the mailbox functionality (as described below) and serial communication protocols. In addition, in the presently preferred embodiment a pair of cascaded Schmitt trigger chips is connected to the clock line at each of the four ports of the gateway 110. These have been found to improve the accuracy of the serial data link.

The gateway 100 normally draws power from its connections over lines 110. However, to avoid data loss during periods when the gateway is not connected to any operating computer, the gateway 100 also contains a small battery back-up, which provides power to the gateway integrated circuit at all times. A simple diode isolation is used to prevent this battery from being drained over the lines 110.

Port Adapter

Figure 2 is a schematic representation of the innovative port adapter 120, as used in the presently preferred embodiment. This adapter permits data communication to occur over the printer port of a common microprocessor-based computer. To use the printer port without activating the printer, the STROBE line is simply held. The printer never sees the data output, because no edge ever appears on the STROBE line. In the presently preferred embodiment, communication over the printer port is accomplished using four lines in the

SUBSTITUTE SH standard printer port format.

The standard parallel printer port format has one set of pin assignments (referred to as DB-25) for the cable's interface to the computer, and a second slightly different set of pin assignments (referred to as the Centronics interface) for the cable's interface to the printer. Since the port adapter 110 is used only at the computer end of the printer cable, only the DB-25 pin assignments matter. In the DB-25 standard pins 2 through 9 are used for 8 data bits (DATA_1 through DATA_8). In the presently preferred embodiment, the adapter 120 connects two of these lines to the serial communication line 110: pin 4 (the DATA_3 line) is used for the reset signal RSTZ, and pin 5 (the DATA_4 line) is used for the clock line CLK. These two lines provide the necessary control signals, and a third wire of wire 110 carries the actual data. This third wire is connected to two pins of the DB-25 connection: pin 17 (which is normally designated as Select_In) is used to output data from the computer, and pin 12 (which is normally used for an out- of-paper signal from the printer) is available to receive data from the gateway. Alternatively, for example, pin 13 can be used instead of pin 12 for incoming data or another pin can be substituted. As noted the STROBE-bar line (pin 1) is held high by the computer when data communication through the printer port is desired.

Some previous attempts have been made to achieve data communication over a printer port. Dallas Semiconductor's part number DS1253, which is believed to have been on sale prior to September 1987, provided a security key interface through a printer port. More, IBM's PS/2 provided a capability for one-way file transfer (only) from the printer port of a PC to the printer port of a PS/2. However, this innovative teaching of the present application provides a "port-sharing" use of the printer port, where the printer port permits fully interactive two-way data communication between computers and also remains available for its normal function of interfacing to a printer. No such port-sharing use is known in the prior art. A review of printer port uses may be found in Eckel, "A PrngraTT.mf.r--s Guide to the Parallel Port," which appeared at page 74 of the November December 1987 issue of Turbo Technix and which is hereby incorporated by reference.

SUB Thus, port adapter 120 not only does not consume a slot, it does not even use up a port, since the printer can remain connected to the printer port as before, and the printer port can still be used in its normal fashion for printing.

Multiport Memory Hardware

The multiport memory of the presently preferred embodiment has a memory array of four quadrants. Each quadrant includes two columns of 32 bits each. Each of the eight columns of cells is accessed by four pairs of bitlines. Each of the 32 rows of cells is addressed by four word lines. Thus, there are 32 bitline pairs, 4 sense amplifiers, 128 word lines (plus four dummy word lines), and the memory contains a total of 256 bits. However, the architectural principles set forth herein can readily be scaled to other memory sizes, if desired. The innovative teachings set forth can also be readily applied to the design of multiport memories having a different number of ports, if desired. Thus, in the following description it must be noted that all specific references which relate to these parameters are merely illustrative.

In the following description, each bitline pair will be referred to as COLp(q,c)/COLZp(q,c), where the letter "p" indicates which of the four ports is connected to this particular bitline pair, "q" indicates which one of the four quadrants of memory, and "c" refers to the column address. (The letter Z, added to the name of a signal, generally indicates a complementary signal.) Thus, in this embodiment, the 32 bitline pairs would be written out as COLO(0,0)/COLOZ(0,0) through COL3(l,l)/COLZ3(3,l). Similarly, the word lines will be represented as pROW(r), where the letter "p" indicates which of the four ports is connected to the data in cells addressed by this particular word line, and "r" refers to the row address. Thus, in this embodiment, the 128 word lines would be represented as 0ROW(0) through 3ROW(31).

Figures 3 and 4 show the architecture and the general layout of the gateway integrated circuit which includes an array of multiport memory cells with appropriate peripheral and I/O circuits, and also includes logic to implement mailbox ^•functionality. The memory array and its operation will first be described in detail, and the mailbox implementation will then be described.

SUBSTITUTE SHEET Preferred Memory Cell

Figure 5A shows the memory cell used to provide multiport memory, in the presently preferred embodiment of the gateway of Figure 3. This particular memory cell is assumed to be located in row "r" and column "c" of quadrant number zero.

Latch 510 is bistable, and therefore can store one bit of information. The two PMOS devices each have nominal dimensions of 3 microns wide and four microns long, and the two NMOS devices each have nominal dimensions of 12 microns wide by 2 microns long. (In the presently preferred embodiment, scaling has already been applied, so that all nominal dimensions should be multiplied by 90% to get the actual as-patterned dimensions. However, gate lengths have not been scaled below 2 microns.)

The two nodes 510A and 510B of this latch are connected through a first pair of pass transistors 514A which are both gated by a signal 0ROW, to a pair of bitlines COL0(q,c) and COLZ0(q,c).

Thus, by precharging the bitline pair COL0(q,c) and COLZ0(q,c) high and then driving 0ROW(r) high to turn on the first pair of pass transistors 514A, one of the two NMOS transistors in latch 510 will pull down one of the two bitlines as COLO(q,c) and COLZ0(q,c), generating a data signal which can be amplified by a sense amplifier. Conversely, by applying complementary digital signals to the bitlines (e-g.. 5V to COL0(q,c) and 0V to COLZ0(q,c) or vice versa) and then driving 0ROW high to turn on the first pair of pass transistors 514A, one of the two NMOS transistors in latch 510 will be turned on and the other turned off (regardless of the previous state of the latch 510), thus writing information into the cell. This is essentially the same as the conventional operation of a normal single-port SRAM cell.

Nodes 510A and 510B are also connected to the gates of two pull¬ down buffer transistors 512. (In the presently preferred embodiment these transistors are each 12 microns wide and two microns long.) These cause secondary nodes A' and B' to follow the state of primary nodes A and B respectively. Thus, when any one or more of the three other word lines 1ROW, 2ROW, or 3ROW is driven high, the corresponding pass transistor pairs 514B, 514C, and/or 514D will be turned on to couple the signal on nodes A' and B' onto the corresponding bitline pair. Thus, any one of the word lines 1ROW, 2ROW, or 3ROW can be activated at any time to immediately achieve a fully static read operation. In alternative embodiments (which are presently less preferred), the pull-down buffer transistors 523 can be made wider than the drivers in the latch 510, and/or the 0ROW pass gates 514A can be made wider than the other three pass transistor pairs 514B, 514C, and 514D.

Layout of the Preferred Memory Cell

Figure 6 shows the layout of the multiport memory cell in the presently preferred embodiment. Areas 602 and 604, with solid line borders and no hatching, indicate active device areas. Area 610, with dotted borders and no hatching, indicates the p-well area (where NMOS transistors will be located). Areas 620, with solid borders and stippling, indicate polysilicon lines. (A MOS transistor will occur wherever a polysilicon line crosses an active device area. This transistor will normally be NMOS in active device area 604, and PMOS in area 602.) Solid black squares 650 indicate contacts, where a metal line 640 is in ohmic contact with polysilicon or with the silicon substrate. Areas with solid borders and cross hatching indicate metal lines. The presently preferred embodiment uses single level metal, but of course it will be readily recognized that double- or triple-level metal could be used instead.

As will be obvious to those skilled in the art of integrated circuit fabrication, other patterning steps would normally be used in the fabrication of a complete integrated circuit. For example, another masking step (using a pattern which is almost the same as the p-well pattern) is normally used to keep the N + source/drain implant out of the PMOS transistors; another masking step is normally used to remove a protective overcoat from contact pad locations; and other masking steps may be used for threshold adjustment or other functions if desired.

Accessing the Memory Array

Figure 5B shows the logic preferably used to control write access to

SUBSTITUTE SHEET each column of memory cells. Note that one of the four bitline pairs has different logic from the other three: this is because, as noted above, only one bitline pair can write data into the cell; the other three bitline pairs have read access only. Again, the logic shown is assumed to be for a column in quadrant zero, so that bitline pair COL0(q,c)/COLZ0(q,c) is the only one of the four bitline pairs which has write access to the cells in this column.

All four bitline pairs have a precharge transistor pair 524. When these transistors are turned on, they will precharge their respective bitline pair to approximately the supply voltage V(DD). (This would be done just before a read operation.) In addition bitline pair COL0(q,c)/COLZ0(q,c) (but not the other pairs) has a write data access transistor pair 522. When data is to be written in, these transistors connect the write data to the bitline pair COL0(q,c)/COLZ0(q,c). (In the presently preferred embodiment, the sense amplifier is preferably of a type which is not convenient for write access to the data lines, as will be discussed below.)

The three read-only bitline pairs COLl(q,c)/COLZl(q,c), COL2(q,c)/COLZ2(q,c), and COL3(q,c)/COLZ3(q,c) each have a cross- coupled pair of PMOS transistors 520. These transistors prevent the one of the bitlines which is not being pulled down from floating. That is, after the precharge transistors have turned off and the pass transistors have turned on for the cell (in this column) whose row has been selected, the pull-down buffer device pair will be pulling down only one of these lines. When a cell is accessed, and its pull-down buffer transistors begin to pull one of the bitline pair low, one of the pull-up transistors 520 will begin to turn on to hold the other one of the bitline pair. This helps to provide noise margin during the real operation. In the presently preferred embodiment, each of the transistors 520 has nominal dimensions of 2.75 microns wide and 5 microns long.

Figure 5C shows the sense amplifier which is used, in the presently preferred embodiment, for each of the four ports. Column select logic controls PMOS pass transistors, not shown, which multiplex each port's eight bitline pairs onto this sense amplifier. This circuit does not provide feedback onto the bitlines, but instead is used simply as a switched balanced latch, which is enabled only after valid data is expected to be present on the bitline pair.

SUBSTITUTE SHEET A row of dummy cells, with a set of four dummy word lines, is used to set the timing for the sense amplifiers. The dummy cells each include a latch like the latch 520 used in the memory cells, and also include all four pairs of pass transistors 514A-514D. However, one node of the latch is simply tied to ground, and the bitline pairs simply pass over the dummy cell without making connection to it

Thus, when port number "p" (for example, port 2) accesses row "r" of cells (for example, row 6), the row decoder will not only raise that port's word line pROW(r) for that row of cells (in this example, line 2ROW(6)), but will also raise that port's dummy word line pROW(D) (in this example, line 2ROW(D)). This dummy word line is connected to exactly as many pairs of pass gates as the data word lines pROW(r). Moreover, of each pair of pass gates which the dummy word line sees, one is coupled to a high potential and one is coupled to a low potential, as in the memory cells. Since the dummy cells and the dummy word lines have nominal dimensions which are exactly equal to those of the data cells and their word lines, the resistance and the capacitive loading of the dummy word line will be very close to that of the data word lines, despite any variations in sheet resistance or specific capacitance which may occur during processing. Therefore, the time constant of the dummy word line will be very close to that of the data word lines. Therefore, since the elements in the row decoder which drive the dummy word line pROW(D) are the same as those which drive the data word lines pROW(0)-pROW(31), the voltage on the dummy word line pROW(D) will closely track that on the active data word line during the beginning of a read or write access. Therefore, the pull-down transistors in invertor 531 will turn on at approximately the same time as the pass transistors 514 in the same column. Invertor 531 preferably has an NMOS device which is 11 microns wide and 2 microns long, and a PMOS device which is 5.5 microns wide and 2 microns long, so the effective threshold voltage of the pulldown device in invertor 531 will be slightly lower than that of the pass transistor.

Invertor 532 preferably has an NMOS device which is 25 microns wide and 2 microns long, and a PMOS device which is 5 microns wide and 2 microns long. The additional delay imposed by the invertors 531 and 532 will

SUBSTITUTE SHE T allow for the extra delay imposed by the distributed capacitance of the bitline pair COLp(q,c)/COLZp(q,c) to which this particular sense amplifier is connected.

While the output of invertor 532 has been low, PMOS precharge transistors 534 have been turned on and NMOS transistor 533 has been turned off. However, when the output of 532 begins to drop, precharge transistors 534 will turn off as soon as the voltage has fallen one V(TP) below the supply voltage. This leaves the latch 530 in a metastable condition where both the PMOS transistors 535 are off and both of the NMOS transistors 536 are turned on. (Both of the transistors 537 are already turned on strongly, due to the bitline precharge.) As the large NMOS sinking transistor 533 begins to turn on, the state of the latch becomes increasingly unstable. The data signal on bitline pair COLp(q,c)/COLZ(q,c) will bring one of the data transistors 537 down into its analog regime while the other data transistor 537 is still hard on. The resulting current difference produces a voltage difference on the two nodes of latch 530, and this causes one of the latch pull-up transistors 535 to begin to conduct before the other. This further amplifies the differential between the two latch nodes, and also induces a difference in conduction through NMOS transistors 536. (Note that transistors 536 preferably have their substrate potential tied back to their sources.) Thus, the latch fires conventionally and reaches a steady state, where one of its nodes is driven high and the other is driven low.

To equalize the loading on the nodes of the sense amplifier, an invertor 538 is connected to each node, although one of these invertors is a dummy. The output of one of the invertors is passed through a clocked transmission gate 539, and latched to provide a stable data output.

As noted above, a cross-coupled pair of PMOS transistors 520 is provided on 24 of the 32 bitline pairs. Note also that the sense amplifier of Figure 5C is not regenerative (j e. does not provide an amplified signal on the bitlines).

Message-Handling Functionality

The gateway chip of the presently preferred embodiment includes not

SUBSTITUTE SHEET only the memory array and access logic just described, but also contains logic which provides mailbox and message-handling functionality and off-chip communication. This additional functionality helps to provide a flexible gateway. This gateway provides a low cost device which can be used to loosely couple up to four computers, microprocessors or microcontrollers. The message-handling protocols will now be described, and the implementation of this functionality will be described thereafter.

Arbitration is handled by protocol, and a message center forces discipline and prevents collisions. Each port has read access to all four quadrants of memory array 400, and can therefore read information from all other ports. Each port can write information only in its one quadrant of memory array 400, so that write access collisions are impossible.

Each of the ports is connected to a three wire serial bus which can be accessed by an external computer. The use of a serial bus keeps pin count low, while affording sufficient bandwidth to accommodate loosely coupled system communication. Each port also has a message flag, which can be used to warn of message ready conditions.

Thus, there are four separate three wire serial ports. Each port has direct read and write access to eight message bytes (he. one quadrant) of memory array 400. These bytes are designated as "belonging" to that particular port. In addition, the external computer connected to each port has read only access to three groups of eight message bytes each, which are designated as belonging to the three other ports. To send a message between any two ports, the sending port writes a message in its allocated quadrant, and the receiving port reads those eight message bjrtes. Since each port can read every quadrant of memory, each port can receive a message from and other port. On-chip logic generates a check byte after each group of eight message bytes to verify data integrity. All of the cells within the RAM matrix are quad- ported (i.e. four-way multiported), and can be read simultaneously by all four ports if desired. This reduces arbitration to concerns of read write collision only.

Each of the four three wire serial ports also contains a three byte protocol register. This defines access to the RAM, and controls arbitration

SUBSTITUTE SHEET between the four ports. (In the presently preferred embodiment, the elements of this register, which will be described below, are actually somewhat distributed.)

The first byte of the protocol register is called the "port select" byte. This byte contains an eight bit identification pattern. If the first 8 bits sent on an active port do not match this pattern, any further activity will be ignored. (This identification test permits multiple gateways to be tied onto the printer port of a single microcomputer. This identification test also avoids conflict with other functions which may make use of the printer port of a microcomputer.) A port is active when the reset line is inactive (high) and the CLK input is transitioning. The first eight bits are sent into a port on the data line IOp, and are latched on the rising edge of the CLK input.

The second byte of the protocol register contains eight bits of status information about activity on all four ports. This byte, called the "message- center" byte, is divided into two nibbles: the "message-sent" nibble and the "mailbox" nibble. The first four bits (the message-sent nibble) tell which ports have not yet received messages sent to them. By reading these four bits, the inquiring port knows not to send new messages to a receiving port which has not yet read a previously sent message. Each message-sent bit is cleared when the receiving port reads the last bit of its message, or when the RSTZ input of the receiving port is driven low while the receiving port is reading. The next four bits (the mailbox nibble) of the message-center byte indicate which ports have sent messages to this port (the port which includes this protocol register) which are ready for reading. These bits are set (in accordance with the destination bits of a message) when a sending port finishes writing the last bit of a message.

The bits of the message-center byte can be read, but not written, over the serial data link. All message-center bits are driven out on the data line IOp (i.e. IO0, IOl, 102, or 103) while RST is inactive and the CLK input is low. The third byte of the protocol register contains the execution code.

The execution code byte is also divided into two four bit-nibbles: the "action code" nibble and the "destination" nibble. This byte can be written by the external processor (over the serial data link), but can not be altered by the on-

'SUBSTITUTE SHEET chip logic of the gateway. The data is input on the IOp line, with RST active and the CLK input transitioning from low to high.

The bits of the action code nibble have only three patterns which will allow subsequent action to take place: An action code of four zeros (0000) calls for a read-message action to occur in one of the four quadrants of the memory array, at an address specified by the destination bits. A read-message can occur to only one port and, therefore, only one of the four destination bits can be set for an action code of 0000. Once a destination bit is set, the on-chip logic will reset the message-sent bit in the sending port's protocol register only as specified above (i.e. when a complete message of eight bytes has been read, or the receiving port's RSTZ is driven low).

An action code of a one and three zeros (1000) calls for a write- message action to be performed. A write-message can only be written in the section of RAM 400 that is identified with the sending port. However, a message which is written by a sending port can be directed to one or more ports by setting appropriate values in the destination bits. The destination bits will cause on-chip logic to set the mail box bits in the protocol register of the ports which are to receive the message to "1" (logic one) as soon as the last bit of the message is written by the sending port (or RSTZ is driven, as noted above).

An action code of two ones and two zeros (1100) calls for a write-message to be performed, and indicates that more data will follow. This action code works exactly the same as a standard write-message action, with one exception. The check byte which follows an eight byte message is driven to a special code which, when read by a receiving port, indicates that more messages will be coming. This information can be used by a receiving port to reduce the overhead of constantly polling for new .messages.

As mentioned, each port has direct read and write access to eight message bytes (i.e. one quadrant of RAM 400), and read access to three groups of eight message bytes. Once the protocol register has been correctly accessed, one of the four sections of the RAM 400 will be read, or that section of the RAM 400 which is dedicated to the transmitting port will be

_SUBSTITUTE SHEET written. When sending a message, all eight message bytes should preferably be written. When receiving a message, all eight of the message bytes will normally be read. (However, a read operation may be terminated by a reset signal, as mentioned above.) A check byte (byte 11) is provided at the end of each of the eight message byte groups. The check byte is read only and provides information to a receiving port. Reading the check byte code is optional and may not be necessary in applications where software discipline is stringent enough to avoid accidental collisions between messages sent and messages received. Three different codes give status to a receiving port about the messages sent and messages received. Three different codes give status to a receiving port about the message which has just been read: good data, corrupted data, and good data with more data coming. When the check byte is read with a good data code, the data which is read by a receiving port is correct and -valid. This check byte code assures the receiving port that a sending port is not writing a new message while the receiving port is attempting to read the previous message. When the check byte is read with a corrupted data code, the data which is read by a receiving port is suspect. This check byte warns the receiving port that the sending port is writing a new message while the receiving port is reading an older message. When the check byte is read with a good-data-and-more-coming code, the data which is read by a receiving port is correct and valid, and the receiving port is informed that additional messages will follow. This check byte code can be used by a receiving port to reduce the overhead of frequent polling. If the check byte indicates that a new message will follow, the receiving port is warned to expect a new message.

The gateway chip of the presently preferred embodiment has two methods of warning the sending and receiving ports of impending message status. The software method of polling avoids the complication of additional hardware which is required to connect the message ready pins to a host sending/receiving unit. Polling is accomplished with a receiving unit by satisfying the port select byte of the protocol register and reading the message center. When a port is being polled, care should be taken to avoid entering the execution code portion of the protocol register. When polling a port, communications can be teπninated by taking the RSTZ input signal low.

An alternate method of alerting a host sending/receiving unit of impending message status is to use the message ready signals to generate an interrupt to a microprocessor when a message is ready to be read. The message ready pins (MZO-MZ3) are driven to an active state (low) when a sending port has written the last bit of the eight message bytes and RSTZ of the sending port is set to inactive state (low), provided the appropriate destination bit is set. When the message ready pin is set to an active state, a receiving unit can execute a software routine to service the interrupt and read the pending message. However, note that the use of these pins requires using a fourth line in each of the wires 110. These pins are available on the preferred gateway chip, but are not used in the preferred system embodiment.

All message transactions are initiated by one of the computers driving the RSTZ (or RST-bar) input pin high. Each of the RSTZ input pins (there is one at each port) serves two functions. First, it turns on control logic which allows access to the protocol register. Second, the RSTZ signal provides a method of terminating message transfer. Care must be taken when terminating a message transfer to avoid errant information in the message center. The following rules will avoid all problems.

While polling the message center for new messages, always terminate the transaction by driving RSTZ low after completing a read of the message- center byte and before entering the execution code byte.

When sending a message, all eight message bytes must be written. If fewer than eight bytes are written, the mailbox bit of the destination port(s) may not be set and the check byte may indicate corrupted data.

When receiving a message, all eight bytes will normally be read.

However, if RSTZ is used to terminate a message which is being read, the message sent bit and the mailbox bit are cleared as RSTZ is driven low. When reading a message, the check byte is optional, and can be either read or ignored.

A clock cycle is a sequence of a falling edge followed by a rising edge. For message inputs, the data must be valid during the rising edge of the clock

SUBSTITUTE cycle. Protocol bits and message bits are input on the rising edge of the clock. Protocol bits and message bits are output on the falling edge of the clock. All message transfer terminates if RSTZ is low, and the data pins IO0-IO3 will then go to a high impedance state. When message transfer is terminated using RST, the transition of RSTZ should occur while the clock is at the high level, to avoid disturbing the last bit of data.

^•f-ircnϊt Implementation of Message-Handling

The circuit implementation which permits the above-described functionality to be achieved will now be described in detail. Figure 3 shows the general architecture of the gateway integrated circuit of the presently preferred embodiment. A multiport memory array 400 (with its four quadrants 400A, 400B, 400C, and 400D schematically indicated), together with the peripheral logic very schematically indicated as 320, is as described above. In addition, each port has a protocol register 310, which holds important status information as described above. The four protocol registers 310 are actually somewhat distributed, as will be described below. Moreover, these registers are linked together, as schematically indicated by lines 330, by set/clear logic which provides an efficient control interface, as described above. Figure 4 shows a high-level view of the physical layout of the gateway integrated circuit of the presently preferred embodiment. A memory array 400 is accessed by wordline drivers 402, by read-column-select logic 404 (which connects a selected column, for each port, to that port's sense amplifier 408). Write-coluπm-select logic 406 connects a selected column to the write-access transistors 522. Preferably, the cross-coupled PMOS pair 520 and precharge transistors 524 are also located in this area.

Each of the four ports includes message-handling and interface logic elements. It may be seen, in Figure 4, that the block of elements 410, 420, 430, 440, 450, 460, 470, 480, and 490 is repeated four times (for the four ports).

Each of the four ports also has four dedicated external pins: CLKp (i.e. CLK0-CLK3), RSTZp, IOp, and MZp. (As is conventional, electrostatic discharge protection is provided at each pin.) The incoming CLK and RSTZ signals are monitored by clock logic 490, which generates internal clocks, and by counter/decoder 440. (In the presently preferred embodiment, this is a seven-bit counter, but of course other sizes could be used instead, depending on the serial data format used.) Each bit of the counter's total is brought out separately, and these bits are decoded, to provide enable signals which permit various elements on the chip to pick off the appropriate elements in the serial data stream. For example, when the count reaches 88 during a read operation, a signal called CNT88 activates the

DIT_DONT logic 420 to provide the check byte output referred to above. These decoded counts, in effect, provide mask bits so that the appropriate bits of the incoming serial data stream can be loaded into appropriate logic elements.

_..T e -jata p^ IOp are connected to input/output (I/O) buffers 460. These are conventional input buffers and output drivers, but it should be noted that the output driver has tri-state capability. That is, under certain conditions the output buffer 460 leaves the data line IOp in a ^" high-impedance (floating) condition.

ROM code/port detect logic 470 contains a hard-wired identification address (preferably an eight-bit address). Whenever the computer accesses the port, the port detect logic compares the first byte of the incoming message

(the port select byte referred to above) with the hard-wired identification tag to see if the message address matches the unique signature of this port.

When data is being sent back to the computer, the mailbox logic 410 receives the second byte of the outgoing message. As noted above, this byte includes a messages-sent mbble and a mailbox mbble. (The logic used to set and clear these bits will be described below.)

The third byte (the "execution code" byte) is written into action logic 450. The action logic 450 checks the "action code" 'mbble against the "destination code" nibble, to ensure that a legal combination of action and address is being specified. If no error is detected, the "action .code" nibble is translated by action logic 450 to (eventually) activate the appropriate memory peripherals 402, 404, 406, and/or 408, and the "destination code" controls logic which will (eventually) set this port's bit in the mailbox nibble and the message-sent nibble of one or more of the other ports. A four-phase scan mask is generated by the action logic 450, to load the appropriate bits of the destination code into field bit storage 430. (Similarly, the SM_CLR logic 480 is able to clear this port's bit in one of the other ports' message-sent nibbles, after a successful read operation. However, this clear action is conditional. It is performed only if the DITJDONT logic 420 finds that the read access is complete and has been made without error. If this occurs, a one-shot is fired to clear the appropriate bit.)

The DΓT_DONT logic 420 also contains simple logic combinations to generate the three possible check-byte values (in hexadecimal notation, AA, 5A, or 55) which may be required, as noted above. This logic will also kill the Read or Write signal, if data is bad, before the one-shot can fire to clear the message-sent bit (at the sending port) or the mailbox bit corresponding to the destination port.

Software Orpaτn^'τarinn

Preferably, software is used to permit the communications over this interface to occur in background. This software provides for a master process and a slave process, as described above, and also performs normal error recovery functions. (For example, if corrupt data is received, either of the communication-handling processes can automatically request a resend.) This software will now be described in detail.

The following text briefly describes the major functions performed by the various modules of the PC Interlink software package and outlines the structure of the background network server. The software package consists of a program to install the background network server, and several utility programs to be used for transferring data between host computers attached to the network.

A. INTRUNK < hostname >

INTRLINK is the name of the program which installs the PC Interlink background network server. <hostname> is a name (of six characters or fewer) which the user chooses to refer to the computer that he is using. If the

SUB <hostname> is absent, the default <host name> used is #i, where i is the number of the Interlink port which is attached to the computer. The major functions performed by this program are as follows:

1. Check whether the Interlink background network server is already installed. If it is, return to DOS after displaying the following message:

The PC Interlink is already active. Please re-boot to remove Interlink.

2. For each of the installed parallel ports, send a self-addressed message packet to each of the four possible quad ports and attempt to read it back. Tabulate the number of successful reads. If this number, <i>, is not equal to one, return to DOS after displaying the following message:

<i> Interlink ports are connected to this computer. For the PC interlink to operate correctly, only one Interlink port may be connected to any given computer. Please check the connections to make sure you have an Interlink port connected to this computer.

3. Save the parallel port address and quadport number found in step

2 above in memory reserved for use by the background network server.

4. Put the introduction packet out to the quadport, addresed to all of the other three ports. Wait a predetermined time for a response, then check the message-center to determine which other computers have read the introduction message and have responded with their own <hostname>s. For each of these, read the <hostname> and store it in a table to associate it with the port number from which it was read. (This table maintains a list of all the currently active hosts. A host is added to the table whenever an introduction packet is received, and it is deleted whenever a remote host fails to respond for a specified period of time.) Display the table in the following form: The following users are now active: Port Host Name:

^'SUBSTITUTE SHEET i <hostnamei>

_j <hostnamej> k <hostnamek>

5. Install the information interchange block on interrupt 19 to enable program modules running in the foreground to exchange information directly with the background network sever.

6. Install the background network server procedure on the timer and other interrupts to enable it to gain periodic control. This background -process responds to requests from other hosts to send or receive information.

7. Terminate and stay resident (TSR) after displaying the following message: PC Interlink Resident Monitor Installed.

B. ICOPY < source filespeo < destination filespeo

ICOPY is the name of the main utility program for sending DOS files from one host to another. ICOPY cbpies the data from the file or device denoted by <source filespeo to the destination denoted by < destination filespeo.

1. < source filespeo may have either of the forms indicated below:

<source filespeo := <DOS source filespeo^', or <hostnaιϊιe>-= <DOS source filespeo.

<DOS source filespeo here represents a specification- which is legal as a source specification for the COPY command in MS DOS.

2. < destination filespeo may have either of ffie forms indicated below: < destination filespeo™ <DOS dest filespeo, or

<hostname> = <DOS dest filespeo. <DOS dest filespeo here represents a specification which is legal as a destination specification for the COPY command in MS DOS. . Whenever a source or destination filespec begins with <hostname> =,the program ICOPY will attempt to access the data on the quadport whose number is associated with <hostname> in the active host table. If < hostname > = is absent, the filespec is assumed to refer to the user's computer. In the presently preferred embodiment, this is subject to the constraint that either the source or destination filespec (or both) must be on the user's computer.

If the given hostname does not match any of the hostnames in the active user table, the program will return to DOS after displaying the following message:

User < hostname > is not active at this time. The program ICOPY posts the task of performing the data transfer for the background process and then waits for the background process to take over and complete the transfer. The background network server completes the transfer by stealing time periodically from the foreground process until the transfer is complete. Posting is accomplished through the information interchange block located on interrupt 19.

If for any reason the transfer is not allowed (for example, the source file or device does not exist), ICOPY will display the appropriate error message and return to DOS.

Note that device names are legal in commands such as the following:

ICOPY \LOTUS\SALES.PRN EVELYN=LPT2 This command causes the text contained in the file SALES.PRN in the subdirectory LOTUS of the user's computer to be printed on the printer LPT2 of the computer denoted by the hostname EVELYN.

C. IERASE <filespec>

This program attempts to erase the file denoted by <filespeo. < filespeo may have either of the following forms: <filespeo is <DOS filespeo, or

<filespeo is <hostname> = <DOS filespeo. <DOS filespeo is any specification which is legal as an argument of the ERASE command in MS DOS. If the <hostname> is not present, the program assumes that the file is on the local host, attempts to erase it, and displays the results of the attempt. If the <hostname> is present, the program looks in the active host table for a matching entry. If none is found, the program returns to DOS after displaying the following message:

User <hnstrjaτne> is not active at this time. If the <hostname> is present in the active host table, the program obtains the corresponding quadport number form the table and sends an erase command packet to that port, followed by a series of packets containing the filespec of the file to be erased. The program then awaits the response packet from the remote host which gives the results of the erase attempt, and displays the results on the console.

D. IDIR < directory filespeo This command causes a directory of the information in < directory filespeo to be displayed. < directory filespeo may have either of the following forms:

< directory filespeo is <DOS dir filespeo, or <directory files> is <hostname> = <DOS dir filespeo. "<DOS dir filespeo" is any specification which is legal as an argument of the DIR command in MS DOS.

E. ISTAT

This command causes the table of active hosts referred to above to be displayed. This information is obtained from the backgroimd process through pointers in the information interchange block on interrupt 19.

F. Background Network Server

This is the resident background process installed by the program INTKLTNK described in A. Once the background process is installed, it remains resident in memory until the computer is re-booted. The background network server is active regardless of what program the local host computer is running, and it is invoked periodically by the timer hardware interrupt to

SUBSTITUTE SHEET perform several essential functions as described below:

1. Poll each of the other quadports for which no active task is posted to see if any message has been received. Examine the first byte of any received message to determine the type of message and proceed accordingly as follows:

a. If the message is an introduction packet from another host, copy its <hostname> into the table of active hosts, then construct a packet consisting of the local <hostname> preceded by a code byte indicating an acknowledgment packet. When the output channel is available (messages sent = O), transmit the acknowledgment packet back to the port from which the introduction packet was received. b. If the message is a read-file (or device) command from another host, wait to receive the subsequent packets containing the DOS filespec from the remote host and attempt to perform the open operation locally using this specification. Send back a packet to the remote host containing the results of the attempted open command. If the attempt was successful, alter the state variable to indicate remote file transfer on that quadport number, and reserve the resulting file handle so that it will not be closed accidentally by any program running in the foreground. Next, transfer the first group of data packets back to the remote host and return to the foreground process. The next time the background server is called, it will sense the state variable and will send back the next group of data packets, continuing until all packets have been sent, the file handle is released, the file is closed, and the read-in-progress state is cleared. (The size of the packet group and the period of the server invocation will be adjusted to give the most satisfactory performance on both the local and remote hosts.) c. If the message is a write command, make sure there is a local file handle assigned to be written to. If so, post the flag indicating that the write operation is in progress and proceed in the same manner as in c above. (Note that there is a different set of task flags for each quadport, so that a read can be taking place from one remote host while a write is taking place to a different remote host. However, only one task can be posted to the same remote host at the same time.) d. If the message is a write file (or device) command from another host, wait to receive the subsequent packets containing the DOS filespec from the remote host and attempt to perform the open operation locally using these specification. Send back a packet to the remote host containing the results of the attempted open command. If the attempt was successful, alter the state variable to indicate a remote file transfer on that quadport number, and reserve the resulting file handle number so that it will not be deleted accidentally by any process running in the foreground. Next, wait to receive the first group of data packets from the remote host and write them in the file, and then return to the foreground process. The next time the background server is called, it will sense the state variable and receive the next group of packets, continuing until all packets have been sent, the handle is released, the file is closed, and the write-in-progress state is cleared. (Note that there is a different set of task flags for each quadport, so that a read can be taking place to a different remote host. However, only one task can be posted to the same remote host at the same time.) e. If the message is an erase command from an other host, wait to receive the subsequent packets contøining the DOS filespec from the remote host and attempt to perform the erase operation locally using this specification. Send back a packet to the remote host containing the results of the attempted erase command. f. If the message is a directory command, wait to receive subsequent packets conta ing the filespec for the directory, then send back one group of packets of directory information and post the task flag indicating the directory operation in progress. Additional groups of directory information are sent back on successive invocations of the server until all the information has been sent and the task flag cleared. 2. Examine the active task flags to dete^*rmine which operations in progress require service. Transfer a packet group for each active task according to the type of task.

3. Examine the local task flags posted by the utility programs to indicate a data transfer in progress, then transfer a packet group for each uncompleted local task, clearing the local task flags for any operations that are completed. (The local task flags are posted by the utility programs using data pointers in the information interchange block associated with interrupt 19.) 4. If any remote host fails to receive information sent to it (as indicated by the messages-sent nibble) within a specified period of time, the <hostname> associated with that quadport number is removed from the table to indicate that this remote host is no longer available. Any local handle opened by that remote host is then closed, and any task in progress flag associated with that remote host is cleared. The same action is taken if a remote host fails to respond to a request for information within a specified period of time (as indicated by the mailbox mbble).

5. After all new messages have been responded to and all active tasks serviced, return to execution of the foreground program while awaiting the next invocation of the background process.

In all of the message exchanges described above, each computer also constructs an error check message. An error check message is transmitted after every complete transmission, or after every 32 messages, whichever is less. The error-check message is then used by the two computers to determine whether to continue sending or to retransmit the previous group of messages. In this way, a degree of protection is provided against data errors.

Further Modifications and Variations

It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moveover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative.

These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts.

For one example, the number of ports does not have to be four. In particular, the disclosed architecture could be directly adapted to gateways with a larger number of ports, and such embodiments might be even more advantageous. The architecture of the preferred embodiment provides a network which effectively permits every node to talk to every other node. Such a ghly-connected network becomes more advantageous as the number of nodes increases. By contrast, in a network architecture such as Ethernet, the communication of all processors must share the bandwidth of the serial link, and performance is therefore limited by that bandwidth. Of course, the exact architecture of the presently preferred embodiment may not be the most advantageous architecture if the number of ports becomes very much larger, but the disclosed innovative ideas can be adapted to other architectures.

Optionally, the gateway architecture of the presently preferred embodiment can be modified to permit extension, so that multiple gateways could be connected. This can be done by, for example, adding logic to modify headers in accordance with data contained within the messages. However, this alternative is presently less preferred.

For participation in larger network architectures, one of the nodes connected to the gateway can be replaced by an interface card (e.g. an Ethernet interface card) which interfaces to the larger network.

A further alternative embodiment is the use of two gateways back-to- back, with a processor providing a smart interface. For example, two four- port gateway chips can be combined with one microprocessor to provide a very compact and economical six-port LAN gateway. Optionally, if line drivers are also included, this compact configuration can also be connected to a higher-level network. The present version of the memory is a four megahertz part, i-e. has a 250 nanosecond full cycle time. However, it will be readily recognized by those skilled in the art that this access time can be drastically improved if desired. In general, it is expected that (if the additional speed is needed) multiport full-CMOS memories according to the present invention can be given access times which are much closer to those of a conventional SRAM of comparable process technology and dimensions. It should also be recognized that the disclosed innovative features of the memory array and access operations can be used apart from the serial data interface used at the ports.

Of course, the innovative concepts set forth herein can be widely modified and varied. For example, one alternative embodiment of the memory cell uses an "upside-down" cell, where the bitline pairs are precharged low, the pass transistors are PMOS, the latch nodes are connected to drive pull-up (PMOS) buffer transistors rather than the pull-down buffer transistors used in the presently preferred embodiment, a cross-coupled NMOS pair is used on the read-only bitline pairs, and the types of the devices in the sense amplifier are exchanged. For another example, it is possible (although less preferred) to give more than one (but less than all) bitline pairs read and write access to each cell. The balancing of devices in the cell is still easier for two pass-transistor pairs than for four, and in some applications this might provide additional flexibility. For example, this embodiment might be used where access arbitration between two of the ports could be expected to be present, or where the system architecture inherently precludes write-write conflicts between two of the ports.

For another example, it is similarly possible (although also less preferred) to give one or more ports read-only access to the memory. For example, the presently preferred embodiment could be modified to permit ports 0 and 1 to each have read and write access to half of the memory cells, and ports 2 and 3 to have only read-only access to all of the cells in the array.

Moreover, it should be recognized that the architectural ideas set forth herein (although not the specific cell layout) can readily be adapted to technologies other than CMOS, as noted above.

The present invention has been discussed with the primary reference to microcomputers, ^*Le. to computer systems whose CPU is an 8080, 80386, 68020, 32032, or comparable microprocessor. However, it should be recognized that the innovative teachings set forth herein could also be applied to a wide range of other types of computer systems, including minicomputer systems, multiprocessor systems, and particularly multicomputer systems.

Multiple gateway chips can be operated in parallel if desired. For example, by stacking eight gateway chips together, with their clocks (and other control signals) ganged together, a byte-wide interface would result. By departing from the strictly serial organization of the presently preferred embodiment, this alternative embodiment provides substantially more memory, and a substantially faster interface. As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly their scope is not limited except by the allowed claims.

Claims

CLAIMSWhat is claimed is:

1. A gateway device, comprising: multiple ports, each providing an external data interface; an array of multiported memory cells, each write-accessible by at least one of said ports and read-accessible by more than one of said ports; wherein said external data interface is defined to provide power to said array when data access is occurring; and further comprising message-handling logic, connected so that, at each said port, a processor accessing said memory through one of said ports can read status bits to determine whether messages which should be read are waiting, and whether messages it has written have not yet been read.

2. A gateway device, comprising: multiple ports, each providing an external data interface; an array of multiported memory cells, each write-accessible by at least one of said ports and read-accessible by more than one of said ports; wherein said external data interface js defined to provide power to said array when data access is occurring; and further comprising a battery, packaged together with said gateway device, and connected to provide power to said array, to retain data therein, during- periods when data access is not occurring.

3. A networked multi-computer system, comprising a gateway device, comprising multiple ports; and a plurality of computers, each being connected to a respective port of said gateway device; wherein said gateway device operates as a slave to each of said computers, and comprises: multiple ports, each providing an external data interface; an array of multiported memory cells, each write-

SUBSTITUTE SHEET accessible by at least one of said ports and read-accessible by more than one of said ports; wherein said external data interface is defined to provide power to said array when data access is occurring; and further comprising message-handling logic, connected so that, at each said port, a processor accessing said memory through one of said ports can read status bits to determine whether messages which should be read are waiting, and whether messages it has written have not yet been read.

4. A microcomputer system, for interfacing to a network, comprising: a microcomputer, comprising a parallel printer port which is strobed to indicate normal printing outputs thereon; an adapter, connected to the parallel printer port of said microcomputer, said adapter bringing out at least two lines from predetermined pins of said parallel printer port to connect to a data link; wherein said microcomputer is prr.grammp.ri to permit data to be output over said printer port by driving said predetermined pins of said parallel printer port without strobing said parallel printer port.

5. An adapter, for connection to the printer port of a microcomputer, comprising: a first parallel-port connection shaped to mate with the parallel printer port connector on a computer; a second parallel-port connection, shaped to be connectable to cables which are connectable to the parallel printer port connector on a computer, pins of said second connection being wired together with corresponding pins of said first connection; a first serial data connection, comprising at least two lines which are cormected to predetermined pins of said parallel printer port; and a second serial connection, comprising at least two lines which are connected to predetermined pins of said parallel printer port; whereby said first serial data connection can be accessed by the microcomputer, to permit data to be output through said printer port over a

T data link attached to said first serial data connection by driving said predetermined pins of said parallel printer port without strobing said parallel printer port.

6. A multiport memory, implemented in a complementary integrated circuit logic technology, comprising: multiple ports, each providing an external data interface; a plurality of memory cells, each including a latch comprising complementary device pairs connected to drive a pair of primary nodes to complementary states, said primary data nodes being selectably accessible to a first bitline which is operatively cormected to a first one of said ports, a pair of secondary data nodes driven by a pair of buffer devices, said pair of secondary nodes being selectably accessible to at least a second bitline which is operatively connected to a second one of said ports, said pair of buffer devices each being connected to provide current of only one polarity to one of said secondary data nodes, in accordance with the state of one of said primary nodes, wherein at least some ones of said second bitline pairs, but not ones of said first bitline pairs, are connected to a cross-coupled pair of active devices each of which is connected to provide current, of a polarity opposite to the polarity provided by said buffer devices, to one bitline of said respective second bitline pair.

7. A CMOS multiport memory, comprising: multiple ports, each providing an external data interface; a plurality of memory cells, each including a latch comprising complementary CMOS device pairs connected to drive a pair of primary nodes to complementary states, a first pair of pass transistors, gated by a first wordline to selectably connect said primary data nodes to a first bitline pair which is operatively connected to a first one of said ports, a pair of secondary data nodes driven by a pair of NMOS buffer devices, said pair of buffer devices being connected to pull down one of said secondary data nodes, in accordance with the state of said primary nodes, a second pair of pass transistors, gated by a second wordline to selectably connect said secondary data nodes to a second bitline pair which is operatively connected to a second one of said ports, each said bitline pair being connected to precharge devices, which selectably pull up said bitline pair to a high level; wherein at least some ones of said second bitline pairs but not ones of said first bitline pairs are connected to a cross-coupled pair of PMOS active devices, each of which is connected to pull up one bitline of said respective second bitline pair.

8. A multiport memory, comprising: at least three ports each providing an external data interface; and a plurality of memory cells, each including a static data storage element, and each cell being simultaneously accessible by at least three of said ports; each of said ports having direct read-and-write access to some of said cells, and having only read-only direct access to all others of said cells.

9. The memory of Claim 6, wherein each one of said ports has direct read-and-write access to some ones of said memory cells.

10. The memory of Qaim 6, wherein each one of said memory cells is directly read-and-write accessible to only a respective one of said ports.

11. The memory of Qaim 5, wherein substantially every one of said memory cells is read accessible by every one of said ports.

12. The memory of Qaim 6, wherein said latch is a CMOS latch.

SUBSTITUTE SHEET

13. The memory of Claim 6, wherein said latch is a CMOS latch, and wherein said buffer device pairs each comprise two NMOS transistors, and wherein said cross-coupled device pairs comprise cross-coupled PMOS transistors.

14. The memory of Qaim 6, wherein said latch comprises two PMOS transistors and two NMOS transistors.

15. The memory of Qaim 1, wherein in each said cell, access to each respective said pair of bitlines is controlled by a respective pair of pass transistors.

16. The memory of Claim 1, further comprising a plurality of sense amplifiers, each selectably connected through a multiplexer to multiple ones of said bitline pairs, and each connected to only one of said ports,

17. The memory of Qaim 1, further comprising a plurality of sense amplifiers connectable to ones of said bitline pairs, each comprising a precharged and switched latch and each connected to only one of said ports.