WO1988002148A1

WO1988002148A1 - A transparent translation method and apparatus for use in a memory management unit

Info

Publication number: WO1988002148A1
Application number: PCT/US1987/001341
Authority: WO
Inventors: William C. Moyer; Edward J. Ii. Rupp; David W. Trissel; Anantakotiraju Vegesna; Russell C. Stanphill
Original assignee: Motorola, Inc.
Priority date: 1986-09-15
Filing date: 1987-06-08
Publication date: 1988-03-24

Abstract

In a data processing system (10) comprising a central processing unit (CPU) (12), a memory management unit (MMU) (16) and a storage system (14), the MMU (16) translates each of the logical addresses output by CPU (12) to a corresponding physical address in the storage system (14). In the MMU (16), a comparator (32) determines if each logical address is within an address range defined by an address range descriptor stored in a transparent translation register (TTR) (30). If a logical address is found to be within that address range, the MMU (16) is forced to provide that logical address as the corresponding physical address without translation. Selected control signals may be conditionally provided in the event of such a ''transparent'' translation.

Description

A TRANSPARENT TRANSLATION METHOD AND APPARATUS FOR USE IN A MEMORY MANAGEMENT UNIT

Field of the Invention The subject invention relates generally to memory management units and, more particularly, to a method and apparatus to force a memory management unit to provide each of a plurality of logical addresses within a selected range of logical addresses as a respective physical address without translation.

Background Art

In data processing systems having virtual memory capabilities, a memory management unit (MMU) is provided to translate each "logical" address in virtual memory as it is output by the data processor to a respective "physical" address in real memory. In general, upon initiation of system operation, the MMU is in a non-translation mode so that each logical address is provided as the respective physical address without translation. After the operating system has initialized all appropriate logical-to-physical address translation information in the MMU or in memory, as the case may be, the MMU can be put into the normal translation mode. Thereafter, the MMU will translate all logical addresses output by the processor to the respective physical addresses according to the translation information established by the operating system.

In some systems, certain portions of the available physical address space are reserved for special functions, such as memory-mapped I/O, system tables, shared code and the like. To minimize the time necessary to access these reserved portions of physical memory, steps can be taken to "bypass" the MMU. For example, in at least one prior art system, commercially available from Sun Microsystems, Inc. , of Mountain View, CA, the MMU includes special address detection hardware which, upon detecting logical addresses within a fixed address range, immediately forces the MMU to gate such logical addresses directly from the logical address bus to the physical address bus without translation or any associated table-walking. Although this technique greatly speeds up the operation of the processor to locations within this fixed portion of memory, there is no provision for direct access to other portions of the physical memory. Neither is there any mechanism for modifying the physical address of this dedicated portion of memory if such becomes necessary or desirable. Further, this scheme restricts the range of dedicated physical addresses to physically contiguous memory locations. Finally, there is no ability for the user/supervisor to turn off this mechanism, either permanently or temporarily, should the need arise.

Summary of the Invention

Accordingly, it is an object of the present invention to provide a transparent translation mechanism which allows the range of non-translated addresses to be dynamically changed.

Another object of the present invention is to provide a technique whereby the range of non-translated addresses is not restricted to a set of physically contiguous addresses.

One other object of the present invention is to provide a transparent translation mechanism which can be selectively restricted to certain types of access, i.e. reads only, writes only, or both reads and writes.

Still another object of the present invention is to provide a transparent translation mechanism which can be selectively restricted to certain classes of operands, i.e. data or instructions or both.

Yet another object of the present invention is to provide a transparent translation mechanism which can be selectively restricted to certain modes of access, i.e. user or supervisor or both. One other object of the present invention is to provide a transparent translation mechanism which allows transparent translated addresses to be selectively cache inhibited.

These and other objects are achieved in a memory management unit which translates each of a plurality of logical addresses to a corresponding physical address using a respective one of a plurality of predetermined logical-to- physical address translators. In accordance with the present invention, a register is provided in the memory management unit for storing an address range descriptor which defines a selected range of said logical addresses. In addition, a comparator is provided in the memory management unit for comparing each logical address received by the memory management unit for translation to the selected range of logical addresses defined by the address range descriptor, and for forcing the memory management unit to provide said received logical address as said respective physical address if said received logical address is within the selected range of logical addresses.

Brief Description of the Drawing Figure 1 illustrates in block diagram form, a data processing system constructed in accordance with the present invention.

Figure 2 illustrates in schematic form, the preferred form of the transparent translation register and the comparator shown in Figure 1.

Description of the Invention Shown in Figure 1 is a virtual memory type of data processing system 10 comprising a central processing unit (CPU) 12, a storage system 14 and a memory management unit (MMU) 16. In general, supervisor and user programs are stored in the storage system 14, which typically comprises high speed memory and slower speed peripherals such as disks, at respective physical addresses. During operation, the CPU 12 references the instructions and data operands comprising these programs using respective logical addresses. The MMU 16 receives the logical addresses output by the CPU 12 via a logical address bus 18, translates these logical addresses to the corresponding physical addresses using logical-to-physical address translation descriptors stored either within the MMU 16 or within the storage system 14, and forwards the resultant physical addresses to the storage system 14 via a physical address bus 20. In response to receiving each physical address, the storage system 14 allows the CPU 12 to access a respective storage location within the storage system 14 via a data bus 22.

Within the MMU 16, an address translation cache (ATC) 24 is provided to temporarily store a selected subset of the translation descriptors so that many, if not most, of the logical addresses output by the CPU 12 can be rapidly translated to the corresponding physical addresses. A translation controller 26 is provided to find any translation descriptor not resident in the ATC 24 by "walking" a set of translation tables stored in the storage system 14. If the ATC 24 is full, one of the resident translation descriptors, preferrably the least recently used, will be discarded to make room in the ATC 24 for the new translation descriptor. Once translated, the resultant physical address is gated onto the physical address bus 20 via a bus switch 28»

In the preferred form of the MMU 16, a transparent translation register (TTR) 30 is provided to store an address range descriptor which defines a range of logical addresses that the MMU 16 is not to translate. A comparator 32 is also provided to compare each logical address as it is output by the CPU 12 on the logical address bus 18 to the address range descriptor stored in the TTR 30. If the logical address is determined to be within the address range defined by the address range descriptor stored in the TTR 30, the comparator 32 enables the bus switch 28 to couple the logical address bus 18 directly to the physical address bus 20, thereby bypassing the ATC 24. Preferably, the comparator 32 will simultaneously disable the operation of the ATC 24 and the translation controller 26, to preclude unnecessary table walking.

In the preferred form shown in Figure 2, the address range descriptor stored in the TTR 30 generally comprises an Enable (E) bit 34 and a primary address range qualifier 36. If appropriate, one or more secondary address range qualifiers 38-40 may also be provided. In some applications, the address range descriptor may include one or more address range conditionals 42 which control respective output signals.

In general, each of the address range qualifiers comprises a base field and a mask field. For example, in the preferred form shown in Figure 2, the primary address range qualifier 36 comprises a logical address (LA) base field 36a and a logical address mask (LA MASK) field 36b, the first secondary address range qualifier 38 is comprised of a Read/Write (R/W) base field 38a and a Read/Write mask (R/W MASK) field 38b, and the second secondary address range qualifier 40 is comprised of a Function Code (FC) base field 40a and a Function Code mask (FC MASK) field 40b.

In deciding whether or not a particular logical address is "within" the address range defined by a given address range descriptor, each of the bits of each of the base fields are compared one-for-one against corresponding bits of the logical address. However, for the purposes of determining a "match", only those bit comparisons for which the corresponding bit in the respective mask field(s) is "clear", i.e. logic zero, are considered "significant". Only if all of these "significant" bit comparisons are "equal" will the logical address be considered to fall within the given address range.

An alternate way of viewing the address range matching mechanism is to consider only those bits of the base field(s) for which the corresponding bit of the respective mask field(s) is "clear" as "significant". During the matching decision, only these "significant" bits are compared one-for-one to corresponding bits in the logical address. Only if all of these bit comparisons are "equal" will the logical address be considered to be within the address range defined by this descriptor.

In the preferred form shown in Figure 2, comparator 32 generally comprises a decision array 44 which is enabled by a transistor 46 only if the Enable bit 34 in the TTR 30 is "set", i.e. logic high. Within the decision array 44, a discharge path between the input of a sense amplifier (SA) 48 and the transistor 46 is provided for each of the bits comprising each of the several base fields 36a, 38a and 40a. Each of the discharge paths are comprised of a first transistor 50 in series with a second transistor 52. The gate of each of the transistors 50 is coupled to the output of a respective EXCLUSIVE OR gate 54 responsive to a respective one of the bits of one of the base fields and to a corresponding one of the bits of the logical address. The gate of each of the transistors 52 is coupled to a corresponding one of the bits of the respective mask fields via a respective inverter 56.

In operation, a particular bit of the logical address will "match" only if the corresponding one of the discharge paths of the decision array 44 is "opened" either (1) by the transistor 50 being turned off in response to the corresponding EXCLUSIVE OR gate 54 determining that that particular bit of the logical address is the same as the corresponding bit in the respective base field, or (2) by the respective transistor 52 being turned off in response to the corresponding bit in the respective mask field being "set". Thus, the full logical address will "match" only if all of the several parallel discharge paths comprising the decision array 44 are simultaneously opened by some combination of bit matchs and/or bit masks. In this situation, the input of the SA 48 remain logic high. The resultant logic high output by the SA 48 will in turn indicate that the current logical address is within the address range defined by the address range descriptor currently stored in the TTR 30.

In the preferred embodiment shown in Figure 1, the output of the SA 48 controls the bus switch 28 so that, upon the detection of a logical address within the address range defined by the address range descriptor currently stored in the TTR 30, that logical address will be coupled directly onto the physical address bus 20. The output of the SA 48 also simultaneously disables the ATC 24 and/or the translation controller 26 to preserve the state of the entries in the ATC 24 and to prevent unnecessary table walking.

In some applications, it may be desirable to condition certain activities upon whether or not a particular physical address was generated as a result of a normal translation or as a result of a transparent translation. For example, in a data processing system in which data and/or instruction caches are provided to enhance performance, it would be inappropriate to cache accesses to memory mapped peripherals. On the other hand, the present transparent translation mechanism is particularly well suited to support direct addressing of these areas. To enable conditional control of such system functions as cacheing, the address range descriptor may include one or more conditional fields 42. For example, as shown in Figure 2, a Cache Inhibit (Cl) field 42a may be provided to selectively enable an AND gate 58 to provide a Cache Inhibit (Cl) signal whenever the output of the SA 48 indicates that the current logical address is within the address range defined by the current address range descriptor stored in the TTR 30. This Cl signal may be provided to the rest of the data processing system 10 either directly or via the Translation Controller 26, as appropriate. Although the present invention has been described herein in the context of a preferred embodiment, alternate embodiments may be made without departing from the spirit and scope of the present invention. For example, in some applications it may be appropriate to provide more than one transparent translation register 30, together with a corresponding comparator 32, so that multiple translation translation regions may be supported. If desired, a different number of address qualifiers, or simply different address qualifiers, may be desirable. Similarly, additional or different address conditionals may be appropriate. In any event, however, the present invention may be used to signficant advantage to provide versatile, selective control of logical-to-physical address translations.

Claims

CLAIMS What is claimed is:

1. In a memory management unit which translates each of a plurality of logical addresses to a corresponding physical address using a respective one of a plurality of predetermined logical-to-physical address translators, the improvement comprising: register means in the memory management unit for storing an address range descriptor which defines a selected range of said logical addresses; and comparator means in the memory management unit for comparing each logical address received by the memory management unit for translation to the selected range of logical addresses defined by the address range descriptor, and for forcing the memory management unit to provide said received logical address as said respective physical address if said received logical address is within the selected range of logical addresses.

2. The memory management unit of claim 1 wherein: said register means comprises: a base field having a predetermined number of bits, and a mask field having said predetermined number of bits, and said comparator means comprises: first logic means, responsive to the bit values in said mask field, for determining from the bit value of each of the bits of said mask field which of the bits of said base field are significant, second logic means, coupled to first logic means and responsive to the bit values in said base field and said logical address, for comparing each of the significant bits of said base field to a corresponding one of the bits of the logical address and providing an output only if all of said bits compare equal, said output indicating that said received logical address is within the selected range of logical addresses.

3. The memory management unit of claim 2 wherein the register means includes an enable field, and the comparator means is selectively enabled by the bit value in said enable field.

4. The memory management unit of claim 3 wherein the register means includes a conditional field, and the comparator means is selectively enabled by the bit value in said conditional field to provide a condition signal upon detecting that said received logical address is within the selected range of logical addresses.

5. The memory management unit of claim 2 wherein the register means includes a conditional field, and the comparator means is selectively enabled by the bit value in said conditional field to provide a condition signal upon detecting that said received logical address is within the selected range of logical addresses.

6. The memory management unit of claim 1 wherein the register means includes an enable field, and the comparator means is selectively enabled by the bit value in said enable field.

7. The memory management unit of claim 1 wherein the register means includes a conditional field, and the comparator means is selectively enabled by the bit value in said conditional field to provide a condition signal upon detecting that said received logical address is within the selected range of logical addresses.