WO1986003606A1 - Arrangement for apportioning priority among co-operating computers - Google Patents

Arrangement for apportioning priority among co-operating computers Download PDF

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Publication number
WO1986003606A1
WO1986003606A1 PCT/SE1985/000429 SE8500429W WO8603606A1 WO 1986003606 A1 WO1986003606 A1 WO 1986003606A1 SE 8500429 W SE8500429 W SE 8500429W WO 8603606 A1 WO8603606 A1 WO 8603606A1
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WO
WIPO (PCT)
Prior art keywords
priority
bus
signal
access
low
Prior art date
Application number
PCT/SE1985/000429
Other languages
French (fr)
Inventor
Lars-Örjan KLING
Original Assignee
Telefonaktiebolaget L M Ericsson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget L M Ericsson filed Critical Telefonaktiebolaget L M Ericsson
Priority to AU50932/85A priority Critical patent/AU580359B2/en
Priority to KR1019860700547A priority patent/KR910003015B1/en
Priority to AT85905902T priority patent/ATE45825T1/en
Priority to BR8507112A priority patent/BR8507112A/en
Priority to DE8585905902T priority patent/DE3572552D1/en
Priority to JP60505172A priority patent/JPH0630086B2/en
Publication of WO1986003606A1 publication Critical patent/WO1986003606A1/en
Priority to FI862682A priority patent/FI88549C/en
Priority to NO86862764A priority patent/NO170999C/en
Priority to DK381686A priority patent/DK165077C/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/46—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using electromechanical counter-type accumulators

Definitions

  • the invention relates to a priority apportioning arrangement for computers containing processors of two types, high-priority type which can determine its priority itself in relation to processors of the second low-priority type when using a common bus, such as to allow the use of the bus by the low-priority type also, if the high-priority processor does not have important tasks.
  • the object of the invention is to shorten the waiting and to give the high- priority processor full priority when it needs the bus, but to give access to the low-priority processors when the bus is not needed by the high-priority processor. This is achieved in accordance with the invention by access to the bus being blocked for the low-priority units when the high-priority one needs the bus, whereas when the high-priority unit does not need the bus immediately, the low-priority units are given access for a time in given proportion to the operating time of the high-priority unit.
  • the invention is characterized as will be seen from the claim.
  • Figure 1 is a block diagram of a processor system with processors working over a common bus
  • FIG. 2 is a block diagram of a priority distribution arrangement in accordance with the invention.
  • Figure 3 is a time chart illustrating how the bus is assigned when the high- priority processor does not need the bus immediately
  • a processor 1 with high priority is connected via a bus 2 to a plurality, in all eight, of low-priority processors 3a- 3h.
  • a memory 4 is connected to the bus, and the processors have acess to the memory via the bus.
  • the problem occuring in this co-operation is that access for the high-priority processor must always be ensured, while the low-priority processors share the remaining access time.
  • this is solved by the priority apportioning arrangement denoted by 5.
  • the arrangement is indicated as a separate unit, but may be divided such that certain parts are in the processors.
  • the signals with which these units communicate with each other will be explained in detail in connection with Figure 2. Their designations are as follows:
  • BMA bus master address. Selects one of the 8 low-priority processors.
  • EBG external bus grant. Grants access to one of the low-priority units.
  • MBG intensive processor bus grant. Grants access to the high-priority processor.
  • RQB request bus. Request for bus access from the low-priority units.
  • REB reserve bus. Request for access to the bus from the high-priority processor.
  • BOC bus occupied.
  • the bus is engaged, work is in progress.
  • Figure 2 illustrates the priority apportioning arrangement in the form of a block diagram.
  • the mutual apportioning of the bus between the low-priority pro ⁇ cessors takes place with the aid of a logic consisting of a PROM memory 10 and a register 11.
  • Each low-priority processor 3a-3h in all eight according to the exemplified embodiement, sends a signal RQB with a request for access to the PROM memory 10, which contains a table. In the table there is given the address to that of the low-priority processors which shall be activated next. The address is pointed out by a signal BMA which enables addressing eight different units via a 3-wire line.
  • the fed-out address is registered in the register 11 and points out in the memory a new address which is to be used when the next low- priority processor sends an RQB signal.
  • a wait flip-flop denoted by 6 has its output activated when bus access is desired according to the programme, and an access flip-flop is denoted by 7, this flip-flop being activated when the processor has obtained access, and is kept activated as long as this processor uses the bus. During this
  • the flip-flop 7 is activated by a comparator 8 determining that the address BMA sent from the register 11 agrees with the address of the processor itself and activates an input on an AND circuit 9, which obtains an EBG signal on another input, denoting that the bus is available for the low-priority processors.
  • a comparator 8 determining that the address BMA sent from the register 11 agrees with the address of the processor itself and activates an input on an AND circuit 9, which obtains an EBG signal on another input, denoting that the bus is available for the low-priority processors.
  • the arrangement includes a first logic circuit 20 controlling the assignment of the bus alternatively to the high- priority unit or to a low-priority unit, and a second logic circuit 40, the output signal of which indicates that the high-priority unit is in immediate need of the bus or that it can temporarily release the bus to a low-priority unit.
  • the first logic circuit 20 is arranged outside the processors while the second logic circuit 40 is in the high-priority processor. However, where the logic circuits are situated has no importance from the inventive aspect.
  • the first logic circuit 20 has three inputs, a first where a signal RQB occurs when one of the low-priority units needs the bus, a second where a signal REB occurs when the high-priority unit needs the bus and a third where a signal BOC occurs denoting that the bus is engaged by one of the units.
  • the signals on the first and the second inputs are taken to an AND circuit 21 which sends an output signal only if the high-priority unit does not request access, and is blocked for the opposite case.
  • This signal is fed to an input on an AND circuit 22 the negation input of which obtains the signal BOC.
  • an EBG signal is se it to enable access for one of the low-priority units.
  • a further AND circuit 23 is arranged, which obtains the AND circuit 21 output signal on one side and the BOC signal on the other side. If both these signals cease, the signal MBG is generated, which assigns the bus to the high-priority unit and this signal is fed to the second logic circuit 40.
  • a program selector denoted by 30 provides one of two alternative signals in response to the programme in progress.
  • the first type of signal from the programme selector signifies that immediate bus access is desired by the high- priority unit, and the other signal signifies that immediate access is desired, but low-priority units are also permitted to use the bus.
  • a wait flip-flop denoted by 41 has its output activated immediately when the first type of signal is fed to its activating input S. The output signal blocks the circuit 21 so that access to the bus from the low-priority units is prevented, and when the (bus occupied) signal BOC ceases, the bus is once again assigned to the high-priority unit by the signal MGB.
  • an AND circuit 39 This is fed to one input of an AND circuit 39, the other input of which obtains the programme selector signal via an OR circuit 38.
  • the output signal of the AND circuit 39 activates an access flip-flop 42, which feeds a BOC signal via its output to the logic circuit 20 to indicate that the bus is occupied. If the first type of signal remains from the programme selector, the output of the wait flip-flop 41 is immediately activated so that the circuit 21 is kept blocked and no EBG signal is sent for giving access to the low-priority units.
  • the other type of signal from the programme selector 30 signifies that the high-priority unit can allow access for a low-priority unit.
  • a flip-flop 43 which is activated by this signal, feeds a signal to the input of and AND circuit 6 in which a negation input is connected to the output of the flip-flop 42 so that it is blocked the whole time the high-priority processor uses the bus.
  • the output of the AND circuit 46 is connected to an input of the OR circuit 47 which will send the output signal of the circuit 46 to the AND circuit 21.

Abstract

A priority apportioning arrangement for computers that contain processors of two types, a high-priority type which can determine its priority itself in relation to processors of a second low-priority type when using a common bus. The arrangement contains a first logic circuit (20) which has its first input activated on a request for access from one of the low-priority units (3a-3h), its second input activated on a request for access from the high-priority unit (1) and its third activated during the whole time the bus is used and has two outputs for assigning the bus a low-priority unit or the high-priority unit. The arrangement furthermore contains a second logic circuit (40) with two inputs, of which one senses that the high-priority unit desires access and the other senses that this access can take place with delay, the circuit also having two outputs, of which one is for indicating to the first logic circuit that the access request from the high-priority unit is present, and the other for indicating that the bus is occupied. When the input signal to the second logic circuit indicates that granting the bus to the high-priority unit can take place with delay, the arrangement has time to grant the bus to a low-priority unit, but the high-priority unit still has immediate access to the bus after termination of the task of the low-priority unit.

Description

ARRANGEMENT FOR APPORTIONING PRIORITY AMONG CO-OPERATING COMPUTERS
TECHNICAL FIELD
The invention relates to a priority apportioning arrangement for computers containing processors of two types, high-priority type which can determine its priority itself in relation to processors of the second low-priority type when using a common bus, such as to allow the use of the bus by the low-priority type also, if the high-priority processor does not have important tasks.
BACKGROND ART
In a system having several processors using the same bus where none of the processors has priority, distribution on the bus can take place with the aid of a ' logic which obtains a signal from each of the prospective users and assigns the bus to them in a given order, with the latest user coming last. None of the processors can be kept out longer than for a number of accesses corresponding to the number of processors minus one.
Apportioning becomes more complicated when a number of processors with low priority and a processor with high priority work on the same bus. In known arrangements, such as that described in Electronic Design, May 24th, 1978 an extra time is necessary for assigning the bus when the high-priority processor needs it.
DISCLOSURE OF INVENTION
The object of the invention is to shorten the waiting and to give the high- priority processor full priority when it needs the bus, but to give access to the low-priority processors when the bus is not needed by the high-priority processor. This is achieved in accordance with the invention by access to the bus being blocked for the low-priority units when the high-priority one needs the bus, whereas when the high-priority unit does not need the bus immediately, the low-priority units are given access for a time in given proportion to the operating time of the high-priority unit. The invention is characterized as will be seen from the claim.
BRIEF DESCRIPTION OF DRAWINGS
The invention will be described below with the aid of an embodiment and with reference to the accompanying drawings, on which
Figure 1 is a block diagram of a processor system with processors working over a common bus,
Figure 2 is a block diagram of a priority distribution arrangement in accordance with the invention, and
Figure 3 is a time chart illustrating how the bus is assigned when the high- priority processor does not need the bus immediately
BEST MODE FOR CARRYING OUT THE INVENTION
According to Figure 1 a processor 1 with high priority is connected via a bus 2 to a plurality, in all eight, of low-priority processors 3a- 3h. A memory 4 is connected to the bus, and the processors have acess to the memory via the bus. The problem occuring in this co-operation is that access for the high-priority processor must always be ensured, while the low-priority processors share the remaining access time. In accordance with the invention this is solved by the priority apportioning arrangement denoted by 5. The arrangement is indicated as a separate unit, but may be divided such that certain parts are in the processors. The signals with which these units communicate with each other will be explained in detail in connection with Figure 2. Their designations are as follows:
BMA = bus master address. Selects one of the 8 low-priority processors. EBG = external bus grant. Grants access to one of the low-priority units. MBG = intensive processor bus grant. Grants access to the high-priority processor. RQB = request bus. Request for bus access from the low-priority units.
REB = reserve bus. Request for access to the bus from the high-priority processor.
BOC = bus occupied. The bus is engaged, work is in progress. Figure 2 illustrates the priority apportioning arrangement in the form of a block diagram. The mutual apportioning of the bus between the low-priority pro¬ cessors takes place with the aid of a logic consisting of a PROM memory 10 and a register 11. Each low-priority processor 3a-3h, in all eight according to the exemplified embodiement, sends a signal RQB with a request for access to the PROM memory 10, which contains a table. In the table there is given the address to that of the low-priority processors which shall be activated next. The address is pointed out by a signal BMA which enables addressing eight different units via a 3-wire line. The fed-out address is registered in the register 11 and points out in the memory a new address which is to be used when the next low- priority processor sends an RQB signal. Of the low-priority units only the unit 3h is indicated in detail. A wait flip-flop denoted by 6 has its output activated when bus access is desired according to the programme, and an access flip-flop is denoted by 7, this flip-flop being activated when the processor has obtained access, and is kept activated as long as this processor uses the bus. During this
' time the flip-flop sends the signal BOC denoting that the bus is engaged by the processor. The flip-flop 7 is activated by a comparator 8 determining that the address BMA sent from the register 11 agrees with the address of the processor itself and activates an input on an AND circuit 9, which obtains an EBG signal on another input, denoting that the bus is available for the low-priority processors. Such an arrangement is already known.
If it is now desired to subdivide the access between the low-priority processors and the high-priority processor such that the former will have access to the bus during a time which is in a given proportion to the time during which the high- priority processor uses the bus, although permitting the high-priority processor to have immediate access to the bus at any time, an arrangement in accordance with the invention is then necessary. The arrangement includes a first logic circuit 20 controlling the assignment of the bus alternatively to the high- priority unit or to a low-priority unit, and a second logic circuit 40, the output signal of which indicates that the high-priority unit is in immediate need of the bus or that it can temporarily release the bus to a low-priority unit. According to the exemplified embodiement, the first logic circuit 20 is arranged outside the processors while the second logic circuit 40 is in the high-priority processor. However, where the logic circuits are situated has no importance from the inventive aspect. The first logic circuit 20 has three inputs, a first where a signal RQB occurs when one of the low-priority units needs the bus, a second where a signal REB occurs when the high-priority unit needs the bus and a third where a signal BOC occurs denoting that the bus is engaged by one of the units. The signals on the first and the second inputs are taken to an AND circuit 21 which sends an output signal only if the high-priority unit does not request access, and is blocked for the opposite case. This signal is fed to an input on an AND circuit 22 the negation input of which obtains the signal BOC. When the signal BOC thus ceases in connection with the bus being disengaged and the signal REB does not occur since the high-priority unit is not in immediate need of the bus, an EBG signal is se it to enable access for one of the low-priority units. A further AND circuit 23 is arranged, which obtains the AND circuit 21 output signal on one side and the BOC signal on the other side. If both these signals cease, the signal MBG is generated, which assigns the bus to the high-priority unit and this signal is fed to the second logic circuit 40.
A program selector denoted by 30 provides one of two alternative signals in response to the programme in progress. The first type of signal from the programme selector signifies that immediate bus access is desired by the high- priority unit, and the other signal signifies that immediate access is desired, but low-priority units are also permitted to use the bus. A wait flip-flop denoted by 41 has its output activated immediately when the first type of signal is fed to its activating input S. The output signal blocks the circuit 21 so that access to the bus from the low-priority units is prevented, and when the (bus occupied) signal BOC ceases, the bus is once again assigned to the high-priority unit by the signal MGB. This is fed to one input of an AND circuit 39, the other input of which obtains the programme selector signal via an OR circuit 38. The output signal of the AND circuit 39 activates an access flip-flop 42, which feeds a BOC signal via its output to the logic circuit 20 to indicate that the bus is occupied. If the first type of signal remains from the programme selector, the output of the wait flip-flop 41 is immediately activated so that the circuit 21 is kept blocked and no EBG signal is sent for giving access to the low-priority units. The other type of signal from the programme selector 30 signifies that the high-priority unit can allow access for a low-priority unit. A flip-flop 43, which is activated by this signal, feeds a signal to the input of and AND circuit 6 in which a negation input is connected to the output of the flip-flop 42 so that it is blocked the whole time the high-priority processor uses the bus. The output of the AND circuit 46 is connected to an input of the OR circuit 47 which will send the output signal of the circuit 46 to the AND circuit 21. By activating the output signal of the circuit 46, and the generation of the REB signal taking place with a given delay after the BOC signal has ceased, due to the delay circuit 48, the REB signal does not occur until after the EBG signal has occurred at the output of the circuit 22, so that one of the low-priority units will be given access. The REB signal occurs, immediately afterwards which ensures that the high-priority unit is given direct access when the "bus occupied" signal BOC has ceased.
This is further explained in the time chart according to Figure 3. When the high-priority unit is working and there is no immediate need to use the bus again, there is no standing REB signal from the flip-flop 41. When the "bus occupied" signal BOC ceases, the output of the circuit 46 is activated with a ' time lag such that the REB signal does not occur until the EBG signal has had time to be sent to the low-priority processors. Immediately afterwards the circuit 21 is once again blocked by the REB signal, so that when the low- priority unit has completed its task and the BOC signal has ceased, the high- priority unit can take over the bus without delay. By the BOC signal ceasing, the register 11 is activated and the identity of the low-priority unit can be sent out. With the aid of the described arrangement it will be possible to assign the bus to the low-priority units during such periods where the program does not make necessary immediate acces for the high-priority unit, although it is ensured that the high-priority unit always has immediate access to the bus when so required.

Claims

CLAIM
Arrangement for apportioning priority for computers that contain processors of two types, a high-priority type which can itself determine its priority in relation to processors of a second low-priority type when using a common bus, such as to allow the low-priority type to use the bus also, if the high-priority processor does not have important tasks characterized in that the arrangement includes a first and a second logic circuit, the first logic circuit (20) having three inputs, the first for an input signal (RQB) which signifies a request for access from one of the low-priority units (3a-3h) the second for an input signal (REB) which signifies a request for access from the high-priority unit (1) and the third for an input signal (BOC) which occurs during the whole time the bus is used, the circuit (20) having two outputs on which a signal (EBG) occurs on the first one for assigning the bus a low-priority unit (3a-
' 3h) if only the first input has been activated, on the second output there occuring a signal (MGB) for assigning to the bus the high-priority unit, while the signal on the first output is inhibited, the second logic circuit (40) being with two outputs and two inputs, a first output which feeds the signal (REB) with the request for access from the high-priority unit to the second input of the first logic circuit, and a second output which feeds the signal (BOC) indicating that the bus is occupied, to the third input of the first logic circuit, there occuring a signal (REB) unconditionally on the first input on its activation, the signal (REB. denoting on the second input of the first logic circuit that the high-priority unit desires access, so that the assigning or granting signal (MGB) occurs on the second output of the first logic circuit, the second input of the second logic circuit on activation resulting in that the signal (REB) of a request for access for the high-priority units occurs with delay on the first output of the second logic circuit so that the signal (EBG) for granting or assigning the bus to a low- priority unit has time to occur, but the high-priority unit still has immediate access to the bus after termination of the work of the low-priority unit.
PCT/SE1985/000429 1984-12-12 1985-11-01 Arrangement for apportioning priority among co-operating computers WO1986003606A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
AU50932/85A AU580359B2 (en) 1984-12-12 1985-11-01 Arrangement for apportioning priority among co-operating computers
KR1019860700547A KR910003015B1 (en) 1984-12-12 1985-11-01 Arrangement for apportioning priority among co-operating computers
AT85905902T ATE45825T1 (en) 1984-12-12 1985-11-01 ARRANGEMENT FOR DISTRIBUTING PRIORITY BETWEEN TWO COMPUTERS.
BR8507112A BR8507112A (en) 1984-12-12 1985-11-01 SYSTEM FOR REPRESENTING PRIORITY BETWEEN COOPERANT COMPUTERS
DE8585905902T DE3572552D1 (en) 1984-12-12 1985-11-01 Arrangement for apportioning priority among co-operating computers
JP60505172A JPH0630086B2 (en) 1984-12-12 1985-11-01 Device for assigning priority among computers operating in parallel
FI862682A FI88549C (en) 1984-12-12 1986-06-24 Prioritetsfoerdelningsanordning Foer samarbetande datorer
NO86862764A NO170999C (en) 1984-12-12 1986-07-08 ARRANGEMENT FOR DISTRIBUTION OF PRIORITY FOR COMPUTERS
DK381686A DK165077C (en) 1984-12-12 1986-08-11 PRIORITY DISTRIBUTION CIRCUIT FOR CO-OPERATING COMPUTERS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE8406312A SE445861B (en) 1984-12-12 1984-12-12 PRIORITY DISTRIBUTION DEVICE FOR COMPUTERS
SE8406312-2 1984-12-12

Publications (1)

Publication Number Publication Date
WO1986003606A1 true WO1986003606A1 (en) 1986-06-19

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PCT/SE1985/000429 WO1986003606A1 (en) 1984-12-12 1985-11-01 Arrangement for apportioning priority among co-operating computers

Country Status (23)

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US (1) US4791563A (en)
EP (1) EP0205472B1 (en)
JP (1) JPH0630086B2 (en)
KR (1) KR910003015B1 (en)
AT (1) ATE45825T1 (en)
BR (1) BR8507112A (en)
CA (1) CA1241767A (en)
DE (1) DE3572552D1 (en)
DK (1) DK165077C (en)
EG (1) EG17290A (en)
ES (1) ES8702677A1 (en)
FI (1) FI88549C (en)
GR (1) GR852847B (en)
IE (1) IE57050B1 (en)
IT (1) IT1186409B (en)
MA (1) MA20594A1 (en)
MX (1) MX158467A (en)
NO (1) NO170999C (en)
NZ (1) NZ214010A (en)
PT (1) PT81612B (en)
SE (1) SE445861B (en)
TR (1) TR22658A (en)
WO (1) WO1986003606A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0284094A2 (en) * 1987-03-26 1988-09-28 Bull HN Information Systems Inc. Tandem priority resolver
EP0444711A2 (en) * 1990-03-02 1991-09-04 Fujitsu Limited Bus control system in a multi-processor system
EP0671692A1 (en) * 1994-02-24 1995-09-13 Hewlett-Packard Company Fast pipelined distributed arbitration scheme
US6374319B1 (en) 1999-06-22 2002-04-16 Philips Electronics North America Corporation Flag-controlled arbitration of requesting agents

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2635639B2 (en) * 1987-12-28 1997-07-30 株式会社東芝 Data processing device
JP2635995B2 (en) * 1988-05-18 1997-07-30 株式会社日立製作所 System with processor
JPH0289149A (en) * 1988-09-26 1990-03-29 Matsushita Electric Ind Co Ltd Bus priority device
DE69030640T2 (en) * 1989-11-03 1997-11-06 Compaq Computer Corp Multiprocessor arbitration in single processor arbitration schemes
US5081578A (en) * 1989-11-03 1992-01-14 Ncr Corporation Arbitration apparatus for a parallel bus
US5414818A (en) * 1990-04-06 1995-05-09 Mti Technology Corporation Method and apparatus for controlling reselection of a bus by overriding a prioritization protocol
US5297277A (en) * 1990-08-31 1994-03-22 International Business Machines Corporation Apparatus for monitoring data transfers of an oemi channel interface
JPH06110825A (en) * 1992-09-30 1994-04-22 Nec Corp Common bus control system
US5740383A (en) * 1995-12-22 1998-04-14 Cirrus Logic, Inc. Dynamic arbitration priority
FR2894696A1 (en) * 2005-12-14 2007-06-15 Thomson Licensing Sas METHOD FOR ACCESSING A DATA TRANSMISSION BUS, DEVICE AND CORRESPONDING SYSTEM

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4059851A (en) * 1976-07-12 1977-11-22 Ncr Corporation Priority network for devices coupled by a common bus
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
US4121285A (en) * 1977-04-01 1978-10-17 Ultronic Systems Corporation Automatic alternator for priority circuit
US4151592A (en) * 1975-10-15 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Data transfer control system
SE414087B (en) * 1977-02-28 1980-07-07 Ellemtel Utvecklings Ab DEVICE IN A COMPUTER SYSTEM FOR SENDING SIGNALS FROM A PROCESSOR TO ONE OR MANY OTHER PROCESSORS WHERE PRIORITY SIGNALS ARE SENT DIRECTLY WITHOUT TIME DELAY AND OPRIORATED SIGNALS ORDER ...
US4302808A (en) * 1978-11-06 1981-11-24 Honeywell Information Systems Italia Multilevel interrupt handling apparatus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4096569A (en) * 1976-12-27 1978-06-20 Honeywell Information Systems Inc. Data processing system having distributed priority network with logic for deactivating information transfer requests
US4257095A (en) * 1978-06-30 1981-03-17 Intel Corporation System bus arbitration, circuitry and methodology
US4271467A (en) * 1979-01-02 1981-06-02 Honeywell Information Systems Inc. I/O Priority resolver

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151592A (en) * 1975-10-15 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Data transfer control system
US4059851A (en) * 1976-07-12 1977-11-22 Ncr Corporation Priority network for devices coupled by a common bus
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
SE414087B (en) * 1977-02-28 1980-07-07 Ellemtel Utvecklings Ab DEVICE IN A COMPUTER SYSTEM FOR SENDING SIGNALS FROM A PROCESSOR TO ONE OR MANY OTHER PROCESSORS WHERE PRIORITY SIGNALS ARE SENT DIRECTLY WITHOUT TIME DELAY AND OPRIORATED SIGNALS ORDER ...
US4121285A (en) * 1977-04-01 1978-10-17 Ultronic Systems Corporation Automatic alternator for priority circuit
US4302808A (en) * 1978-11-06 1981-11-24 Honeywell Information Systems Italia Multilevel interrupt handling apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0284094A2 (en) * 1987-03-26 1988-09-28 Bull HN Information Systems Inc. Tandem priority resolver
EP0284094A3 (en) * 1987-03-26 1990-04-25 Honeywell Bull Inc. Tandem priority resolver
EP0444711A2 (en) * 1990-03-02 1991-09-04 Fujitsu Limited Bus control system in a multi-processor system
EP0444711A3 (en) * 1990-03-02 1994-07-20 Fujitsu Ltd Bus control system in a multi-processor system
US5526495A (en) * 1990-03-02 1996-06-11 Fujitsu Limited Bus control system in a multi-processor system
EP0671692A1 (en) * 1994-02-24 1995-09-13 Hewlett-Packard Company Fast pipelined distributed arbitration scheme
US5519838A (en) * 1994-02-24 1996-05-21 Hewlett-Packard Company Fast pipelined distributed arbitration scheme
US6374319B1 (en) 1999-06-22 2002-04-16 Philips Electronics North America Corporation Flag-controlled arbitration of requesting agents

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EG17290A (en) 1989-06-30
BR8507112A (en) 1987-03-31
DK381686D0 (en) 1986-08-11
SE445861B (en) 1986-07-21
JPS62501039A (en) 1987-04-23
IT1186409B (en) 1987-11-26
JPH0630086B2 (en) 1994-04-20
MA20594A1 (en) 1986-07-01
FI88549B (en) 1993-02-15
DK381686A (en) 1986-08-11
KR870700156A (en) 1987-03-14
ES549805A0 (en) 1986-12-16
MX158467A (en) 1989-02-03
IE853053L (en) 1986-06-12
EP0205472B1 (en) 1989-08-23
CA1241767A (en) 1988-09-06
PT81612A (en) 1986-01-02
NO862764L (en) 1986-07-08
GR852847B (en) 1985-12-02
PT81612B (en) 1987-09-30
EP0205472A1 (en) 1986-12-30
FI862682A0 (en) 1986-06-24
NO862764D0 (en) 1986-07-08
ES8702677A1 (en) 1986-12-16
DE3572552D1 (en) 1989-09-28
FI862682A (en) 1986-06-24
NO170999C (en) 1993-01-06
DK165077B (en) 1992-10-05
TR22658A (en) 1988-02-08
US4791563A (en) 1988-12-13
NZ214010A (en) 1988-10-28
ATE45825T1 (en) 1989-09-15
SE8406312L (en) 1986-06-13
DK165077C (en) 1993-02-22
IT8523124A0 (en) 1985-12-06
KR910003015B1 (en) 1991-05-15
FI88549C (en) 1993-05-25
IE57050B1 (en) 1992-04-08
NO170999B (en) 1992-09-28
SE8406312D0 (en) 1984-12-12

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