WO1983001120A1

WO1983001120A1 - Doppler dropout compensating signal conditioning circuit

Info

Publication number: WO1983001120A1
Application number: PCT/US1981/001300
Authority: WO
Inventors: Tractor Co. Caterpillar
Original assignee: Riebschlager, Jeffrey, J.
Priority date: 1981-09-24
Filing date: 1981-09-24
Publication date: 1983-03-31
Also published as: IT1190998B; EP0088755A1; BR8109043A; JPS58501519A; ZA824408B; IT8223218A0

Abstract

A dropout compensating signal conditioning circuit (10) especially well suited for conditioning signals utilized in doppler shift monitoring apparatus. The circuit (10) includes phase-locked loop (32) responsive to an input signal at (30) for generating a second signal at (44) of a frequency substantially directly proportional to the input signal. This circuit (10) provides an output on line (75) which tracks the input at (12) with great precision and is free from the occasional absence of one or more periods of the input signals, which is known as dropout.

Description

Descriptiofi

DOPPLERDROPOUTCOMPENSATING.SIGNALCONDITIONINGCIRCUIT

Technical Field

This invention relates to circuits for providing dropout compensation and more particularly to circuits for providing dropout compensation for doppler shift measuring devices.

Background Art

Several varieties of velocity detectors and certain other devices include an element for transmitting a signal, an element for receiving the signal, and an element for monitoring the frequency difference between the signal as transmitted and the signal as received. From this frequency difference, termed "doppler shift" in the art, the velocity of the transmitter can be determined relative to the receiver or to a reflecting surface. Since the measurement made by such devices is entirely dependent upon this doppler shift, it is important to ensure that the signal as received accurately represents a true doppler shift of the signal as transmitted. in certain applications this reflected signal can periodically become rather weak or entirely non-existent. For example, where the transmitter is a vehicle mounted ultrasonic signal generator and the ground is utilized as the reflector, the^" attenuation of the signal from transmitter to receiver is typically several orders of magnitude. Where there is an irregularity in the reflector, a depression in the ground, for instance, the attenuation of the signal can be virtually complete. In such cases the reflected signal can become undetectable for one or more periods. This condition of undetectability is known as "dropout". any existing doppler effect type devices make no provision for dropout and, as a consequence, provide an erroneous output during the occurrence of this condition. Other systems do incorporate dropout compensation circuits, but these circuits tend to render the system sluggish in response to changes in the magnitude of the doppler shift.

The present invention is directed to overcoming one or more of the problems as set forth above.

Disclosure Of The Invention

In one aspect of the present invention a signal conditioning circuit includes means for receiving a cyclical input signal. Means responsive to said input signal is provided for generating an output signal of a frequency substantially directly proportional to the cyclical input signal. Means is further provided for preventing dropout in the output signal for no more than a preselected period of time during the occurrence of dropout in the input signal and for substantially preventing dropout of said input signal from decreasing the frequency of the output signal during the existence of said dropout condition. Several classes of electrical devices track cyclical signals for one purpose or another. Many of these devices, especially doppler shift detectors, suffer impaired performance due to the occasional absence of one or more periods of the input signal. This absence is known as "dropout".

It has been found^* that this problem can be overcome by the generation of a synthetic second signal, the frequency of which is substantially equivalent to that of the cyclical input signal. Dropout in the synthetic second signal is avoided through the use of suitable electronics as is described below. Further, significant deviations of the output signal from the input signal at a time immediately following termination of the dropout condition is also avoided. The synthetic second signal can be utilized directly as a replacement for the input signal or can be combined with the input signal to establish an output signal which is substantially free from all dropout.

Brief Description Of The Drawings

For a better understanding of the present invention, reference may be had to the accompanying drawings in which:

Fig. 1 is a schematic circuit diagram of the best known embodiment of the present invention; and Fig. 2 is a schematic circuit diagram of a second embodiment of the present invention.

It is to be understood that the drawings are not intended as a definition of the invention but are provided for the purpose of illustration only.

Best Mode For Carrying Out The Invention

Referring to the drawings, a signal conditioning circuit embodying certain of the principles of the present invention is generally indicated by the reference symbol 10. It should be understood that the following detailed description of the signal conditioning circuit 10 relates to the best presently known embodiment of this advance. The signal conditioning circuit 10 can assume numerous other embodiments, as will become apparent to those skilled in the art, without departing from the principles of the described embodiments. In the preferred embodiment, the signal conditioning circuit 10 receives a cyclical input signal subject to dropout and generates from this input signal an output signal. During those periods in which the input signal is in a condition of dropout the output signal remains at a substantially constant frequency, this frequency being substantially equivalent to the frequency of the input signal at the time the dropout commenced. By use of the term "equivalent" what is meant is "equal to or varying from by a fixed constant of proportionality".

In the preferred embodiment, the signal conditioning circuit 10 includes four major components. The first of these is means 32 for generating a second signal normally^* equivalent to the input signal. The second of the prime components is means 66 for detecting dropout of the input signal. This dropout detecting means 66 preferably receives two inputs which are, respectively, equivalent to the input signal and the second signal. The dropout detecting means 66 assumes a condition of dropout detection in response to a fraction of a period of the second signal occurring without a corresponding fraction of a period of the input signal being detected. The third of the major aspects of the signal conditioning circuit 10 is means 69 for freezing the frequency of the second signal in response to the occurrence of dropout in the input signal. This second signal freezing means 69 is controlled by the dropout detecting means 66. Further ^* included is means 63 for rendering the frequency of the second signal substantially equal to zero in response to the condition of dropout continuing for more than a preselected period of time.

¹ K-JCΛ More specifically, as shown in Fig. 1, an input 12 serves as a means for receiving a cyclical input signal. This input signal can be either a pulse train or wave train, preferably a square wave train, and should be substantially free from noise. Suitable electronics (not shown) , well known to those skilled in the art, can be provided for filtering noise from the input signal prior to applying the input signal to the signal conditioning circuit 10. This input signal may represent the doppler shift of one wave train relative to another or any other cyclical signal subject to dropout.

The input 12 is connected to a first means 14 for multiplying pulses. Preferably, this first pulse multiplying means 14 is a first pulse doubler which converts waves or pulses of sufficiently great duration into two pulses, one of these two pulse occurring at each transition of the input signal.

In the preferred embodiment, as shown in Fig. 1, the first pulse doubler 14 includes a first exclusive OR gate 16 and a first flip-flop 18, preferably a type D flip-flop. A first input 20 of the exclusive OR gate 16 receives the input signal from the input 12. A second input 22 of ^"the exclusive OR gate 16 is grounded through a .001 microfarad first capacitor 24 and also is connected through a 1.2 k ohm first resistor 26 to the Q output of the first flip-flop^"18. The output 28 of the exclusive OR gate 16, which also serves as the output of the first pulse multiplying means 14, is connected to the clock CLK of the flip-flop 18. The data input D and the Q output are connected one to the other, and the direct set and reset S,R are each grounded.

*ςQ ϊ.ϊ-A , The input 12 is also connected to a signal input terminal 30 of a means 32 for generating a second signal of a frequency substantially proportional to the input signal. Preferably, the second signal is directly proportional to the input signal. This second signal generating means 32 can be a phase-locked loop or the equivalent. Preferably, as shown in the corresponding detail of Fig. 2, the second signal generating means 32 includes a phase comparator 34 and ^an oscillator 36 forming a phase-locked loop 37. The oscillator 36 is preferably a voltage controlled oscillator. The phase comparator 34 has first and second inputs 3.8,39 and an output 40. The oscillator 36 has an input 42 and an output 44. The signal input terminal 30 is connected to the first input 38 of the phase comparator 34. A first circuit 46 connects the oscillator output 44 to the phase comparator second input 38. A second circuit 48 connects 'the phase comparator output 40 to the oscillator input 42. Th*² first circuit 46 includes a second type D flip-flop 50 which preferably is identical to the first flip-flop 18. The clock CLK of the second flip-flop 50 is connected to the oscillator output 44. The Q output of the second flip-flop 50 is connected to the second input 38 of the phase comparator 34.

The second flip-flop 50 serves as a means for dividing the frequency from input to output. In the preferred-embodiment, the factor of division is two. It is preferred that the factor of multiplication of the first pulse multiplying means 14 and the factor of division of the dividing means 50 be equal.

Referring again to Fig. 1, which shows the preferred embodiment, the second circuit 48 includes a first transmission gate 52 having a control terminal 54 and an input and output 56,58. In the preferred embodiment the first transmission gate 52 is closed in

OMPI , V V//IIPPOO response to a signal being applied to the control terminal 54 and is open in response to no signal being applied to the control terminal 54. The first transmission gate input 56 is connected to the phase comparator output 40 and the first transmission gate output 58 is connected through a 100 k ohm second resistor 60 to the oscillator input 42. As shown in Fig. 1, the oscillator input 42 is also connected, through a series connection of 47 microfarad second capacitor 62 and a 1.2 k ohm third resistor 64, to ground.

A second transmission gate 52' having an input 56', an output 58' and a control terminal 54' is connected by its input 56* to the^'."oscillator input 42. The output 58' of this second transmission gate 52' is grounded through a 100 k ohm fourth resistor 65 such that the charge on the second capacitor 62 can be bled off through the fourth resistor 65 in response to the second transmitting gate 52' being closed. Preferably, the first and second transmission gates 52,52' are identical and are each one-quarter of an MC 14066B manufactured by Motorola Semiconductor Products, Inc. of Austin, Texas.

Further included in the signal conditioning circuit 10 is means 66 for detecting dropout Of the input signal. Preferably, this dropout detecting means 66 includes a shift register 67 such as, for example, an eight s^'tage MC14015B dual four bit static shift register manufactured by Motorola Semiconductor Products, Inc. of Austin, Texas. It must be emphasized that any shift register configured in a manner analogous to that described below can also be utilized as an element of the dropout detecting means 66. The dropout detecting means 66, in conjunction with the first transmission gate 52, forms the nucleus of means 69 for substantially preventing the occurrence of dropout in the input signal from -commencing a change or aberration, such as rapid frequency decay, in the second signal. By use of the phrase "substantially preventing the occurrence of dropout in the input signal from commencing a change in the output signal", what is meant is that no change in the output signal occurs except that change due to discharge of the second capacitor 62 through the very high input impedance of the oscillator 36. This change in the output is, of course, typically insignificant. Both clocks C K_A and CLK- of the shift register 67 are connected to the oscillator output 44, and both resets- R ,P are connected to the output 28 of the first exclusive OR gate 16. The first data input D is supplied with a constant input +V. The second data input D_β is connected to the fourth output stage Q4, of the shift register 67.

The first output stage QI, of the shift register 67 is applied to a second input 70 of a second exclusive OR gate 72. The first input 68 of the second exclusive OR gate 72 is supplied with a constant input +V. The output 74 of the second exclusive OR gate 72 is applied to the control terminal 54 of the first gate 52. The shift register 67, the second exclusive OR gate 72, and the first transmission gate 52 form a third circuit 73 for controlling the application of the phase comparator output 40 to the oscillator input 42. -This third circuit is the preferred form of the previously discussed means 69 for freezing the frequency of the second signal in response to dropout of the input signal. This third circuit 73 has first and second controlling inputs 91,92 which are, respectively, the oscillator output 44 and the first pulse multiplying means output 28.

OKPI The seventh output stage¹ Q3_β of the shift register 67 is applied to the control terminal 54' of the second transmission gate 52*. As will be described subsequently, the second transmission gate 52' is used to terminate the generation of the second signal a preselected time following the initiation of dropout. The shift register 67 and the second transmission gate 52' form the previously discussed means 63 for rendering the frequency of the second signal substantially equal to zero in response to the condition of dropout continuing for more than a preselected period of time.

The oscillator output 44 is also connected to a second means 14' for multiplying pulses. Preferably, this second pulse multiplying means 14' is a second pulse doubler having a third exclusive OR gate 16' and is otherwise identical in makeup to the first pulse doubler 14. The output 28' of the third exclusive OR gate 16' of the second pulse multiplying means 14'is the signal conditioning circuit output 75.

The exclusive OR gates 16,16' of the two pulse doublers 14,14' and the second exclusive OR gate 72 can each be one-quarter of a MC 14070B, manufactured by Motorola Semiconductor.Products, Inc. of Austin, Texas. The type D flip-flops 18,50 can each be one-half of a MC 14013B also manufactured by Motorola. The phase-locked loop 37 can be a MC 14046B and the shift register can be a MC 14015B, both of which are also manufactured by Motorola. A second embodiment of the signal conditioning circuit 10 is set forth in Fig. 2. This second embodiment has an input 12 connected to a first means 14 for multiplying pulses which, as shown in Fig. 2, can be identical to that of the preferred embodiment. The input 12 is also connected to a signal input terminal 30 of a means 32 for generating a second

OMPI signal of a frequency substantially directly proportional to the input signal. This second signal generating means 32 can be identical to the phase-locked loop 37 of the preferred embodiment. The first circuit 46 of this embodiment is also preferably identical to that previously described. As shown in Fig. 2, the second circuit 48 of this embodiment differs from that of the first embodiment in that the first and second transmission gates 52,52' are deleted, these being replaced with closed circuits. In this embodiment it is preferred that the second resistor 60 have a value of 510 k ohms, the third resistor 64 have a value of 1.2 "k ohms, and the second capacitor 62 have a value of 10 microfarads. The second embodiment further includes means

66 for detecting dropout. This dropout detecting means 66 of the second embodiment preferably includes a shift register 67 which preferably is composed of two flip-flops. These flip-flops can be identical to those used elsewhere in this embodiment. As shown, both shift register clock inputs CLK are connected_, to the oscillator output 44. Both resets R are connected to the output of the first pulse doubler 14. The data input D of the first flip-flop is connected to a constant voltage source and the Q output of the first shift register flip-flop is connected to the data input D of -the second shift register flip-flop. The shift register 67, in conjunction with the first pulse multiplying means 14, forms the dropout ^"detector 66. The shift register 67 has a first output terminal 71 which provides a dropout signal in response to said input signal being in a condition of dropout for a preselected period of time.

OMPI A signal selector 76 is provided for providing a single output signal at a signal selector output 77, this output being selected from one of the signal conditioning circuit input signal and the conditioned phase-locked loop signal from the Q output of the second flip-flop 50. This signal selector 76 can, of course, assume numerous forms. Preferred is an arrangement of two AND gates 78,80, the outputs of each providing one of the two inputs to a fourth exclusive OR gate 82. The inputs to the first AND gate 78 are the input signal from the signal conditioning circuit input 12 and the Q^" output from the second flip-flop of the shift register. The inputs to the second AND gate 80 are the Q output from the second flip-flop and the shift register output terminal 71.

The signal selector output 77 is applied to means 84 for multiplying the input and for achieving a cqnstant pulse width output. This multiplying and constant pulse width obtaining means 84 preferably includes of a third and a fourth pulse multiplier

86,88, these being series connected. This, yields a net multiplication of four. Each of these pulse multipliers includes means, preferably a precision monostable, for providing a consistent pulse width. The second of these pulse multipliers 88 can be identical to the first 86 with the exception that the pulse width of the second should be significantly less, preferably by a factor of two, than that of the first. This can be achieved by substitution of the timing resistors in the monostables. A buffer 90 can be included at the output of the multiplying and constant pulse width obtaining means 84. The output of this buffer 90 is the signal conditioning circuit output 75. Industrial Applicability

The operation of the preferred embodiment of the dropout compensating signal conditioning circuit 10 will now be detailed. The first pulse multiplying means 14 produces a pulse at its output 28 for each transition of the doppler input as applied to the input 12. Since there are two transitions per cycle of the doppler input signal, two pulses are produced at the first pulse multiplying means output 28. The input signal applied at input 12 is also applied to the signal input terminal 30, and, hence to the phase comparator first input 38 of the second signal generating means 32. Initially, however, there is no signal applied to the second input terminal 39 of the phase comparator 34. This establishes an imbalance between these inputs 38,39 resulting in the phase comparator 34 establishing an output of lo.gic high pulses. These logic high pulses charge the second capacitor 62. This causes the voltage at the oscillator input 42 to rise and, consequently, produce an output of increasing frequency. The logic_, high pulses from the phase comparator 34 will continue to charge the second capacitor 62 until the frequency of the signal applied to the second phase comparator input 39 exceeds that of the first phase comparator input

38. At this point, the phase comparator 34 will output logic low pulses causing the second capacitor 62 to discharge.^" The output frequency of the oscillator 36 will then drop and the process will repeat until the phase-locked loop has managed to lock itself onto the phase and frequency of the doppler input signal applied at input 12. At this point the output of the oscillator 36 will be twice that of the doppler input signal. This factor of two difference is due to the divide by two effect of the second flip-flop 50.

OMP The first pulse multiplying means 14 and the shift register 67 form a means 66 for detecting dropout. ^"With the oscillator output 44 being applied to both clocks CLK of the shift register 67, and the output 28 of the first pulse doubler 14 being applied to both resets R_A, R_., the outputs of the shift register 67 are always low so long as there is no dropout in the input signal. In response to dropout, however, an output does occur. In the dropout situation, no reset signals are applied to the shift register, thus allowing the output stages QI, - Q3„ to sequentially store high signals. As the signal at the oscillator 'output 44 will have a frequency substantially double that of the input, the dropout of the input signal must occur for at least 3 1/2 periods of the signal to allow the seventh stage of the shift register 67, Q3B, to go to the logic high state. The first stage QI, of the shift register 67 will, of course, go to the logic high state one-half of a phase following dropout of the inut signal.

The first transmission gate 52 of the second circuit 48 provides a highly advantageous aspect to the operation of the second signal generating means 32. In the non-dropout situation the second exclusive OR gate 72 applies a signal to the control terminal 54 of the first transmission gate 52, closing the transmission gate -52 and*, hence, closing the second circuit 48. This permits the phase comparator output 40 to charge and discharge the second capacitor 62, which itself controls the oscillator 36. In response to the dropout situation the first stage QI, clocks high and the output of the second exclusive OR gate 72 terminates. Withdrawing the signal, which until then was applied to the control terminal 54 of the first transmission gate 52 disables this gate, opening the second circuit 48.

The second capacitor 62 can then discharge only through the oscillator input 42. As the Oscillator 36 has a very high input impedence, charge depletion of the second capacitor 62 will be negligible during dropout. This results in output of the phase locked loop 37 being initially frozen during dropout, thereby preventing the output frequency being "pulled down" by the phase comparator due to absence of the input signal,

It is preferred that the second signal generating means 32 not continue to provide an output indefinitely upon absence of the input signal. This feature is provided by the second transmission gate 52' and the electronics associated with it. The second transmission ga-te 52' is enabled when the seventh stage Q3-, of the shift register is clocked high. As previously stated, the seventh stage will clock high after 3 1/2 phases of input signal dropout. In response to the second transmission gate 52' being enabled, the second capacitor 62 will discharge through the fourth resistor 65 to ground. The values of the resistors are such that the output of the phase-locked loop 37 will terminate about 2.5 seconds following the termination of the signal input at input 12. Of course, resumption of an input will open the second transmission gate 52¹. In many applications dropouts rarely occur for more than two cycles. It was this that influenced the use αf the 3.5 cycle dropout for control of the second transmission gate 52'. If it is desired that the second transmission gate 52 not be enabled for a longer period of time following dropout, a shift register having a greater number of stages can be substituted for that of this embodiment.

The output of the second signal generating means 32 is taken directly from the oscillator output 44 and hence is twice that of the input doppler signal. The second means 14' for multiplying pulses

OMPI applies a further multiplication Of two yielding a total multiplication of four for the dropout compensating circuit 10 as a whole.

It should be noted that in this preferred embodiment the output signal is at all times taken from and is directly proportional to the oscillator output 44. The phase-locked loop 37 tracks the input signal with great accuracy and in the dropout situation the output of the second signal generating means 32 is frozen at the frequency of the input signal at the time immediately preceeding the dropout.

The operation of the second embodiment of the dropout compens-ating circuit differs somewhat from that of the preferred embodiment. The first and second transmission gates 52,52* of the preferred embodiment do not exist in the second embodiment. As a result, the output of the phase comparator 34 decreases during dropout due to the absence of the input signal. Even though this embodiment does not- include the second transmission gate 52' of the preferred embodiment, the phase-locked loop 37 will not continuously provide an output once the input signal has been removed. This is due to the fact that the phase comparator 34 controls the second capacitor 62 even in the dropout situation. Hence after a sufficiently great time the output will go to zero, matching the absence of input.

The second embodiment also includes a signal selector 76. This signal selector 76 applies only one of the input signal and the oscillator output signal to the signal conditioning circuit output 75. In response to the input signal being free from dropout the NOT Q output of the shift register 67 is in a logic high condition. As this NOT Q output is applied in conjunction with the input signal from INPUT 12 to the first AND gate 78, the first AND gate 78 will provide an output for each existing cycle of the input signal.

OMPI In response to the input signal tfeing in a dropout condition, the second of the inputs to the first AND gate 78 remains low and the first AND gate 78 will provide no output to the exclusive OR gate 82. Turning now to the second AND gate 80, in response to the input signal being in a dropout-free condition the Q output of the shift register 67' is in a logic low condition and the second AND gate 80 can provide no output. In a dropout condition, however, the Q output of the shift register 67 attains a logic high state and the output of the second AND gate 80 will follow the Q output of the second flip-flop 50.

Thus, he second embodiment of the signal conditioning circuit 10 provides an output proportional to the input signal when the input signal is free from dropout and provides an output proportional to the phase-locked loop output in response to the input being in a dropout condition.

It should be understood that the signal conditioning circuit can differ as is known in the art without departing from the invention. Other aspects, objects, advantages and uses of this invention can be obtained from a study of the drawings, the disclosure and the appen^'ded claims.

Claims

Claims 1

1. A signal conditioning circuit (10) comprising: means (12) for receiving a cyclical input signal; means (32) for generating a second signal of a frequency substantially directly proportional to said input signal and for preventing for a preselected period of time the occurrence of dropout in said input signal from establishing a corresponding dropout in said second signal, said means (32) being responsive to said input signal..

2. The signal conditioning circuit (10) , as set forth in claim 1, wherein said second signal generated by said generating and preventing means (32) remains, ^'during dropout of said input signal, at a substantially constant frequency, this frequency being equal to that of the second signal at the time of dropout.

3. A signal conditioning circuit (10) comprising: means (12) for receiving a cyclical input signal; means (32) for generating a dropout free second signal, said second signal normally being of a frequency substantially proportional to -said input signal; and, means (69,76) for establishing an output signal, said output signal being of a frequency proportional to said input signal in response to said input signal being in a dropout-free condition, and said output signal being of a frequency proportional to said second signal in response to said input signal being in a condition of dropout.

- 2 ^hA

OMPI

4. The signal conditioning circuit (10), as set forth in claim 3, wherein said output signal establishing means (69,76) includes: means (69) for detecting dropout of said input signal, said dropout detecting means (69) having first and second conditions, said dropout detecting means (69) adopting said first condition in response to said input signal being free from dropout and adopting said second condition in response to said input signal being in a condition of dropout; and a signal selector (76) , said signal selector (76) having a plurality of inputs and an output (77) , said signal selector (76) receiving at one of said inputs said input signal, and receiving at another of said inputs said second signal, said signal selector (76) being adapted to apply said input signal to said signal selector output (77) in response to said dropout detecting means (69) being in said first condition and being adapted to apply said second signal to said _ signal selector output (77) ^"in response to said dropout detecting means (69) being in said second condition.

5. The signal conditioning circuit (10), as set forth in claim 4, wherein said dropout detecting - means (69) includes a shift register (67) having a first output terminal (71) , said shift register (67) being* adapted to establish a dropout signal at said first output terminal (71) in response to said input signal being in a condition of dropout for a preselected period of time.

6. A signal conditioning circuit (10) comprising: means (12) for receiving a cyclical input signal; means (32) for generating a second signal, said second signal normally being of a frequency substantially proportional to said input signal; and means (69) for substantially preventing any alteration in the frequency of said second signal for a preselected period of time following dropout of said input signal.

7. A signal conditioning circuit (10) , as set forth in claim 6, wherein said second signal generating means (32) includes a phase-locked loop (37) .

8. A "signal conditioning circuit . (10) , as set forth in claim 7, wherein said phase-locked loop (37) includes: a phase comparator (34) having a first input (38) , a second input (39) , and an output (40) , said phase comparator (34) being responsive to the frequency difference between signals applied to said first and -• second inputs (38,39); and, an oscillator (36) having an input (42) and an output (44) .

9. A signal conditioning circuit (10), as set forth in claim 8, wherein said cyclical input signal is applied to said phase comparator first input (38) , and wherein a first circuit (46) connects said oscillator output (44^*) to said phase comparator second input (39) , and wherein a second circuit (48) connects said phase comparator output (44) to said oscillator input (42) .

10. The signal conditioning circuit (10), as set forth in claim 9, wherein said means (69) for substantially preventing alterations in the frequency of said second signal includes means (66) for detecting dropout of said input signal and means (73) for

OMPI substantially freezing the frequency of said second signal for a preselected period of time in response to input signal dropout being detected by said dropout detecting means (66) .

11. The signal conditioning circuit (10) , as set forth in claim 10, wherein said detecting and freezing means (66,73) includes a third circuit (73) having first and second inputs (91,92) and^'a first output (Q1_A) / said first output (Ql_A) having first and second states, said first input being in communication with said input signal and said second input being in communication with said second signal, said third circuit (73) being of a construction sufficient for changing said first output from one of said first and second states -to the other of said first output first and second states in response to the occurrence of a first preselected number of periods of said second signal during dropout of said first signal.

12. The signal conditioning circuit ^'(10) , as set forth in claim 11, wherein said first preselected number is less than 1.

13. The signal conditioning circuit (10), as set forth in claim 12, wherein said third circuit (73) includes a shift register (67) , said shift register (67) receiving said first input (91) at a clock terminal (CLK) and receiving said second input at a reset terminal (R.) .

14. The signal conditioning circuit (10), as set forth in claim 12, wherein said third circuit first output (QI_*) controls a first switch (52) , said first switch (52) being in series with said second circuit

(48) , said first switch (52) being maintained closed in response to said third circuit f_irst output (74) being at one of said first and second states and said first switch (52) being maintained open in response to said third circuit first output (74) being at the other of 5 said first and second states.

15. The signal conditioning circuit (10), as set forth in claim 12, wherein said third circuit further includes a second output (Q3_β) , said second

10 output (Q3_β) having first and second states, said third circuit (73) being of a construction sufficient for changing from one of said second output first and second states to the other of said second output first and second states in response to the occurrence of a 5 second preselected number of periods of said signal during dropout of said second signal, said second preselected number being of greater magnitude than said first preselected number.

0 16. The signal conditioning circuit (10), as set forth in claim 15, wherein said third circuit

^•- - second output (Q3_β) controls a second switch (52'), said second switch (52') being connected to said oscillator input (42) such that when closed the 5 oscillator input (42) is drained, said second switch (52) being in an open condition in response to one of said -second output first and second states and being in a closed condition in response to the other of said second output first and second states. 0

17. The signal conditioning circuit (10), as set forth in claim 6, wherein said means (69) for substantially preventing alterations in the frequency of said second signal includes means (66) for detecting 5 dropout. of said input signal and means (73) for substantially freezing the frequency of said second

OMPI signal for a preselected period of^" time in response to input signal dropout being detected by said dropout detecting means (66) .

18. The signal conditioning circuit (10), as set forth in claim 17, further including means (63) for reducing the frequency of the second signal to substantially zero in response to dropout of said second signal existing for a predetermined period of time.

19. A signal conditioning circuit (10) , as set forth in claim 17, wherein said second signal generating means (32) includes a phase-locked loop (37) .

20. A signal conditioning circuit (10), as set forth in claim 19, wherein said phase-locked loop (37) includes: a phase comparator (34) having a first input_s (38) , a second input (39) , and an output (40) , said phase comparator (34) being responsive to the frequency difference between signals applied to said first and second inputs (38,39) ; and, an oscillator (36) having an input (42) and an output (44) .

21. A signal conditioning circuit (10) , as set forth in claim 20, wherein said cyclical input signal is applied to said phase comparator first input (38) , and wherein a first circuit (46) connects said oscillator output^' (44) to said phase comparator second input (39) , and wherein a second circuit (48) connects said phase comparator output (44) to said oscillator input (42) .