WO1981001225A1

WO1981001225A1 - Clock derivation circuit for double frequency encoded serial digital data

Info

Publication number: WO1981001225A1
Application number: PCT/US1980/001360
Authority: WO
Inventors: T Woodward
Original assignee: Burroughs Corp
Priority date: 1979-10-19
Filing date: 1980-10-14
Publication date: 1981-04-30
Also published as: JPS56501469A; US4313206A; DE3071038D1; EP0044311B1; JPH0157854B2; EP0044311A1; EP0044311A4

Abstract

A circuit for extracting clocking signals for double frequency encoded transition-event waveforms. The incoming waveform is fed to a digital delay line (10) and delayed by 1/4, 1/2 and 3/4 of the incoming waveform, respectively. Transitions in the incoming waveform are detected by comparing the output of the first delay line tap with the incoming waveform and simultaneously comparing the outputs of the second and third delay taps, thus generating first and second transition waveforms (S5 and S7). The two generated transition waveforms are used to form a composite clock to toggle a nip-flop (18). The outputs of flip-flop are then gated with the first and second generated transition waveforms, to produce two clocking signals (S12 and S13), the first clocking signal providing pulses commencing at the incoming waveform's guaranteed transitions, the second clocking signal providing pulses commencing one-half bit cell after the incoming waveform's guaranteed transitions.

Description

TITLE

CLOCK DERIVATION CIRCUIT FOR DOUBLE FREQUENCY ENCODED SERIAL DIGITAL DATA

BACKGROUND OF THE INVENTION Serial digital data is frequently transmitted using a self-clocking encoding. The basic idea behind these self-clocking codes is to guarantee that a certain minimum number of digital "events" (pulses or transitions in level) occur within the digital waveform. These "guaranteed" events can then be used to establish and reconstruct frequency and phase of the clocking signals which were used to encode and transmit the data.

"Double frequency" encoding is the simplest of the self-clocked encodings and has many variants; two of these variants are known as "frequency modulated" (FM) and "biphase". FM and biphase encodings differ slightly, but have as a common characteristic the guarantee that at least one, but no more than two digital events occur per bit cell in the digital waveform. A bit cell is that portion of the waveform which is generated by one cycle of the basic digital clock and contains a single binary 0 or binary 1. The

OMPI presence or absence of the second (non-guaranteed) event depends upon the data being encoded.

Examples of FM and biphase encoding are illustrated in Figs. 1 and 2, respectively. In the given example of FM (Fig. 1), pulses are the events of interest. In the given example of biphase, transitions of level are the events of interest.

In FM encoding (Fig. 1), a binary 1 is represented by two consecutive events occurring one-half bit cell apart, with a bit cell defined as the time between two guaranteed transitions. Binary 0 is represented by a single event at the beginning of a bit cell.

In biphase encoding (Fig. 2), the guaranteed event is a transition in level occurring in the middle of each bit cell. A binary 1 is distinguished from a binary 0 by the relative phase of the waveform surrounding the guaranteed transition. Thus, in the example shown in Fig. 2, a binary 1 is represented by — ___ and a binary 0 is represented by s

Transitions occurring between the guaranteed transitions are required whenever two consecutive bit cells carry the same binary data value.

As will be obvious to those skilled in the art, an FM pulse event waveform may be converted to an equivalent FM transition-event waveform by using the FM pulse event waveform to toggle a flip-flop, and then using an output of the flip-flop as the transition- event waveform. All biphase waveforms are of the transition-event type since the phase of the waveform is crucial to the successful recovery of the encoded data. Therefore, the preferred embodiment of the present invention is designed to be driven by transition-event waveforms only. Recovering data from a double frequency encoding depends on the ability to recognize the guaranteed transitions and to synchronize some timing circuit with these recognized guaranteed transitions. The output of the timing circuit can then be used, along with some additional logic, to extract data from the waveform. In the prior art, various timing circuits have been used for this purpose. Two commonly used techniques are briefly discussed below. In the first prior art technique, monostable multivibrators triggered by the guaranteed transitions define a "window" during an interval when a non- guaranteed transition may occur. The pulses produced by the monostables are then used to extract data from the waveform. Technique 1 has the advantage of simplicity, but suffers from wide variations in timing common with monostables. Further, technique 1 is quite susceptible to spurious operation induced by noise in the incoming waveform and is limited to usage with relatively low frequency signals.

In the second prior art technique, a variable frequency oscillator is synchronized to the incoming frequency by means of a phase-locked loop. The output of the oscillator is then used to extract data from the incoming waveform. Technique 2 eliminates the timing tolerance problem associated with technique 1 and is much less prone to noise induced failure. However, technique 2 is substantially more complex than technique 1. In certain applications where units containing circuits exemplified by techniques 1 or 2 are placed in series, such as in a ring network, the clocking signals derived from the incoming waveform are used to construct an outgoing waveform for transmission to the next unit downline. In such a configuration, "jitter" (viz., timing uncertainty) in the output waveform must be minimized since the jitter may cascade and be amplified by passage through several units in series. Phase locked loops, such as those of technique 2, always exhibit frequency jitter. The amount of jitter is traded off against capture time (time to go from initial "unlocked" state to "locked") and lock range (input frequency range within which the phase-locked loop will eventually enter the locked condition) . Since less jitter means less tracking ability and hence greater sensitivity to component value tolerances, technique 2 may be unsuitable for applications in which many units, each containing the extraction circuit, are cascaded in series. Using technique 1 it is possible to design a circuit which exhibits no jitter beyond that present in the incoming waveform, but one that suffers from the aforementioned drawbacks. Objects of the Invention

It is the general object of the present invention to overcome these and other drawbacks of the prior art by providing an improved clock derivation circuit arrangement for double frequency encoded serial digital data.

It is a further object of the present invention to provide an improved clock derivation circuit arrangement which is characterized by the simplicity of technique 1 without its component value sensitivity.

It is another object of the present invention to provide an improved clock derivation circuit arrangement which will not introduce additional jitter when utilized in a cascade arrangement such as a ring network.

O It is still a further object of the present invention to provide an improved clock derivation circuit arrangement whose noise sensitivity is no greater than clock derivation circuits utilizing monostable multivibrators (technique 1).

It is yet another object of the present invention to provide a clock derivation circuit arrangement capable of operating at frequencies higher than those possible with circuits utilizing monostable multivibrators (technique 1).

It is still another object of the present invention to provide a circuit arrangement which derives a clock signal which identifies the commencement of each guaranteed transition in an inputted double frequency encoded transition-event waveform.

Still further, it is another object of the present invention to provide a circuit arrangement which derives a clock signal which commences one-half bit time after the commencement of each guaranteed transition in an inputted double frequency encoded transition-event waveform.

These and other objects, features and advantages of the present invention will become more apparent from the description of the preferred embodiment of the present invention when read in conjunction with the drawings contained herewith. Summary of the Invention

The foregoing objects of the present invention are achieved by providing a circuit arrangement which receives a double frequency encoded transition-event waveform and derives two sets of clocking signals from the waveform received. The clocking signals derived are pulses of 1/4 T duration, where T is the length of a bit cell in the encoded waveform. The two clocking signals derived are 1/2 T out of phase with each other, giving available clock edges at OT, 1/4 T, 1/2 T and 3/4 T in each bit cell.

The incoming double frequency encoded transition-event waveform is fed directly into a digital delay line which generates three versions of the incoming waveform, each delayed by 1/4 T, 1/2 T or 3/4 T respectively. Transitions in the incoming waveform are detected by comparing the 1/4 T output of the delay line with the incoming signal by means of a first exclusive OR gate, thus providing a positive pulse of 1/4 T duration for each transition of level in the incoming waveform. A second exclusive OR gate performs an identical function on the incoming waveform delayed by 1/2 T, the second exclusive OR gate receiving its inputs from the 1/2 T and 3/4 T outputs of the delay line. The output of the second exclusive OR gate is therefore identical to the output of the first exclusive OR gate delayed by 1/2 T. A composite clock is derived by ORing together the outputs of the first and second exclusive OR gates, the output of the OR gate thus providing two pulses per bit cell T, and more particularly providing exactly two negative going transitions per bit cell spaced approximately 1/2 T apart. The composite clock formed at the output of the OR gate is used to clock a flip-flop, the flip-flop being of the type that is triggered by a negative going transition. As a result, the flip-flop is clocked every 1/2 T. The true and false outputs of the flip-flop are then gated with the outputs of the first and second exclusive OR gates, respectively, as inputs to first and second NAND gates, respectively, to produce the desired clocking signals at the outputs of the first and second NAND gates, respectively.

OMP Brief Description of the Drawings

Fig. 1 is an example showing data encoded as an FM pulse event waveform.

Fig. 2 is an example showing data encoded as a biphase transition-event waveform.

Fig. 3 is a schematic drawing of the preferred embodiment of .the clock extraction circuit of the present invention.

Fig. 4 is a timing diagram showing the input waveform, internal signals generated and clocks derived by the clock extraction circuit of Fig. 3. Description of the Preferred Embodiment

Fig. 3 shows the clock derivation circuit utilized in the preferred embodiment of the present invention. The circuit shown extracts two clock signals S12, S13 from a double frequency encoded transition-event waveform provided as the input SI. The preferred embodiment of the present invention is designed to handle waveforms having a frequency of 1 MHz. However, those skilled in the art will realize that the present invention may be readily modified to handle different frequency waveforms and will be most beneficial when used with waveforms having a frequency equal to or greater than 1 MHz. The clocks S12, S13 derived are negative pulses of 1/4 T duration, where T is the length of a bit cell in the encoded waveform (in the preferred embodiment, T is 1 microsecond). The two clocks S12, S13 are 1/2 T out of phase with each other, giving available clock edges at OT, 1/4 T, 1/2 T and 3/4 in each bit cell.

The basic timing element used in the preferred embodiment is a digital delay line 10 with three taps S2, S3, S4. These taps S2, S3, S4 are for delays of 1/4 T, 1/2 T and 3/4 T respectively. The incoming waveform SI is sent directly into the delay line 10. This results in the generation of three delayed versions S2, S3, S4 of the waveform SI at the output of delay line 10 (Fig. 4). In the preferred embodiment of the present invention, a Technitrol TTLDL750C digital delay line having a total delay of 3/4 T, or 750 nanoseconds, is utilized to correspond to the frequency of input waveform SI.

Referring to Fig. 4, the incoming waveform SI is shown with asterisks above the guaranteed transitions. The non-guaranteed transitions in SI are shown with an uncertainty interval since the exact position of the non-guaranteed transitions is determined by the characteristics of the delay line in the preceding unit (assuming a cascade arrangement of units utilizing the present invention) . The guaranteed transitions on the outgoing waveform from a preceding unit may be generated by the leading edge of one of the derived clock signals S12. As will be seen,this leading edge is derived directly from the guaranteed transition of the incoming waveform. Thus, the guaranteed transitions on the outgoing waveform are derived from the guaranteed transitions of the incoming signal without any dependence on the timing element 10 within the unit. Therefore, the guaranteed transitions are "precise" in the sense that the interval between these guaranteed transitions is constant throughout the chain of cascaded units. To the contrary, the center (non-guaranteed) transitions are derived from timing signal S13. Timing signal S13 is derived from signals out of the delay line 10. Thus, the exact position of a center (non-guaranteed) transition relative to its neighboring guaranteed transitions is subject to an uncertainty interval determined by the timing tolerance of the delay line 10. On the assumption that units containing the present invention are cascaded, the

OMPI incoming signal SI will also have an uncertainty interval surrounding center transitions, as shown in Fig. 4.

The preferred embodiment of the present invention (Fig. 3) is implemented using the following integrated circuit types:

Exclusive OR gates 12, 14 - 74LS86 OR gate 16 - 74LS32

Flip-flop 18 (Dual J-K, negative edge triggered) - 74LS76

NAND gates 20, 22 - 74LS00 However, those skilled in the art will realize that various substitutions in the components used may be made without departing from the spirit of the present invention.

The operation of the clock derivation circuit will now be explained in detail.

As previously mentioned, the input waveform SI to the clock derivation circuit is a double frequency encoded transition-event waveform SI (Fig. 4) with the guaranteed transitions identified by asterisks.

Transitions in input waveform SI are detected by comparing the output of the first tap S2 of the delay line 10 with SI. The comparison is performed by exclusive OR gate 12, whose output is low whenever both of its inputs are the same and high when they are different. The resulting signal S5 (Fig. 4) provides a positive pulse of 1/4 T duration for each transition of level in SI. Some of these positive pulses in S5 are "fuzzy" (having uncertainty intervals) because they derive from the fuzzy center transition. Another exclusive OR gate 14 performs an^* analogous function on the incoming signal SI delayed by 1/2 T. That is, the inputs SI, S2 to exclusive OR gate 12 are out of phase by 1/4 T as are the inputs S3, S4 to exclusive OR gate 14. Thus, the output S7 of exclusive OR gate 14 is identical to the output S5 of exclusive OR gate 12 delayed by 1/2 T.

The output S5 of exclusive OR gate 12 has a "clean" (i.e., not fuzzy) pulse for each guaranteed transition in input waveform SI, and so has one clean pulse per bit cell commencing with each guaranteed transition in SI and lasting 1/4 T. Since S7 is simply S5 delayed, S7 has one clean pulse per bit cell commencing at 1/2 T after each guaranteed transition and lasting until 3/4 T.

The clocks which are to be derived are S12 and S13. Clock pulse S12 is a 1/4 T negative pulse commencing with each guaranteed transition. Clock pulse S13 is a 1/4 T negative pulse commencing 1/2 T after each guaranteed transition. In order to complete the task of deriving clocks S12 and S13, the clean pulses must be isolated out of the S5 and S7 waveforms. The means for isolating out just the clean pulses is provided by flip-flop 18. In normal operation (i.e., the incoming waveform SI is in sync, and there is no noise on SI), flip-flop 18 simply toggles (changes state) every 1/2 T (Fig. 4). Its true and false outputs S9 and S10, respectively, are then gated with S5 and S7 respectively through NAND gates 20 and 22, respectively, to produce the desired clocking signals S12 and S13, respectively.

In order for flip-flop 18 to change state, it must be clocked. Flip-flop 18 is triggered by a negative going transition at its clock input. In order for flip-flop 18 to change state every 1/2 T, a composite clock for flip-flop 18 is derived by ORing together S5 and S7 via OR gate 16 to produce S8 (Fig. 4). Each of these signals S5, S7 has at least one pulse per bit time T, and S7 is S5 delayed 1/2 T.

OMPI Furthermore, if S5 has a second pulse (the fuzzy one) , it overlaps^* the clean pulse in S7 and vice versa. Therefore, the composite clock S8 has exactly two pulses per bit cell T, and more particularly S8 has exactly two negative going transitions per bit cell T. These negative going transitions in- S8 are spaced approximately 1/2 T apart and thus flip-flop 18 is clocked every 1/2 T.

Since the outputs S9, S10 of flip-flop 18 are being used to isolate the clean (i.e., not fuzzy) pulses on S5, S6 which correspond to the negative pulses on S12, S13 respectively, closer attention must be given to the fuzziness of clocking signal S8. S8 is the logical OR of S5 and S7. Thus, S8 must be high as long as either S5 or S7 is high. Referring now to Fig. 4, and more particularly to an instance of a clean pulse occurring on S5 coincident with a fuzzy pulse on S7, it will be seen that the S7 pulse may begin before or after the S5 pulse and may end before or after the S5 pulse. Further, as will be obvious to those skilled in the art, the timing tolerance associated with the delay is not so large as to allow the S7 pulse to end before the S8 pulse begins. Thus, S8 goes high no later than S5 goes high (disregarding gate propagation delay) and goes low no earlier than S5 goes low. This is illustrated in Fig. 4 by the halving of the uncertainty interval. This same logic applies to the case of a clean pulse on S7 coinciding with a fuzzy pulse of S5. Any pulse occurring on S5 without a coincident pulse on S7, or vice versa, must be a clean pulse since a clean pulse occurs every 1/2 T on either S5 or S7.

The implication from the discussion of the last paragraph is that the negative going edges on S8 always occur no earlier than the end of the clean pulse on either S5 or S7. Thus, since flip-flop 18 is triggered by negative going edges on S8, flip-flop 18 changes state after the end of the clean pulse on either S5 or S7. Since the outputs S9 and S10 of flip-flop 18 are being used to isolate the clean pulses on S5 and S7, the implication is that an entire clean pulse from S5 or S7 is allowed through NAND gates 20 or 22, respectively, before flip-flop 18 changes state to select the next clean pulse from S7 or S5 respectively. Additionally, by the same logic, a negative edge on S8 may occur no earlier than the end of a fuzzy pulse on S5 or S7, and thus flip-flop 18 changes state at the later of the end of the pulse on S5 or the end of the pulse on S7. Consequently, when flip-flop 18 changes state to enable NAND gate 22 rather than NAND gate 20 or vice versa, it is guaranteed that no trailing part of a pulse on S5 or S7 will be allowed through NAND gate 20 or NAND gate 22, respectively.

Having shown and described the preferred embodiment of the present invention, those skilled in the art will realize that various omissions, substitutions and changes in forms and details may be made without departing from the spirit of the present invention. It is the intention, therefore, to be limited only as indicated by the scope of the following claims.

OMPI

Claims

hat is claimed is;

1. A circuit arrangement for reconstructing the timing information encoded in an incoming double frequency transition-event waveform, said incoming waveform characterized as including both guaranteed and non-guaranteed transitions, said incoming waveform further characterized as having a bit cell duration of T, said circuit arrangement comprising: delay line means, responsive to said incoming waveform, said delay line means for generating delayed versions of said incoming waveform; means, responsive to said incoming waveform and said generated delayed versions of said incoming waveform, said means for detecting transitions in said incoming waveform; and means, connected to said detecting means, said means for isolating out the set of guaranteed transitions in said detected transitions, whereby at least one set of timing information is reconstructed.

2. The circuit arrangement in accordance with claim 1 wherein said delay line means is characterized as including means for generating three delayed versions of said incoming waveform, said three delayed versions corresponding to the incoming waveform delayed by 1/4 T, 1/2 T and 3/4 T, respectively.

3. The circuit arrangement in accordance with claim 2 wherein said detecting means includes: a first logical exclusive OR gate receiving its inputs from said incoming waveform and said 1/4 T delayed version of said incoming waveform; and a second logical exclusive OR gate receiving its inputs from said 1/2 T and said 3/4 T delayed versions of said incoming waveform.

4. The circuit arrangement in accordance with claim 3 wherein said isolating means includes: a logical OR gate receiving its inputs from the outputs of said first and said second exclusive OR 5 gates; a logical flip-flop receiving its clocking input from the output of said logical OR gate; and a first logical NAND gate receiving its inputs from the output of said first exclusive OR gate and the true output of said flip-flop, whereby a first set of said timing information is reconstructed at the output of said first NAND gate.

5. The circuit arrangement in accordance with claim 4 wherein said isolating means further includes a second logical NAND gate receiving its inputs from the output of said second exclusive OR gate and the false

<- output of said flip-flop, whereby a second set of said timing information is reconstructed at the output of said second NAND gate.

6. A circuit arrangement in accordance with claim 5 wherein said logical flip-flop is characterized as being triggered by a negative going transition.

7. The circuit arrangement in accordance with claim 6 wherein said logical flip-flop is further characterized as being a J-K type, the J and the K inputs to which are tied high.

8. The circuit arrangement in accordance with claim 1 wherein said detecting means includes: first detecting means, responsive to said incoming waveform and a first one of said delayed versions of said incoming waveform, said first detecting means for generating a signal providing a pulse coincident with the start of each transition in said incoming waveform; and second detecting means, responsive to a second and third of said delayed versions of said incoming waveform, said second detecting means for generating a signal providing a pulse occurring at a time after the start of each transition in said incoming waveform and before a period T after the start of each transition in said incoming waveform.

9. The circuit arrangement in accordance with claim 8 wherein said first and second detecting means are each characterized as including a logical exclusive OR gate, the logical exclusive OR gate included in said first detecting means receiving its inputs from the incoming waveform and the first one of said delayed versions of said incoming waveform, the logical exclusive OR gate included in said second detecting means receiving its inputs from the second and the third of said delayed versions of said incoming waveform.

10. The circuit arrangement in accordance with claim 9 wherein the first, second and third of said delayed versions of said incoming waveform correspond to the incoming waveform delayed by 1/4 T, 1/2 T and 3/4 T respectively.

11. The circuit arrangement in accordance with claim 10 wherein said delay line means includes a digital delay line receiving its input from said incoming waveform.

12. The circuit arrangement in accordance with claim 8 wherein said isolating means includes: means, connected to the output of said first and said second detecting means, said means for forming a composite clock which is characterized as having two unidirectional going transitions per bit cell; means, receiving an input from the output of said composite clock forming means, said means including means for generating a first output which toggles between a high and low state in response to each of said unidirectional going transitions provided at said input; and means, connected to the first output of said toggling means and said first detecting means, said means for generating a first timing signal coincident with the start of each of said guaranteed transitions in said incoming waveform.

13. The circuit arrangement in accordance with claim 12 wherein said toggling means further includes a second output, said second output providing an output signal which is the inverse of said toggle means first output.

14. The circuit arrangement in accordance with claim 13 wherein said isolating means further includes means connected to the second output of said toggling means and said second detecting means, said means for generating a second timing signal commencing 1/2 T after the start of each of said guaranteed transitions in said input waveform.

OMPI

15. The circuit arrangement in accordance with claim 12 wherein the two unidirectional transitions per bit cell formed at the output of said composite clock forming means are spaced substantially 1/2 T apart.

16. The circuit arrangement in accordance with claim 12 wherein said composite clock forming means includes a logical OR gate connected to the outputs of said first and said second detecting means.

17. The circuit arrangement in accordance with claim 12 wherein said toggling means is characterized as including a logical flip-flop, said logical flip-flop responsive to each of said unidirectional going transitions.

18. The circuit arrangement in accordance with claim 12 wherein said first timing signal generation means includes a first logical NAND gate, said first logical NAND gate receiving its inputs from the first output of said toggling means and the output of said first detecting means.

I

19." The circuit arrangement in accordance with claim 14 wherein said means for generating said second timing signal is characterized as including a second logical NAND gate, said second logical NAND gate receiving its inputs from the second output of said toggling means and the output of said second detecting means.

20. The circuit arrangement in accordance with claim 12 or 14 wherein said first and second detecting means are each characterized as including a logical exclusive OR gate, said first detecting means' exclusive OR gate receiving its inputs from the incoming waveform and the first of said delayed versions of said incoming waveform, said second detecting means' exclusive OR gate receiving its inputs from the second and the third of said delayed versions of said incoming waveform.

21. The circuit arrangement in accordance with claim 12 or 14 wherein the first, second and third of said delayed versions of said incoming waveform correspond to the incoming waveform delayed by 1/4 T, 1/2 T and 3/4 T respectively.

22. The circuit arrangement in accordance with claim 19 wherein said delay line means includes a digital delay line receiving its input from said incoming waveform.

23. The circuit arrangement in accordance with claim 1 wherein said isolating means includes: means, connected to said detecting means, said means for forming a composite clock which is characterized as having two unidirectional going transitions per bit cell; means, connected to said composite clock forming means, said means for generating a first output which toggles between a high and low state in response to each of said unidirectional going transitions; and means, connected to said toggling means and said detecting means, said means for generating a first timing signal coincident with the start of each of said guaranteed transitions in said incoming waveform.

24. The circuit arrangement in accordance with claim 23 wherein said detecting means includes: first detecting means, responsive to said incoming waveform and a first of said delayed versions ^ of said incoming waveform, said first detecting means for generating a signal providing a pulse coincident with the start of each transition in said incoming waveform; and second detecting means, responsive to second 0 and third delayed versions of said incoming waveform, said second detecting means for generating a signal providing a pulse occurring at a time after the start of each transition in said incoming waveform and before a period T after the start of each transition in said 5 incoming waveform.

25. The circuit arrangement in accordance withclaim 24 wherein the first, second and third delayed versions of said incoming waveform correspond to the incoming waveform delayed by 1/4 T, 1/2 T, and

5 3/4 T respectively.

26. The circuit arrangement in accordance with claim 24 wherein said first and said second detecting means are each characterized as including a logical exclusive OR gate, the exclusive OR gate included in

5 said first detecting means receiving its inputs from the incoming waveform and the first delayed version of said incoming waveform, the exclusive OR gate included in the second detecting means receiving its inputs from the second and the third delayed versions of said incoming waveform.

27. The circuit arrangement in accordance with claim 26 wherein: said composite clock forming means includes a logical OR gate receiving its inputs from the outputs of said first and said second exclusive OR gates; said toggling means includes a logical flip-flop receiving its clocking input from the output of said OR gate; and said first timing signal generating means includes a logical NAND gate receiving its inputs from the output of said first detecting means' exclusive OR gate and the true output of said flip-flop.

28. The circuit arrangement in accordance with claim 27 wherein said delay line means includes a digital delay line receiving its input from said incoming waveform.