USRE40991E1 - Fast cyclic redundancy check (CRC) generation - Google Patents
Fast cyclic redundancy check (CRC) generation Download PDFInfo
- Publication number
- USRE40991E1 USRE40991E1 US11/362,564 US36256406A USRE40991E US RE40991 E1 USRE40991 E1 US RE40991E1 US 36256406 A US36256406 A US 36256406A US RE40991 E USRE40991 E US RE40991E
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- data block
- crc
- division circuits
- variable length
- bit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/617—Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials
Definitions
- the present invention relates to the field of data processing. More specifically, the present invention relates to high speed cyclic redundancy check (CRC) generation, having special application to high speed network traffic routing, such as Gigabit Ethernet packet switching.
- CRC cyclic redundancy check
- Cyclic Redundancy Check has long been employed as a metric to facilitate detection of data transmission error.
- the technique is employed in a wide variety of data processing related disciplines, including in particular, networking.
- the underlying mathematics including the polynomial divisions involved in the generation of a CRC value for a data block is well understood among those ordinarily skilled in the art.
- Various hardware as well as software implementations are known. Examples of known hardware implementations include but are not limited to the implementations available from e.g. Actel of Sunnyvale, Calif.
- CRC generation resource it is not only necessary for the CRC generation resource to be sufficiently fast to keep pace with the processing of a single network traffic flow, it is further desirable that the CRC generation resource to be sufficiently efficient and fast, such that it can be shared among the various flow processing units, thereby eliminating the need to have dedicated CRC generation resource for each of the flow processing units.
- a CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a data block.
- the CRC generation unit also includes a selector to select one of the remainder values, and a register to store the selected remainder value, return the stored remainder value to the PDCs for formation of different bit length dividends, and output the stored remainder value of the last iteration as the generated CRC value.
- the CRC generation unit further includes alignment circuitry to align the data block. In one embodiment, multiple CRC generation units are provided to generate the CRC values of successive variable length data blocks.
- the CRC generation units form a shared resource to multiple network traffic flow processing units of a network traffic routing device.
- the network traffic routing device is disposed on a single integrated circuit.
- FIG. 1 illustrates an overview of the present invention
- FIG. 2 illustrates one of the fast CRC generators of FIG. 1 in further detail, in accordance with one embodiment
- FIG. 3 illustrates an example of packet data alignment or the lack thereof
- FIG. 4 illustrates one of the alignment units of FIG. 2 in further detail, in accordance with one embodiment
- FIG. 5 illustrates one of the n ⁇ polynomial division circuits of FIG. 2 in further detail, in accordance with one embodiment
- FIG. 6 illustrates one of the polynomial division circuits of FIG. 5 in further detail, in accordance with one embodiment
- FIG. 7 illustrates an example routing device incorporated with the fast CRC generation teaching of the present invention.
- data sender 102 and data receiver 104 are coupled to each other via communication link 107 , over which data sender 102 may send data, including associated CRC values, to data receiver 104 .
- Both data sender 102 and data receiver 104 are equipped with fast CRC generator 106 a/ 106 b of the present invention for generating CRC values for the data blocks being sent from data sender 102 to data receiver 104 .
- fast CRC generator 106 a/ 106 b includes redundant circuit elements organized in accordance with a parallel architecture to allow various calculations to be performed in an overlapped and parallel manner.
- fast CRC generator 106 a/ 106 b may generate CRC values of variable length data blocks, such as variable length packet data, efficiently.
- fast CRC generator 106 a/ 106 b is sufficiently efficient to allow fast CRC generator 106 a/ 106 b to be shared by as many as 64 collections of network traffic flow processing resources of an IC based gigabit Ethernet routing device, resulting in a substantial net reduction in real estate requirement (notwithstanding the duplication of certain elements to enable the overlapped and parallel computations).
- fast CRC generator 106 a/ 106 b Except for fast CRC generator 106 a/ 106 b, data sender 102 , data receiver 104 and communication link 107 are all intended to represent a broad range of data sending, data receiving and communication systems and/or components known in the art. Accordingly, except for fast CRC generator 106 a/ 106 b, data sender 102 , data receiver 104 and communication link 107 will not be otherwise further described.
- FIG. 2 illustrates one of fast CRC generators 106 a/ 106 b of FIG. 1 in further details, in accordance with one embodiment.
- each fast CRC generator 106 a/ 106 includes two parallel datapaths 202 a- 204 a and 202 a- 204 b to facilitate overlapped CRC generation for two successive variable length data blocks.
- Alignment unit 202 a and a collection of n ⁇ polynomial division circuits 204 a form one datapath
- alignment unit 202 b and another collection of n ⁇ polynomial division circuits 204 b form another datapath.
- each variable length data block may be received through m groups of n-bit data groups, where m and n are integers, with m being equal to or greater than 1.
- m is a multiple of 8 (as most data communication as well as telecommunication protocols are defined with data sizes in multiples of bytes).
- the starting bit of each variable length data block may be located at any bit position of the first n-bit group, and the ending bit may be located at any bit position of the last n-bit group.
- alignment unit 202 a/ 202 b aligns the data bits of the received data block, such that when the different portions of the variable data block is provided to n ⁇ polynomial division circuits 204 a/ 204 b to have its CRC value generated, the starting bit of the variable length data block is aligned to the most significant bit position of the first n bit group of the m bit groups through which the variable length data block is received.
- the n ⁇ polynomial division circuits 204 a/ 204 b collectively and iteratively generate the CRC value for the aligned variable length data block in m (or m ⁇ 1) iterations (depending on where the starting and the ending bits of the variable length data block is located in the first and the last n-bit group).
- each collection of n ⁇ polynomial division circuits 204 a/ 204 b includes n sets of polynomial division circuits to facilitate performance of n polynomial divisions of n different length dividends in parallel, thereby allowing the successive CRC generation to be efficiently completed with the last n-bit group having anywhere from 1 to n “residual” bits of the variable length data block.
- one datapath 202 a- 204 a/ 202 b- 204 b may start the iteratively generation of the CRC value for an immediately following variable length data block while the other datapath 202 a- 204 a/ 202 b- 204 b is “finishing up” its iteratively generation of the CRC value for the immediately preceding variable length data, thereby speeding up the aggregate times incurred for generating CRC values for a large number of successive variable length data blocks, as in the case of multiple network flow processing.
- fast CRC generator 106 a/ 106 b also includes selector 206 coupled to the two datapaths 202 a- 204 a and 202 b- 204 b to alternate between selecting the two outputs of datapaths 202 a- 204 a and 202 b- 204 b for output as the CRC values of the successive variable length data blocks.
- FIG. 4 illustrates one of alignment units 202 a/ 202 b of FIG. 2 in further details, in accordance with one embodiment.
- each of alignment units 202 a/ 202 b includes two registers R 1 402 a and R 2 402 b for storing two successive n-bit groups.
- Each alignment unit 202 a/ 202 b also includes multiplexor 404 coupled to registers R 1 402 a and R 2 402 b to select an appropriate number of bits from each of the two stored successive n-bit groups to form an aligned n-bit group, and output the selected bits.
- Each alignment unit 202 a/ 202 b further includes latch 406 to store an aligned n-bit group for output for the corresponding collection of n ⁇ polynomial division circuits 204 a/ 204 b.
- FIG. 5 illustrates one collection of the n ⁇ polynomial division circuits 204 a/ 204 b of FIG. 2 in further details, in accordance with one embodiment.
- Each of polynomial division circuits 502 a- 502 h is employed to perform a polynomial division of a multi-bit dividend by the predetermined generator polynomial for each iteration of an iterative generation of a CRC value.
- the multi-bit dividend for each iteration is formed by combining the remainder value of the immediately preceding iteration with an additional 1 to 8 input bits, to account for the possibility that the next group of bits to be processed are the last group of bits of the variable length data block and that the size of this last group of bits may be 1 or more bits, up to 8 bits.
- the multi-bit dividend is different.
- the multi-bit dividends are 16, 15, 14, 13, 12, 11, 10 and 9 respectively (the 8-bit remainder value of the immediately preceding iteration combined with 8, 7, 6, 5, 4, 3, 2, 1 bit of the next bit group).
- Selector 504 is employed to select one of the remainder value outputs of the n polynomial division circuits 502 a- 502 h, and to output the selected remainder value for CRC register 506 .
- the remainder value selected is the remainder value outputted by polynomial division circuit 502 a, until the last iteration, where the remainder value selected is the remainder value outputted by the appropriate one of the polynomial division circuits 502 a- 502 h corresponding to the number of residual bits of the variable length data block included in the processed bit group.
- FIG. 7 illustrates an example application of the fast CRC generator of the present invention.
- data routing device 702 comprising receive interface 704 and transmit interface 712 is advantageously provided with a number of per flow inbound processing units 706 and a number of per flow outbound processing functions 710 . Examples of these per flow inbound and outbound processing functions may include but are not limited to deciphering and ciphering functions. Additionally, data routing device 702 may also include a number of other common or shared function units 708 .
- common/shared function units 708 include in particular a shared CRC generation function block, incorporated with the dual datapath architecture fast CRC generator of FIG. 2 .
- each collection of n ⁇ CRC polynomial circuits includes n polynomial division circuits as architected in FIG. 4 .
- the common/shared CRC generator may alternate between generating CRC values for different data packets of the different flows being processed by per flow inbound/outboard processing units 708 / 710 .
Abstract
Description
Claims (37)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US11/362,564 USRE40991E1 (en) | 2001-05-15 | 2006-02-23 | Fast cyclic redundancy check (CRC) generation |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/858,232 US6701479B2 (en) | 2001-05-15 | 2001-05-15 | Fast cyclic redundancy check (CRC) generation |
US11/362,564 USRE40991E1 (en) | 2001-05-15 | 2006-02-23 | Fast cyclic redundancy check (CRC) generation |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/858,232 Reissue US6701479B2 (en) | 2001-05-15 | 2001-05-15 | Fast cyclic redundancy check (CRC) generation |
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USRE40991E1 true USRE40991E1 (en) | 2009-11-17 |
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US09/858,232 Ceased US6701479B2 (en) | 2001-05-15 | 2001-05-15 | Fast cyclic redundancy check (CRC) generation |
US11/362,564 Expired - Lifetime USRE40991E1 (en) | 2001-05-15 | 2006-02-23 | Fast cyclic redundancy check (CRC) generation |
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US09/858,232 Ceased US6701479B2 (en) | 2001-05-15 | 2001-05-15 | Fast cyclic redundancy check (CRC) generation |
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WO (1) | WO2002093753A1 (en) |
Cited By (2)
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US8397305B2 (en) | 1994-12-19 | 2013-03-12 | Atwater Ventures Limited | System and method for connecting gaming devices to a network for remote play |
US9251649B2 (en) | 2002-10-09 | 2016-02-02 | Zynga Inc. | System and method for connecting gaming devices to a network for remote play |
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JP3795743B2 (en) * | 2000-11-17 | 2006-07-12 | 株式会社エヌ・ティ・ティ・ドコモ | Data transmission method, data transmission system, transmission device and reception device |
JP2002164791A (en) * | 2000-11-27 | 2002-06-07 | Ando Electric Co Ltd | Circuit and method for operating crc code |
US7216285B2 (en) * | 2001-11-09 | 2007-05-08 | Marvell International Ltd. | System and method for generating cyclic redundancy check |
JP2003243992A (en) * | 2002-02-14 | 2003-08-29 | Matsushita Electric Ind Co Ltd | Code generation circuit |
US6968492B1 (en) | 2002-03-28 | 2005-11-22 | Annadurai Andy P | Hardware-efficient CRC generator for high speed communication networks |
US7191383B2 (en) * | 2003-03-28 | 2007-03-13 | International Business Machines Corporation | System and method for optimizing iterative circuit for cyclic redundancy check (CRC) calculation |
US20050044261A1 (en) * | 2003-07-18 | 2005-02-24 | Rahul Saxena | Method of operating a network switch |
US7353448B1 (en) | 2003-10-21 | 2008-04-01 | Marvell Semiconductor Israel Ltd. | Methods, architectures, circuits and systems for transmission error determination |
US7103832B2 (en) * | 2003-12-04 | 2006-09-05 | International Business Machines Corporation | Scalable cyclic redundancy check circuit |
US7523305B2 (en) * | 2003-12-17 | 2009-04-21 | International Business Machines Corporation | Employing cyclic redundancy checks to provide data security |
US7451381B2 (en) | 2004-02-03 | 2008-11-11 | Phonex Broadband Corporation | Reliable method and system for efficiently transporting dynamic data across a network |
US7434150B1 (en) | 2004-03-03 | 2008-10-07 | Marvell Israel (M.I.S.L.) Ltd. | Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations |
US7266760B1 (en) * | 2004-09-30 | 2007-09-04 | Altera Corporation | Method and apparatus for calculating cyclic redundancy checks for variable length packets |
JP2008011025A (en) * | 2006-06-28 | 2008-01-17 | Fujitsu Ltd | Remainder calculation apparatus for cyclic redundancy check |
KR20080052039A (en) * | 2006-12-07 | 2008-06-11 | 삼성전자주식회사 | Method for checking correcting errors correcting by cyclic redundancy checking and apparatus thereof |
US7886210B2 (en) * | 2007-02-09 | 2011-02-08 | International Business Machines Corporation | Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs |
US8136010B2 (en) * | 2007-12-21 | 2012-03-13 | International Business Machines Corporation | Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs |
US20090254794A1 (en) * | 2008-04-04 | 2009-10-08 | Nxp B.V. | Method for efficient packet framing in a communication network |
FR2935056A1 (en) * | 2008-08-14 | 2010-02-19 | St Microelectronics Rousset | DATA PROCESSING SYSTEM HAVING DISTRIBUTED PROCESSING MEANS FOR EXPLOITING INTRINSIC SYSTEM LATENCIES |
US8261176B2 (en) * | 2009-06-30 | 2012-09-04 | Sandisk Il Ltd. | Polynomial division |
US8381080B2 (en) | 2010-06-15 | 2013-02-19 | Lsi Corporation | Reducing a degree of a polynomial in a polynomial division calculation |
US8443256B2 (en) | 2011-01-24 | 2013-05-14 | Xilinx, Inc. | Method and apparatus for determining a cyclic redundancy check (CRC) for a data message |
WO2012109872A1 (en) * | 2011-08-02 | 2012-08-23 | 华为技术有限公司 | Method, apparatus and lte terminals for cyclic redundancy checking in communication system |
US8738990B2 (en) * | 2012-07-19 | 2014-05-27 | Nvidia Corporation | Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers |
US8726124B2 (en) | 2012-07-19 | 2014-05-13 | Nvidia Corporation | Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers |
US9154161B1 (en) | 2014-04-01 | 2015-10-06 | Cisco Technology, Inc. | Calculating cyclic redundancy checks over overlapping windows of streaming data |
US11855655B2 (en) * | 2021-09-28 | 2023-12-26 | Texas Instruments Incorporated | Serial communications module with CRC |
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-
2006
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8397305B2 (en) | 1994-12-19 | 2013-03-12 | Atwater Ventures Limited | System and method for connecting gaming devices to a network for remote play |
US8959154B2 (en) | 1994-12-19 | 2015-02-17 | Zynga Inc. | System and method for connecting gaming devices to a network for remote play |
US9251649B2 (en) | 2002-10-09 | 2016-02-02 | Zynga Inc. | System and method for connecting gaming devices to a network for remote play |
Also Published As
Publication number | Publication date |
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US20020174399A1 (en) | 2002-11-21 |
US6701479B2 (en) | 2004-03-02 |
WO2002093753A1 (en) | 2002-11-21 |
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