USH73H - Integrated circuit packages - Google Patents

Integrated circuit packages Download PDF

Info

Publication number
USH73H
USH73H US06/526,413 US52641383A USH73H US H73 H USH73 H US H73H US 52641383 A US52641383 A US 52641383A US H73 H USH73 H US H73H
Authority
US
United States
Prior art keywords
chip
wires
pads
layer
rtv
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US06/526,413
Inventor
Kenneth K. Claasen
Ronald N. Graver
Frank P. Pelletier
Kurt M. Striny
Ronald J. Wozniak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Bell Labs
AT&T Corp
Original Assignee
AT&T Bell Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Bell Laboratories Inc filed Critical AT&T Bell Laboratories Inc
Priority to US06/526,413 priority Critical patent/USH73H/en
Assigned to BELL TELEPHONE LABORATORIES, INCORPORATED reassignment BELL TELEPHONE LABORATORIES, INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: CLAASEN, KENNETH K., GRAVER, RONALD N., PELLETIER, FRANK P., STRINY, KURT M., WOZNIAK, RONALD J.
Priority to KR1019840003623A priority patent/KR850002676A/en
Priority to JP59175338A priority patent/JPS6072251A/en
Application granted granted Critical
Publication of USH73H publication Critical patent/USH73H/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This invention relates to semiconductor devices and in particular to a package including wire-bonded semiconductor chips.
  • DIP dual-in-line
  • a semiconductor device comprising a semiconductor chip electrically interconnected to metal leads by means of wires extending from pads on the chip to the leads.
  • the wires include arched portions.
  • a thick, protective layer which comprises a material having a large expansion coefficient and a low shear modulus, is formed over the surface of the chip to a thickness which covers at least the part of the arched portion of the wires where the slope of the wires is reduced to less than 45° relative to the semiconductor chip surface.
  • a plastic encapsulating material surrounds the chip, protective layer and a portion of the leads.
  • FIG. 1 is a cross-sectional view of a semiconductor device in accordance with one embodiment of the invention.
  • FIG. 2 is a graph showing the reliability of devices in accordance with the same embodiment of the invention as compared to other devices.
  • a semiconductor IC chip, 10, is provided with bonding pads, 11 and 12, on one major surface.
  • the pads, 11 and 12 are electrically interconnected to leads, 13 and 14, respectively, which extend out from the package on two sides of the chip for connection to external circuitry.
  • the electrical interconnection is made by wires, 15 and 16, which are bonded to their respective pads, 11 and 12, by means of standard ball bonds, 17 and 18, which were formed from the wires by heating according to standard techniques.
  • the opposite major surface of the chip was bonded to a metal plate (die support paddle), 24, which is part of the lead frame.
  • the chip was 180 mils long, 180 mils wide and 10 mils thick.
  • the wires were approximately 60 mils long and the leads were approximately 750 mils long.
  • the pads were approximately 5 mils ⁇ 5 mils.
  • each wire includes an arch portion, 25 and 26, with a portion of the arch, 19 and 20, where the slope of the wire goes from essentially vertical (typically approximately 100° to the surface to a slope of less than 45° to the semiconductor surface.
  • the chip, 10, along with the wires, 15 and 16, and at least a portion of the leads, 13 and 14, are encapsulated in a plastic material, 22, to form a dual-in-line package.
  • the semiconductor chip, prior to encapsulation is covered by a thick, protective layer, 21, which in this example is RTV silicone rubber.
  • the RTV coating of the present invention is thick enough, in this example approximately 10 mils in the area over the pads, so as to cover the portions, 19 and 20, of the arched portions of wires.
  • the stresses and strains in the wire are caused by the expansion and the contraction of the wires and materials, 10 and 22.
  • FIG. 2 illustrates the increased reliability of the present package in terms of the number of cycles to median life failure for three types of packages when subjected to temperature cycles of -40° C. to 150° C. of approximately 10 minutes per cycle. All packages were 40 lead DIP packages with identical chips encapsulated in plastic. However, one type (curve A) had no RTV applied, one type (curve B) had a thin (1-2 mil) layer of RTV applied and the third type (curve C) had RTV applied in accordance with the invention to a cured thickness of 10 mils in the area over the chip pads. (It will be appreciated that the RTV has a domed shape with a maximum thickness over the middle portion of the chip.
  • the important thickness is that over the area of the contact pads, 11 and 12, which are situated at the edges of the chip.
  • the maximum height of RTV is approximately 25 mils over the middle of the chip.
  • the ordinate shows the coefficient of thermal expansion of different plastic encapsulants employed and the abscissa shows the number of cycles to failure of the median number of devices in each group tested (a failure for a device occurs when one of the wire bonds break).
  • a typical sample size was approximately 60 devices.
  • the RTV was a standard, commercially available type, such as that sold by Dow Corning under the designation DC6550 which was diluted with xylene.
  • the RTV was applied with a dispenser and cured at room temperature for 2 hours and at 125° C. for 6-8 hours.
  • the plastic encapsulant was also a standard, commercially available material such as that sold by Plascon under the designation 3200 LS.
  • the plastic was molded around the structure at a temperature of 150°-175° C. for 2-3 minutes in a standard transfer molding press. As the package cools down to room temperature, the RTV shrinks and an air gap, 23, was formed between the RTV and encapsulant.
  • the formation of this air gap is important since it relieves pressure on the wire bonds by giving some room for mobility of the RTV layer.
  • the air gap has a dimension in the range 1-5 mils at room temperature over the area of the chip pads.
  • the layer should preferably have a large expansion coefficient to form the air gap and a low shear modulus so that movement of the layer causes a minimum stress on the wires. It is recommended that the expansion coefficient be at least 200ppm/°C. and the shear modulus be no greater than 100 psi at -40° C. to 150° C. In general, the thickness of the protective layer should be in the range 6-15 mils over the area of the chip pads.
  • the plastic encapsulant could be any material usually used for encapsulating integrated circuits.
  • a low expansion coefficient material is preferred, and the encapsulant will typically have an expansion coefficient which is less than 25 ppm/°C. from -40° C. to 125° C.

Abstract

A package for wire-bonded semiconductor integrated circuit chips is disclosed. The chip is covered by a protective layer of material such as room temperature vulcanizing silicone rubber. The thickness of the layer is such that it covers a portion of the arched wires, thereby concentrating the stresses away from the wire-ball bond interfaces. The chip is encapsulated in a plastic material while providing an air gap between the plastic and protective layer.

Description

BACKGROUND OF THE INVENTION
This invention relates to semiconductor devices and in particular to a package including wire-bonded semiconductor chips.
In the packaging of semiconductor integrated circuit (IC) chips, a dual-in-line (DIP) package is commonly employed. In such packages, the chip is mounted on a metal plate of a lead frame and the pads on the chip are electrically interconnected to the metal fingers of the lead frame by wire bonds. The chip is then encapsulated in a plastic material and the leads separated from the lead frame to form the discrete package.
Although such packages are generally adequate, a persistent yield and reliability problem has resulted from the tendency of the wire bonds to break due to stresses from the plastic encapsulant's expansion and contraction during temperature variations.
It is therefore a primary objective of the invention to provide a semiconductor chip package with improved mechanical reliability.
SUMMARY OF THE INVENTION
This and other objectives are achieved in accordance with the invention which is a semiconductor device comprising a semiconductor chip electrically interconnected to metal leads by means of wires extending from pads on the chip to the leads. The wires include arched portions. A thick, protective layer, which comprises a material having a large expansion coefficient and a low shear modulus, is formed over the surface of the chip to a thickness which covers at least the part of the arched portion of the wires where the slope of the wires is reduced to less than 45° relative to the semiconductor chip surface. A plastic encapsulating material surrounds the chip, protective layer and a portion of the leads.
BRIEF DESCRIPTION OF THE DRAWING
These and other features of the invention are delineated in detail in the following description. In the drawing:
FIG. 1 is a cross-sectional view of a semiconductor device in accordance with one embodiment of the invention; and
FIG. 2 is a graph showing the reliability of devices in accordance with the same embodiment of the invention as compared to other devices.
It will be appreciated that for purposes of illustration these figures are not necessarily drawn to scale.
DETAILED DESCRIPTION
The basic principles of the invention will be described with reference to the particular embodiment illustrated in FIG. 1. A semiconductor IC chip, 10, is provided with bonding pads, 11 and 12, on one major surface. Of course, it will be appreciated that the surface typically includes many more bonding pads as well as circuit elements which are not shown for the sake of clarity in the illustration. The pads, 11 and 12, are electrically interconnected to leads, 13 and 14, respectively, which extend out from the package on two sides of the chip for connection to external circuitry. The electrical interconnection is made by wires, 15 and 16, which are bonded to their respective pads, 11 and 12, by means of standard ball bonds, 17 and 18, which were formed from the wires by heating according to standard techniques. The opposite major surface of the chip was bonded to a metal plate (die support paddle), 24, which is part of the lead frame.
In a particular example, the chip was 180 mils long, 180 mils wide and 10 mils thick. The wires were approximately 60 mils long and the leads were approximately 750 mils long. The pads were approximately 5 mils×5 mils.
By virtue of the geometry of the package, each wire includes an arch portion, 25 and 26, with a portion of the arch, 19 and 20, where the slope of the wire goes from essentially vertical (typically approximately 100° to the surface to a slope of less than 45° to the semiconductor surface.
The chip, 10, along with the wires, 15 and 16, and at least a portion of the leads, 13 and 14, are encapsulated in a plastic material, 22, to form a dual-in-line package.
In accordance with a main feature of the invention, the semiconductor chip, prior to encapsulation, is covered by a thick, protective layer, 21, which in this example is RTV silicone rubber. The RTV coating of the present invention is thick enough, in this example approximately 10 mils in the area over the pads, so as to cover the portions, 19 and 20, of the arched portions of wires. We have found that use of such a thick coating greatly increases the mechanical reliability of the package by decreasing the strains in the wires and by concentrating the stresses on the wires away from the more fragile wire-ball bond interfaces where stresses in prior art packages caused breaking of the wire. The stresses and strains in the wire are caused by the expansion and the contraction of the wires and materials, 10 and 22.
FIG. 2 illustrates the increased reliability of the present package in terms of the number of cycles to median life failure for three types of packages when subjected to temperature cycles of -40° C. to 150° C. of approximately 10 minutes per cycle. All packages were 40 lead DIP packages with identical chips encapsulated in plastic. However, one type (curve A) had no RTV applied, one type (curve B) had a thin (1-2 mil) layer of RTV applied and the third type (curve C) had RTV applied in accordance with the invention to a cured thickness of 10 mils in the area over the chip pads. (It will be appreciated that the RTV has a domed shape with a maximum thickness over the middle portion of the chip. For the purposes of this invention, the important thickness is that over the area of the contact pads, 11 and 12, which are situated at the edges of the chip. Typically, the maximum height of RTV is approximately 25 mils over the middle of the chip.) The ordinate shows the coefficient of thermal expansion of different plastic encapsulants employed and the abscissa shows the number of cycles to failure of the median number of devices in each group tested (a failure for a device occurs when one of the wire bonds break). A typical sample size was approximately 60 devices.
It will be noted that three different encapsulants were employed for all three of the device types. In each case, the type with the thick RTV applied (curve C) demonstrated an improvement of at least a factor of 8 in cycles to median life failure and therefore a corresponding improvement in estimated life years.
In a particular example, the RTV was a standard, commercially available type, such as that sold by Dow Corning under the designation DC6550 which was diluted with xylene. The RTV was applied with a dispenser and cured at room temperature for 2 hours and at 125° C. for 6-8 hours. The plastic encapsulant was also a standard, commercially available material such as that sold by Plascon under the designation 3200 LS. The plastic was molded around the structure at a temperature of 150°-175° C. for 2-3 minutes in a standard transfer molding press. As the package cools down to room temperature, the RTV shrinks and an air gap, 23, was formed between the RTV and encapsulant. The formation of this air gap is important since it relieves pressure on the wire bonds by giving some room for mobility of the RTV layer. Preferably, the air gap has a dimension in the range 1-5 mils at room temperature over the area of the chip pads.
It will be appreciated tht protective layers other than RTV silicone rubber may be utilized. In order to produce the results of the invention, the layer should preferably have a large expansion coefficient to form the air gap and a low shear modulus so that movement of the layer causes a minimum stress on the wires. It is recommended that the expansion coefficient be at least 200ppm/°C. and the shear modulus be no greater than 100 psi at -40° C. to 150° C. In general, the thickness of the protective layer should be in the range 6-15 mils over the area of the chip pads.
The plastic encapsulant could be any material usually used for encapsulating integrated circuits. A low expansion coefficient material is preferred, and the encapsulant will typically have an expansion coefficient which is less than 25 ppm/°C. from -40° C. to 125° C.
Various additional modifications will become apparent to those skilled in the art. All such variations which basically rely on the teachings through which the invention had advanced the art are properly considered within the spirit and scope of the invention.

Claims (7)

What is claimed is:
1. A semiconductor device comprising:
a semiconductor chip electrically interconnected to metal leads by means of wires ball bonded to pads on a surface of the chip and extending from the pads to the leads, said wires including arched portions of a varying slope;
a thick protective layer formed over and limited to said surface of the chip and including areas over the pads, said layer formed to a thickness which covers at least a part of the arched portions where the slope of the wires is reduced to less than 45° relative to the chip surface, but does not cover the entire length of the wires, said layer comprising a material having a large expansion coefficient and low shear modulus; and
a plastic encapsulating material surrounding said chip, protective layer, a portion of said leads, and covering a portion of said wires.
2. The device according to claim 1 wherein the protective layer is an RTV silicone rubber.
3. The device according to claim 1 wherein the thickness of the protective layer is within the range 6-15 mils in the areas over the chip pads.
4. The device according to claim 1 wherein an air gap is formed between the protective layer and plastic encapsulating material having a width in the range 1-5 mils in the areas over the chip pads.
5. The device according to claim 1 wherein the protective layer material has an expansion coefficient of greater than 200 ppm/°C. and a shear modulus of less than 100 psi at -40° C. to 150° C.
6. The device according to claim 1 wherein the plastic encapsulating material comprises a material having a coefficient of expansion less than 25 ppm/°C. at -40° C. to 125° C.
7. A semiconductor device comprising:
a semiconductor chip electrically interconnected to metal leads by means of wires ball-bonded to pads on a surface of the chips and extending from the pads to the leads, said wires including arched portions;
a layer of RTV silicone rubber formed over and limited to said surface of the chip and including areas over the chip pads, said RTV layer formed to a cured thickness within the range 6-15 mils in the areas over the chip pads so that the RTV layer covers only a portion of the wires, said RTV layer having an expansion coefficient of at least 200 ppm/°C. at -40° C. to 150° C. and a shear modulus of less than 100 psi from -40° C. to 150° C.; and
a plastic encapsulating material surrounding said chip, RTV layer, a portion of said leads, and covering a portion of the wires, with a gap between the RTV layer and encapsulant within the range 1-5 mils at room temperature in the areas over the chip pads.
US06/526,413 1983-08-25 1983-08-25 Integrated circuit packages Abandoned USH73H (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US06/526,413 USH73H (en) 1983-08-25 1983-08-25 Integrated circuit packages
KR1019840003623A KR850002676A (en) 1983-08-25 1984-06-26 Integrated Circuit Chip Package
JP59175338A JPS6072251A (en) 1983-08-25 1984-08-24 Sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/526,413 USH73H (en) 1983-08-25 1983-08-25 Integrated circuit packages

Publications (1)

Publication Number Publication Date
USH73H true USH73H (en) 1986-06-03

Family

ID=24097238

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/526,413 Abandoned USH73H (en) 1983-08-25 1983-08-25 Integrated circuit packages

Country Status (3)

Country Link
US (1) USH73H (en)
JP (1) JPS6072251A (en)
KR (1) KR850002676A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331205A (en) * 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
US5917246A (en) * 1995-03-23 1999-06-29 Nippondenso Co., Ltd. Semiconductor package with pocket for sealing material
US20030024735A1 (en) * 2001-08-01 2003-02-06 Volker Strutz Protective device for subassemblies and method for producing a protective device
US20030119224A1 (en) * 1999-08-30 2003-06-26 Corisis David J. Semiconductor package
US7651891B1 (en) * 2007-08-09 2010-01-26 National Semiconductor Corporation Integrated circuit package with stress reduction
US20120061919A1 (en) * 2008-08-13 2012-03-15 Temic Automotive Of North America, Inc. Seal Apparatus and Method of Manufacturing the Same
US20190019784A1 (en) * 2015-09-04 2019-01-17 Kabushiki Kaisha Toshiba Semiconductor device and optical coupling device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331205A (en) * 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
US5917246A (en) * 1995-03-23 1999-06-29 Nippondenso Co., Ltd. Semiconductor package with pocket for sealing material
US20030119224A1 (en) * 1999-08-30 2003-06-26 Corisis David J. Semiconductor package
US7226813B2 (en) * 1999-08-30 2007-06-05 Micron Technology, Inc. Semiconductor package
US20030024735A1 (en) * 2001-08-01 2003-02-06 Volker Strutz Protective device for subassemblies and method for producing a protective device
US7235873B2 (en) * 2001-08-01 2007-06-26 Infineon Technologies Ag Protective device for subassemblies and method for producing a protective device
US7651891B1 (en) * 2007-08-09 2010-01-26 National Semiconductor Corporation Integrated circuit package with stress reduction
US20120061919A1 (en) * 2008-08-13 2012-03-15 Temic Automotive Of North America, Inc. Seal Apparatus and Method of Manufacturing the Same
US8689438B2 (en) * 2008-08-13 2014-04-08 Continental Automotive Systems, Inc. Seal apparatus and method of manufacturing the same
US20190019784A1 (en) * 2015-09-04 2019-01-17 Kabushiki Kaisha Toshiba Semiconductor device and optical coupling device
US10833055B2 (en) * 2015-09-04 2020-11-10 Kabushiki Kaisha Toshiba Semiconductor device and optical coupling device

Also Published As

Publication number Publication date
KR850002676A (en) 1985-05-15
JPS6072251A (en) 1985-04-24

Similar Documents

Publication Publication Date Title
US5358905A (en) Semiconductor device having die pad locking to substantially reduce package cracking
US6175149B1 (en) Mounting multiple semiconductor dies in a package
US6297547B1 (en) Mounting multiple semiconductor dies in a package
US5864174A (en) Semiconductor device having a die pad structure for preventing cracks in a molding resin
US7838973B2 (en) Semiconductor device
US5053852A (en) Molded hybrid IC package and lead frame therefore
US5319242A (en) Semiconductor package having an exposed die surface
US5441918A (en) Method of making integrated circuit die package
US5479050A (en) Leadframe with pedestal
US5021864A (en) Die-mounting paddle for mechanical stress reduction in plastic IC packages
WO2005124858A2 (en) Package and method for packaging an integrated circuit die
USH73H (en) Integrated circuit packages
US20030111716A1 (en) Wirebonded multichip module
US5278101A (en) Semiconductor device and method for manufacturing the same
EP0405330A2 (en) Flagless leadframe, package and method
US6737737B1 (en) Semiconductor package with chip supporting member
JPS6370532A (en) Semiconductor device
US4974054A (en) Resin molded semiconductor device
JPH08288428A (en) Resin-sealed semiconductor device
KR960005965A (en) Semiconductor devices
KR100475340B1 (en) Lead-on Chip Package
EP0410116B1 (en) Method of manufacturing a wire-bonded semiconductor device
JP3555790B2 (en) Semiconductor device
JPH06334106A (en) Resin-sealed semiconductor device
JPS635250Y2 (en)

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE