US8134227B2 - Stacked integrated circuit package system with conductive spacer - Google Patents
Stacked integrated circuit package system with conductive spacer Download PDFInfo
- Publication number
- US8134227B2 US8134227B2 US11/694,927 US69492707A US8134227B2 US 8134227 B2 US8134227 B2 US 8134227B2 US 69492707 A US69492707 A US 69492707A US 8134227 B2 US8134227 B2 US 8134227B2
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- US
- United States
- Prior art keywords
- integrated circuit
- conductive spacer
- conductive
- spacer structure
- interconnects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/694,927 US8134227B2 (en) | 2007-03-30 | 2007-03-30 | Stacked integrated circuit package system with conductive spacer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/694,927 US8134227B2 (en) | 2007-03-30 | 2007-03-30 | Stacked integrated circuit package system with conductive spacer |
Publications (2)
Publication Number | Publication Date |
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US20080237825A1 US20080237825A1 (en) | 2008-10-02 |
US8134227B2 true US8134227B2 (en) | 2012-03-13 |
Family
ID=39792807
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/694,927 Active 2027-04-02 US8134227B2 (en) | 2007-03-30 | 2007-03-30 | Stacked integrated circuit package system with conductive spacer |
Country Status (1)
Country | Link |
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US (1) | US8134227B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140008785A1 (en) * | 2012-07-05 | 2014-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package Redistribution Layer Structure and Method of Forming Same |
US20170170164A1 (en) * | 2015-12-09 | 2017-06-15 | Samsung Display Co., Ltd. | Integrated circuit assembly with heat spreader and method of making the same |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7868471B2 (en) * | 2007-09-13 | 2011-01-11 | Stats Chippac Ltd. | Integrated circuit package-in-package system with leads |
US8426955B2 (en) * | 2009-06-12 | 2013-04-23 | Stats Chippac Ltd. | Integrated circuit packaging system with a stack package and method of manufacture thereof |
US8564111B2 (en) | 2011-01-27 | 2013-10-22 | Siano Mobile Silicon Ltd. | Stacked digital/RF system-on-chip with integral isolation layer |
Citations (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5233504A (en) | 1990-12-06 | 1993-08-03 | Motorola, Inc. | Noncollapsing multisolder interconnection |
US5923090A (en) | 1997-05-19 | 1999-07-13 | International Business Machines Corporation | Microelectronic package and fabrication thereof |
US6137164A (en) * | 1998-03-16 | 2000-10-24 | Texas Instruments Incorporated | Thin stacked integrated circuit device |
US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
US20020164838A1 (en) * | 2001-05-02 | 2002-11-07 | Moon Ow Chee | Flexible ball grid array chip scale packages and methods of fabrication |
US20030038356A1 (en) * | 2001-08-24 | 2003-02-27 | Derderian James M | Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods |
US6528894B1 (en) * | 1996-09-20 | 2003-03-04 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
US6555917B1 (en) * | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
US6583512B2 (en) * | 2000-12-26 | 2003-06-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US6717253B2 (en) * | 2002-01-31 | 2004-04-06 | Advanced Semiconductor Engineering, Inc. | Assembly package with stacked dies and signal transmission plate |
US20040121521A1 (en) * | 2002-07-31 | 2004-06-24 | Jackson Timothy L. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods of fabrication and assemblies |
US20040126927A1 (en) * | 2001-03-05 | 2004-07-01 | Shih-Hsiung Lin | Method of assembling chips |
US6762488B2 (en) * | 2002-03-19 | 2004-07-13 | Nec Electronics Corporation | Light thin stacked package semiconductor device and process for fabrication thereof |
US6768190B2 (en) * | 2002-01-25 | 2004-07-27 | Advanced Semiconductor Engineering, Inc. | Stack type flip-chip package |
US20040201088A1 (en) * | 2003-04-08 | 2004-10-14 | Samsung Electronics Co., Ltd. | Semiconductor multi-chip package and fabrication method |
US6820329B2 (en) * | 2001-12-14 | 2004-11-23 | Advanced Semiconductor Engineering, Inc. | Method of manufacturing multi-chip stacking package |
US20040238934A1 (en) * | 2001-08-28 | 2004-12-02 | Tessera, Inc. | High-frequency chip packages |
US6833628B2 (en) * | 2002-12-17 | 2004-12-21 | Delphi Technologies, Inc. | Mutli-chip module |
US20050006785A1 (en) * | 2002-06-04 | 2005-01-13 | Siliconware Precision Industries Co., Ltd. | Manufacturing method for multichip module |
US6857470B2 (en) * | 2002-11-20 | 2005-02-22 | Samsung Electronics Co., Ltd. | Stacked chip package with heat transfer wires |
US6870269B2 (en) * | 2001-10-15 | 2005-03-22 | Micron Technology, Inc. | Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods |
US6885093B2 (en) * | 2002-02-28 | 2005-04-26 | Freescale Semiconductor, Inc. | Stacked die semiconductor device |
US6894395B2 (en) * | 2002-02-13 | 2005-05-17 | Sony Corporation | System on a chip device including a re-wiring layer formed between groups of electronic devices |
US20050110126A1 (en) * | 2003-11-25 | 2005-05-26 | Kai-Chiang Wu | Chip adhesive |
US6921968B2 (en) * | 2003-05-02 | 2005-07-26 | Advance Semiconductor Engineering, Inc. | Stacked flip chip package |
US6933176B1 (en) | 2002-07-19 | 2005-08-23 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US20050253240A1 (en) * | 2002-06-12 | 2005-11-17 | Wolfgang Nuechter | Micromechanical component and corresponsing production method |
US20050258545A1 (en) * | 2004-05-24 | 2005-11-24 | Chippac, Inc. | Multiple die package with adhesive/spacer structure and insulated die surface |
US20050269676A1 (en) * | 2004-05-24 | 2005-12-08 | Chippac, Inc | Adhesive/spacer island structure for stacking over wire bonded die |
US6977439B2 (en) | 2002-03-21 | 2005-12-20 | Samsung Electronics Co., Ltd. | Semiconductor chip stack structure |
US7005316B2 (en) | 2001-04-17 | 2006-02-28 | Micron Technology, Inc. | Method for package reduction in stacked chip and board assemblies |
US7024947B2 (en) * | 2002-03-07 | 2006-04-11 | Alps Electric Co., Ltd. | Detection device including circuit component |
US20060091562A1 (en) * | 2004-10-29 | 2006-05-04 | Hsin-Hui Lee | Flip chip BGA process and package with stiffener ring |
US20060097402A1 (en) * | 2004-11-08 | 2006-05-11 | Siliconware Precision Industries Co., Ltd. | Semiconductor device having flip-chip package and method for fabricating the same |
US20060197209A1 (en) * | 2005-02-10 | 2006-09-07 | Stats Chippac Ltd. | Stacked integrated circuits package system with dense routability and high thermal conductivity |
US20060289980A1 (en) * | 2005-06-22 | 2006-12-28 | Chang Hong T | Stacked memory card and method for manufacturing the same |
US7189593B2 (en) * | 2002-01-09 | 2007-03-13 | Micron Technology, Inc. | Elimination of RDL using tape base flip chip on flex for die stacking |
US20070152313A1 (en) * | 2005-12-29 | 2007-07-05 | Shanggar Periaman | Stacked die semiconductor package |
US7245003B2 (en) * | 2004-06-30 | 2007-07-17 | Intel Corporation | Stacked package electronic device |
US20070194415A1 (en) * | 2006-02-20 | 2007-08-23 | Seng Eric T S | Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies |
US20070216005A1 (en) * | 2006-03-17 | 2007-09-20 | Stats Chippac Ltd. | Integrated circuit package-in-package system |
US20070257348A1 (en) * | 2006-05-08 | 2007-11-08 | Advanced Semiconductor Engineering, Inc. | Multiple chip package module and method of fabricating the same |
US20070278657A1 (en) * | 2006-05-30 | 2007-12-06 | Samsung Electronics Co. Ltd. | Chip stack, method of fabrication thereof, and semiconductor package having the same |
US20070284756A1 (en) * | 2006-06-12 | 2007-12-13 | Advanced Semiconductor Engineering, Inc. | Stacked chip package |
US7309913B2 (en) * | 2003-01-23 | 2007-12-18 | St Assembly Test Services Ltd. | Stacked semiconductor packages |
US20080042265A1 (en) * | 2006-08-15 | 2008-02-21 | Merilo Leo A | Chip scale module package in bga semiconductor package |
US7355274B2 (en) * | 2004-12-10 | 2008-04-08 | Samsung Electronics Co., Ltd. | Semiconductor package, manufacturing method thereof and IC chip |
US7420814B2 (en) * | 2004-10-07 | 2008-09-02 | Samsung Electronics Co., Ltd. | Package stack and manufacturing method thereof |
US7435619B2 (en) * | 2006-02-14 | 2008-10-14 | Stats Chippac Ltd. | Method of fabricating a 3-D package stacking system |
US20080280396A1 (en) * | 2005-02-22 | 2008-11-13 | Micron Technology, Inc. | Stacked die package for peripheral and center device pad layout device |
US7518226B2 (en) * | 2007-02-06 | 2009-04-14 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
US20090174051A1 (en) * | 2004-01-22 | 2009-07-09 | Shuichi Osaka | Semiconductor package and semiconductor device |
-
2007
- 2007-03-30 US US11/694,927 patent/US8134227B2/en active Active
Patent Citations (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5233504A (en) | 1990-12-06 | 1993-08-03 | Motorola, Inc. | Noncollapsing multisolder interconnection |
US6528894B1 (en) * | 1996-09-20 | 2003-03-04 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
US5923090A (en) | 1997-05-19 | 1999-07-13 | International Business Machines Corporation | Microelectronic package and fabrication thereof |
US6137164A (en) * | 1998-03-16 | 2000-10-24 | Texas Instruments Incorporated | Thin stacked integrated circuit device |
US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
US6583512B2 (en) * | 2000-12-26 | 2003-06-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
US20040126927A1 (en) * | 2001-03-05 | 2004-07-01 | Shih-Hsiung Lin | Method of assembling chips |
US7005316B2 (en) | 2001-04-17 | 2006-02-28 | Micron Technology, Inc. | Method for package reduction in stacked chip and board assemblies |
US20020164838A1 (en) * | 2001-05-02 | 2002-11-07 | Moon Ow Chee | Flexible ball grid array chip scale packages and methods of fabrication |
US20030038356A1 (en) * | 2001-08-24 | 2003-02-27 | Derderian James M | Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods |
US7268426B2 (en) * | 2001-08-28 | 2007-09-11 | Tessera, Inc. | High-frequency chip packages |
US20040238934A1 (en) * | 2001-08-28 | 2004-12-02 | Tessera, Inc. | High-frequency chip packages |
US6555917B1 (en) * | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
US6870269B2 (en) * | 2001-10-15 | 2005-03-22 | Micron Technology, Inc. | Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods |
US6820329B2 (en) * | 2001-12-14 | 2004-11-23 | Advanced Semiconductor Engineering, Inc. | Method of manufacturing multi-chip stacking package |
US7189593B2 (en) * | 2002-01-09 | 2007-03-13 | Micron Technology, Inc. | Elimination of RDL using tape base flip chip on flex for die stacking |
US6768190B2 (en) * | 2002-01-25 | 2004-07-27 | Advanced Semiconductor Engineering, Inc. | Stack type flip-chip package |
US6717253B2 (en) * | 2002-01-31 | 2004-04-06 | Advanced Semiconductor Engineering, Inc. | Assembly package with stacked dies and signal transmission plate |
US6894395B2 (en) * | 2002-02-13 | 2005-05-17 | Sony Corporation | System on a chip device including a re-wiring layer formed between groups of electronic devices |
US6885093B2 (en) * | 2002-02-28 | 2005-04-26 | Freescale Semiconductor, Inc. | Stacked die semiconductor device |
US7211466B2 (en) * | 2002-02-28 | 2007-05-01 | Freescale Semiconductor, Inc. | Stacked die semiconductor device |
US7024947B2 (en) * | 2002-03-07 | 2006-04-11 | Alps Electric Co., Ltd. | Detection device including circuit component |
US6762488B2 (en) * | 2002-03-19 | 2004-07-13 | Nec Electronics Corporation | Light thin stacked package semiconductor device and process for fabrication thereof |
US6977439B2 (en) | 2002-03-21 | 2005-12-20 | Samsung Electronics Co., Ltd. | Semiconductor chip stack structure |
US20050006785A1 (en) * | 2002-06-04 | 2005-01-13 | Siliconware Precision Industries Co., Ltd. | Manufacturing method for multichip module |
US20050253240A1 (en) * | 2002-06-12 | 2005-11-17 | Wolfgang Nuechter | Micromechanical component and corresponsing production method |
US6933176B1 (en) | 2002-07-19 | 2005-08-23 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US20040121521A1 (en) * | 2002-07-31 | 2004-06-24 | Jackson Timothy L. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods of fabrication and assemblies |
US6857470B2 (en) * | 2002-11-20 | 2005-02-22 | Samsung Electronics Co., Ltd. | Stacked chip package with heat transfer wires |
US6833628B2 (en) * | 2002-12-17 | 2004-12-21 | Delphi Technologies, Inc. | Mutli-chip module |
US7309913B2 (en) * | 2003-01-23 | 2007-12-18 | St Assembly Test Services Ltd. | Stacked semiconductor packages |
US20040201088A1 (en) * | 2003-04-08 | 2004-10-14 | Samsung Electronics Co., Ltd. | Semiconductor multi-chip package and fabrication method |
US6921968B2 (en) * | 2003-05-02 | 2005-07-26 | Advance Semiconductor Engineering, Inc. | Stacked flip chip package |
US20050110126A1 (en) * | 2003-11-25 | 2005-05-26 | Kai-Chiang Wu | Chip adhesive |
US20090174051A1 (en) * | 2004-01-22 | 2009-07-09 | Shuichi Osaka | Semiconductor package and semiconductor device |
US20050258545A1 (en) * | 2004-05-24 | 2005-11-24 | Chippac, Inc. | Multiple die package with adhesive/spacer structure and insulated die surface |
US20050269676A1 (en) * | 2004-05-24 | 2005-12-08 | Chippac, Inc | Adhesive/spacer island structure for stacking over wire bonded die |
US7245003B2 (en) * | 2004-06-30 | 2007-07-17 | Intel Corporation | Stacked package electronic device |
US20070278645A1 (en) * | 2004-06-30 | 2007-12-06 | Intel Corporation | Stacked package electronic device |
US7420814B2 (en) * | 2004-10-07 | 2008-09-02 | Samsung Electronics Co., Ltd. | Package stack and manufacturing method thereof |
US20060091562A1 (en) * | 2004-10-29 | 2006-05-04 | Hsin-Hui Lee | Flip chip BGA process and package with stiffener ring |
US20060097402A1 (en) * | 2004-11-08 | 2006-05-11 | Siliconware Precision Industries Co., Ltd. | Semiconductor device having flip-chip package and method for fabricating the same |
US7355274B2 (en) * | 2004-12-10 | 2008-04-08 | Samsung Electronics Co., Ltd. | Semiconductor package, manufacturing method thereof and IC chip |
US20060197209A1 (en) * | 2005-02-10 | 2006-09-07 | Stats Chippac Ltd. | Stacked integrated circuits package system with dense routability and high thermal conductivity |
US20080280396A1 (en) * | 2005-02-22 | 2008-11-13 | Micron Technology, Inc. | Stacked die package for peripheral and center device pad layout device |
US20060289980A1 (en) * | 2005-06-22 | 2006-12-28 | Chang Hong T | Stacked memory card and method for manufacturing the same |
US20070152313A1 (en) * | 2005-12-29 | 2007-07-05 | Shanggar Periaman | Stacked die semiconductor package |
US7279795B2 (en) * | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
US7435619B2 (en) * | 2006-02-14 | 2008-10-14 | Stats Chippac Ltd. | Method of fabricating a 3-D package stacking system |
US20070194415A1 (en) * | 2006-02-20 | 2007-08-23 | Seng Eric T S | Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies |
US20070216005A1 (en) * | 2006-03-17 | 2007-09-20 | Stats Chippac Ltd. | Integrated circuit package-in-package system |
US20100230796A1 (en) * | 2006-03-17 | 2010-09-16 | Choong Bin Yim | Integrated circuit package-in-package system and method for making thereof |
US20070257348A1 (en) * | 2006-05-08 | 2007-11-08 | Advanced Semiconductor Engineering, Inc. | Multiple chip package module and method of fabricating the same |
US20070278657A1 (en) * | 2006-05-30 | 2007-12-06 | Samsung Electronics Co. Ltd. | Chip stack, method of fabrication thereof, and semiconductor package having the same |
US20070284756A1 (en) * | 2006-06-12 | 2007-12-13 | Advanced Semiconductor Engineering, Inc. | Stacked chip package |
US20080042265A1 (en) * | 2006-08-15 | 2008-02-21 | Merilo Leo A | Chip scale module package in bga semiconductor package |
US7518226B2 (en) * | 2007-02-06 | 2009-04-14 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140008785A1 (en) * | 2012-07-05 | 2014-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package Redistribution Layer Structure and Method of Forming Same |
US9548283B2 (en) * | 2012-07-05 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package redistribution layer structure and method of forming same |
US20170170164A1 (en) * | 2015-12-09 | 2017-06-15 | Samsung Display Co., Ltd. | Integrated circuit assembly with heat spreader and method of making the same |
US9978663B2 (en) * | 2015-12-09 | 2018-05-22 | Samsung Display Co., Ltd. | Integrated circuit assembly with heat spreader and method of making the same |
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