US7752478B2 - Apparatus and method for real time tracking using a quadrature interface - Google Patents
Apparatus and method for real time tracking using a quadrature interface Download PDFInfo
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- US7752478B2 US7752478B2 US11/527,181 US52718106A US7752478B2 US 7752478 B2 US7752478 B2 US 7752478B2 US 52718106 A US52718106 A US 52718106A US 7752478 B2 US7752478 B2 US 7752478B2
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- clock signal
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- clock
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
Definitions
- This description relates to digital logic and computer hardware.
- this description concerns tracking of a real time clock signal.
- Computers may be equipped with a real time clock (“RTC”) that is used to provide current time and date information to a user.
- RTC real time clock
- a RTC generally refers to a clock that is independent of the perations of the computer on which the clock runs, and that therefore must be able to track a current time even when the computer is turned off, in a power-saving mode, or performing other processing.
- the RTC thus provides a computer user with the familiar and convenient experience of viewing the current date and time, e.g., while using the computer.
- the RTC may be used to provide software applications that rely on a knowledge of a current date and time, such as, for example, calendar and/or appointment applications.
- a RTC may provide, for example, year, month, week, hour and second information.
- the RTC may include, or rely on, a periodic pulse signal, as well as a state mechanism or counter that may be used to track/count transitions of the periodic pulse signal between states.
- a Central Processing Unit CPU may be used to monitor transitions between states of the RTC.
- the RTC should operate accurately even when the computer is off or in a low-power mode.
- some computing devices may periodically enter a low power mode, in order to conserve battery life.
- the computing device e.g., for the CPU of the computing device
- the computing device may be unable to monitor the incoming RTC signal when in a low power mode. Consequently, the computing device (e.g., CPU) may be required to ‘wake up’ or enter a normal operating mode in order to track the incoming RTC signal in an accurate manner.
- a benefit of the low power mode may be lost or reduced, e.g., battery life for a battery of the computing device may be spent that could otherwise be conserved.
- an apparatus for tracking a real time clock includes a delay element for receiving a first clock signal and providing a second delayed clock signal, a quadrature interface including a first input and a second input, wherein the first input receives the first clock signal and the second input receives the second clock signal, control logic adapted to provide a state machine including four states, the four states respectively corresponding to a 2-bit gray code such that a current state is selected by determining a correspondence of the first and second inputs to the 2-bit gray code, and the control logic is further adapted to provide a counter, the counter incremented upon a transition between a first state and a second state of the state machine.
- a real time clock may be tracked.
- a second clock signal is generated from a first clock signal, where the second clock signal comprises a delayed replica of the first clock signal.
- a current state is selected from four states respectively corresponding to a 2-bit gray code, wherein the current state is determined by a correspondence of first clock signal and the second clock signal to the 2-bit gray code.
- a counter may be incremented upon a transition between a first state and a second state of the four states.
- a human interface device (“HID”) with real time clock tracking includes a quadrature interface, the quadrature interface including a first input and a second input, wherein the first input receives a clock signal and the second input receives a delayed replica of the clock signal.
- the HID also includes control logic adapted to provide a state machine including four states, the four states respectively corresponding to a 2-bit gray code and wherein a current state is selected by determining a correspondence of first and second inputs to the 2-bit gray code.
- the control logic is further adapted to provide a counter configured to be incremented upon a transition between a first state and a second state of the state machine.
- FIG. 1 is a block diagram of an apparatus for tracking a real time clock according to one embodiment.
- FIG. 2 is a block diagram of a state machine that may be used in the apparatus of FIG. 1 .
- FIG. 3 is a flowchart for a process implementing a state machine on a CPU according to one embodiment.
- FIG. 4 is a timing diagram for a clock pulse and delayed clock pulse signal according to one embodiment.
- FIG. 5 is a timing diagram showing a relationship between real time and a counter according to one embodiment.
- FIG. 6 is a detailed block diagram of a quadrature interface including a state machine, which may be used for tracking a RTC.
- FIG. 1 is a block diagram of an apparatus 100 for tracking a real time clock (RTC) 102 according to one embodiment.
- the apparatus 100 provides a low power solution for tracking the RTC 102 of a computing device 101 , where the apparatus 100 requires few, if any, additions or modifications to existing hardware of the computing device 101 .
- the apparatus 100 provides tracking of the RTC 102 using a human interface device (“HID”) 110 , or, more specifically, using a power island 120 that is associated with the HID 110 and that may be independent of a power supply 101 c of the computing device 101 (or of a separate power supply of the HID 110 , not shown).
- the power island 120 may be used to provide a low power operation mode for the HID 110 , and, in so doing, offers the ability to track the RTC 102 with reduced power, thereby reducing or eliminating use of a CPU 101 a or power supply 101 c of the 4 . computing device 101 in tracking the RTC 102 .
- the HID 110 should generally be understood to represent and include virtually any device that allows a human user to interface with the computing device 101 .
- the HID 110 may include a mouse, keyboard, pointing device, trackball, touchpad, joystick, or any device that translates a detected human action into an action of the computing device 101 .
- Such actions of the computing device 101 should be apparent, and may include, for example, modification of a display or other output of the computing device, or performance of a calculation or other computation of the computing device 101 .
- the HID 110 may interfacer with, or connect to, the computing device 101 using any of a number of known techniques.
- the HID 110 may plug into a Universal Serial Bus (USB) port (not illustrated in FIG. 1 ) of the computing device 101 , or may communicate with the computing device 101 using a Bluetooth or other wireless connection.
- USB Universal Serial Bus
- the computing device 101 is illustrated generically as including the RTC 102 , the CPU 101 a , the memory 101 b , and the power supply 101 c ; however, it should be understood that many other distribution of components may be included, depending on a nature and use of the computing device 101 .
- the HID 110 may-be integrated or otherwise incorporated into the computing device 101 .
- the RTC 102 may be implemented as a module on the HID 110 .
- the HID 110 interfaces with the computing device 101 in the example of FIG. 1 using a quadrature interface 105 .
- the quadrature interface 105 may be used during normal operation of the HID, 110 , for example, to determine both a movement and a direction of the HID 110 .
- known optical or mechanical techniques may be used to create a two phase output to be translated into a motion and direction of a cursor or other pointer on a display of the computing device 101 (e.g., along a defined x-axis and y-axis).
- the HID 110 is used to track the RTC 102 in a manner that minimizes power consumption of the power supply 101 c of the computing device 101 , while maintaining an accuracy and availability of the RTC 102 . More specifically, the HID 110 is configured to use/provide suitable signals conforming to the quadrature interface 105 , but that also maintain state information associated with the RTC 102 (e.g., indicating time and date).
- the quadrature interface 105 may include Qx input 116 and Qy input 114 .
- the RTC 102 provides a clock pulse signal ( ⁇ ) 121 , which is received at the Qx input 116 and at a delay element 112 .
- the delay element 112 may thus generate a delayed clock pulse signal ( ⁇ ′) 123 .
- clock pulse signal 121 is provided to Qx input 116 on quadrature interface 105 .
- Delayed clock pulse signal 123 is provided to Qy input 114 on quadrature interface 105 .
- the delay element 112 may be any apparatus for receiving an input signal and supplying a delayed replica of the input signal.
- delay element 112 may include a circuit characterized by a resistor-capacitor (RC) time constant, which may be as simple as a resistor and capacitor coupled in a series connection.
- RC resistor-capacitor
- other delay elements e.g., a buffer chain, also may be used, as would be apparent.
- the HID 110 may operate in a low-power mode and be supplied with power by the power island 120 .
- HID may include hardware circuitry configured to execute a state machine 122 and a counter 124 .
- the state machine 122 and counter 124 may be updated as a function of signals received at Qx input 116 and Qy input 114 .
- state machine 122 and counter 124 may be implemented directly on quadrature interface 105 .
- Power island 120 may provide an isolated island of power for HID 110 .
- HID 110 may operate in a very low quiescent power mode utilizing power only from power island 120 while CPU 101 a is in a sleep mode.
- CPU 101 a may be awakened upon generation of an interrupt, for example when a user interacts with a peripheral device such as a mouse coupled to HID 110 . Consequently, a count from the counter 124 may be used to track RTC 102 , even when the CPU 101 a and/or the HID 110 are in a low power niode(s).
- HID 110 includes a clock 604 , which may operate at lower power than a clock driving CPU 101 a .
- state machine 122 and counter 124 which provide for tracking of RTC 102 without the involvement of processor 101 a (which would typically require higher power) and can operate at low power, only requiring the quiescent power provided by power island 120 .
- the structure of state machine 122 and its relationship to signals received at Qx input 116 and Qy input 114 are described in more detail below.
- FIG. 2 is a block diagram of a state machine according to one embodiment.
- the state machine 122 may be configured to implement four states 124 ( 1 )- 124 ( 4 ) and a state transition matrix (not shown).
- States 124 ( 1 )- 124 ( 4 ) correspond to 2-bit gray codes 00 , 10 , 11 and 01 , respectively.
- a current state among states 124 ( 1 )- 124 ( 4 ) may be determined as a function of clock pulse signal 121 and delayed clock pulse signal 123 .
- the first digit of a gray code may correspond to clock pulse signal 121
- the second digit of a gray code may correspond to the delayed clock pulse signal 123
- these roles may be reversed, and the first digit of a gray code may correspond to the delayed clock pulse signal 123
- the second digit of a gray code may correspond to the clock pulse signal 121 .
- each clock pulse signal 121 , 123 may be high or low, four possible states result, which may be represented in binary form gray code signal(s) as 00 , 01 , 10 , and 11 .
- state 124 ( 1 ) is selected. If clock pulse 121 is high and delayed clock pulse 123 is low, state 124 ( 2 ) is selected. If both clock pulse 121 and delayed clock pulse 123 are high, state 124 ( 3 ) is selected. Finally, if clock pulse 121 is low and delayed clock pulse 123 is high, state 124 ( 4 ) is selected.
- clock pulse 121 and delayed clock pulse 123 may be configured such that states 124 ( 1 )- 124 ( 4 ) are visited in a cyclical fashion. That is, the combination of clock pulse 121 and delayed clock pulse 123 may be used to describe a gray code.
- state machine 122 may be implemented in hardware. According to an alternative example embodiment, state machine 122 may be implemented on a general purpose central processing unit (“CPU”). For example, some or all of the quadrature interface 105 , the processor 125 (or other dedicated hardware), the state machine 122 , and/or the counter 124 may be implemented in the context of one or more integrated circuit microchip(s) (chip(s)).
- CPU central processing unit
- FIG. 3 is a flowchart for a process implementing a state machine on a CPU according to one embodiment.
- the process is initiated i( 351 ).
- Qx input 116 is polled to detect a clock edge, and, if a clock edge is detected on Qx input 116 ( 352 ), then the counter 124 (count) is incremented ( 350 ). If no clock edge is detected on Qx input 116 ( 352 ), then Qx is again (and repeatedly) polled for a clock edge.
- Qy input 114 also may be polled to detect a clock edge ( 356 ). If a clock edge is detected on Qy input 114 ( 356 ), then the counter 124 is incremented ( 354 ). If no clock edge is detected on the Qy input ( 356 ), then Qy is again (and repeatedly) polled for a clock edge ( 356 ).
- FIG. 4 is a timing diagram for a clock pulse and delayed clock pulse signal according to one embodiment.
- both clock pulse signal 121 and delayed clock pulse signal 123 are low and state 124 ( 1 ) is selected (gray code 00 ).
- clock pulse signal 121 goes high while delayed clock pulse signal 123 remains low and between times t 1 and t 2 state 124 ( 2 ) is selected (gray code 10 ).
- delayed clock signal 123 goes high while clock signal 121 remains high and between times t 2 and t 3 state 124 ( 3 ) is selected (gray code 11 ).
- clock signal 121 goes low while delayed clock signal 123 remains high and between times t 3 and t 4 state 124 ( 4 ) is selected (gray code 01 ).
- FIG. 5 is a timing diagram showing a relationship between real time and a counter according to one embodiment.
- the example of FIG. 5 shows a relationship between real time 520 and a counter variable (“CountX”) 510 .
- Clock pulse 121 signal has period DeltaT.
- CountX 510 is incremented upon a state transition of state machine 122 (see FIG. 2 ) and therefore upon either an edge transition of clock pulse 121 or delayed clock pulse 123 . Thus, upon a complete cycle through state machine 122 , CountX is incremented by 4 .
- FIG. 6 is a detailed block diagram of a quadrature interface including a state machine, which may be used for tracking a RTC.
- state machine 122 may be included as part of HID 110 but according to an alternative example embodiment may be included as part of quadrature interface 105 as shown in FIG. 6 .
- State machine 122 includes flip flops 602 ( 1 )- 602 ( 4 ), clock 604 , decision logic 606 and count register 608 .
- flip flops 602 ( 1 ) and 602 ( 3 ) track a next state for state machine 122 while flip flops 602 ( 2 ) and 602 ( 4 ) track a current state for state machine 122 .
- Clock 604 may be a low power clock, which among other functions, may be used to drive latching of signals in flip flops 602 ( 1 )- 602 ( 4 ).
- flip flops 602 ( 1 ) and 602 ( 3 ) store a next state for state machine 122
- the state of flip flop 602 ( 1 ) is transmitted to flip flop 602 ( 2 ) and the state of flip flop 602 ( 3 ) is transmitted to flip flop 602 ( 4 ). That is, the current state (stored in flip flops 602 ( 2 ) and 602 ( 4 )) is replaced by the next state (stored in flip flops 601 ( 1 ) and 601 ( 3 )).
- flip flops 602 ( 1 ) and 602 ( 3 ) track a next state for state machine 122 .
- flip flop 602 ( 1 ) tracks a next state for Qx and flip flop 602 ( 3 ) tracks a next state for Qy.
- decision logic 606 controls whether count register 608 should be incremented. According to one embodiment, count register 608 is incremented only if the next state stored in flip flops 602 ( 1 ) and 602 ( 3 ) is a valid next state from the current state stored in flip flops 602 ( 2 ) and 602 ( 4 ). In particular, according to one example embodiment, decision logic 606 only causes count register 608 to be incremented if the next state is related to the current state as a succeeding element of a gray code as described above. Next and current states may not be successive elements of a gray code, for example, if noise has introduced errors.
- clock 604 operates at at least twice the frequency between edges of clock signal 121 and delayed clock signal 123 .
- clock 604 may operate at a frequency of at least 2*(1/(t 2 ⁇ t 1 )).
Abstract
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US11/527,181 US7752478B2 (en) | 2006-09-26 | 2006-09-26 | Apparatus and method for real time tracking using a quadrature interface |
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US11/527,181 US7752478B2 (en) | 2006-09-26 | 2006-09-26 | Apparatus and method for real time tracking using a quadrature interface |
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DE102008039795B3 (en) * | 2008-08-26 | 2010-01-07 | Fujitsu Siemens Computers Gmbh | Computer system and method for power-saving operation of a computer system |
US8782454B2 (en) * | 2011-10-28 | 2014-07-15 | Apple Inc. | System and method for managing clock speed based on task urgency |
CN103746787B (en) * | 2013-12-30 | 2017-04-19 | 科大智能科技股份有限公司 | Multi-channel real-time full duplex carrier communication equipment |
Citations (7)
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US4295224A (en) * | 1978-08-16 | 1981-10-13 | Sony Corporation | Tuning indicator apparatus for a frequency synthesizer tuner |
US4599600A (en) * | 1983-10-24 | 1986-07-08 | Red Lion Controls | Conversion of quadrature signals into counter control pulses |
US4714913A (en) * | 1985-07-16 | 1987-12-22 | Cohen Robert K | Quadrature phase signal processor |
US5021781A (en) * | 1989-10-18 | 1991-06-04 | Pitney Bowes Inc. | Two stage quadrature incremental encoder |
US5854915A (en) * | 1996-11-22 | 1998-12-29 | Vlsi Technology, Inc. | Keyboard controller with integrated real time clock functionality and method therefor |
US6097319A (en) * | 1998-05-18 | 2000-08-01 | Primax Electronics Ltd. | Quadrature encoding device with slope-triggered digitizing circuit |
US6380927B1 (en) * | 1999-11-17 | 2002-04-30 | Microsoft Corporation | Determining the position of a detented optical encoder |
-
2006
- 2006-09-26 US US11/527,181 patent/US7752478B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4295224A (en) * | 1978-08-16 | 1981-10-13 | Sony Corporation | Tuning indicator apparatus for a frequency synthesizer tuner |
US4599600A (en) * | 1983-10-24 | 1986-07-08 | Red Lion Controls | Conversion of quadrature signals into counter control pulses |
US4714913A (en) * | 1985-07-16 | 1987-12-22 | Cohen Robert K | Quadrature phase signal processor |
US5021781A (en) * | 1989-10-18 | 1991-06-04 | Pitney Bowes Inc. | Two stage quadrature incremental encoder |
US5854915A (en) * | 1996-11-22 | 1998-12-29 | Vlsi Technology, Inc. | Keyboard controller with integrated real time clock functionality and method therefor |
US6097319A (en) * | 1998-05-18 | 2000-08-01 | Primax Electronics Ltd. | Quadrature encoding device with slope-triggered digitizing circuit |
US6380927B1 (en) * | 1999-11-17 | 2002-04-30 | Microsoft Corporation | Determining the position of a detented optical encoder |
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