US7099818B1 - System and method for automatically matching components in a debugging system - Google Patents
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- US7099818B1 US7099818B1 US10/113,065 US11306502A US7099818B1 US 7099818 B1 US7099818 B1 US 7099818B1 US 11306502 A US11306502 A US 11306502A US 7099818 B1 US7099818 B1 US 7099818B1
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- circuit emulator
- host computer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
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- the present invention relates to the field of software and hardware development. Specifically, embodiments of the present invention relates to development tools, especially useful for debugging microcontroller programs.
- Debugging software effectuates correction of problems in software by finding errors in program logic, and in hardware by finding errors in circuitry.
- Debuggers stop programs at certain breakpoints and display various programming elements regarding the machine's internal state. This allows programmers to step through program source code statements individually and sequentially, while corresponding machine instructions are being executed and observed, and correct and/or modify the code as necessary.
- Debuggers may deploy an in-circuit emulator (ICE) to follow certain functions and features of a device, such as a microcontroller or other integrated circuit (IC).
- ICE in-circuit emulator
- the ICE thus allows debugger software to place code within a device under test, set breakpoints and other debugging functions therein, and prompt the device under test to implement supervisory and other debugging operations.
- These ICE functions further allow the debugger software to “look into” memory, registers, and other internal resources of the device under test to observe the effects corresponding to the execution of the program code.
- An IC device such as a microcontroller
- the pod electrically interconnects the microcontroller or other IC to be tested with the ICE.
- Information may change with each different device. Such information may include the way in which decoding of supervisory operational codes are performed. The types of information that might change with each different device may also include the reset sequence of the device. Further, the types of information that might change with each different device may include the way in which the device is programmed.
- ICE's are typically required for each different microcontroller or other IC that needs to be tested and debugged. Further, if the same microcontroller or other IC to which a particular ICE corresponds is deployed upon a different pod, yet another separate ICE may be required. In general, a particular emulator is limited to operating with a single type of microcontroller or other IC.
- a user of a conventional debugging system may thus be forced to access and maintain a variety of different ICE's for each and every microcontroller or other IC they test. Also, each time a user of a conventional debugging system changes the microcontrollers or other ICs to be tested, they must acquire the corresponding ICE. Further, a user of a conventional debugging system who is developing new microcontrollers or other ICs must develop corresponding ICEs to test them. A user may thus find a conventional debugging system problematic for a number of reasons.
- a conventional debugging system may require access to a variety of different ICEs for each and every microcontroller or other IC they must test. This may limit the flexibility of the conventional debugging system, especially when microcontrollers or other ICs in use change. Also, ICEs are not inexpensive, and upon acquisition, they must be properly selected, stored and maintained. This adds expense to the cost of a debugging system.
- Embodiments of the present invention allow the same ICE base unit and the same software (e.g., a universal developer kit) to be applied with a multiple number of pod combinations with microcontrollers and other IC devices the pods may deploy.
- the debugger's component matching software causes a unique identifier of the microcontroller or other IC device to be read, identifying it to the ICE and the rest of the debugging system.
- a software tool contains different plug-in modules, each applicable for a different version of the devices that may be recognized.
- the software Upon determining the device's version identifier, the software automatically loads the corresponding plug-in into the ICE base unit.
- the plug-in is loaded into a field programmable gate array (FPGA) in the ICE.
- the plug-in may be loaded into a microcontroller, a complex programmable logic device (CPLD), or another programmable functionality within the ICE.
- the proper plug-in module is automatically activated on the software tool in the host computer. Automatically, the software tool and the ICE base unit become compatible with whatever device version is deployed upon the pod.
- an embodiment of the present invention effectuates a debugging system.
- the present embodiment allows communications between the device and the rest of the debugging system by programming the ICE with a first logic set.
- the first logic set enables the ICE to establish communications with the device and determine a unique identifier of the device.
- the ICE communicates the device's unique identifier back to the host computer.
- the host computer matches the unique identifier to a second logic set and a plug-in module, in one embodiment by referencing a database of corresponding device identifiers and programs and plug-in modules.
- the host computer then programs the ICE with the second logic set and activates the plug-in module.
- the second logic set allows the ICE and the device to execute program instructions downloaded with the second logic set in lock-step fashion to perform the debugging functions.
- the plug-in module allows the host computer to interact in the debugging process as necessary. This achieves flexibility, because any ICE may be programmed to communicate with any device.
- FIG. 1 illustrates a general purpose computer system, upon which embodiments of the present invention may be implemented.
- FIG. 2 is a block diagram of a system for implementing a debugger universal developer, in accordance with one embodiment of the present invention.
- FIG. 3 is a diagram of a component matcher of a system for implementing a debugger universal developer, in accordance with one embodiment of the present invention.
- FIG. 4 is a diagram of a component matcher connected via a network to a database, in accordance with one embodiment of the present invention.
- FIG. 5 is a flow chart of a method for component matching by a debugger universal developer, in accordance with an embodiment of the present invention.
- FIG. 5 refers to process 500 , performed in accordance with embodiments of the present invention for debugging which, in one embodiment, are carried out by processors and electricavelectronic components under the control of computer readable and computer executable instructions.
- the computer readable and computer executable instructions reside, for example, in data storage features such as data storage device 118 ( FIG. 1 ) and computer usable volatile memory 104 ( FIG. 1 ) and/or computer usable non-volatile memory 106 ( FIG. 1 ).
- the computer readable and computer executable instructions may reside in any type of computer readable medium.
- Process 500 may be performed by, e.g., executed upon software, firmware, and/or hardware or any combination of software, firmware, hardware, and/or by other effective mechanism or instrumentality, e.g., by other suitable means.
- FIG. 1 is a block diagram of one embodiment of an exemplary computer system 100 that can be used, for example, as a platform for embodiments of the present invention.
- System 100 is well suited to be any type of computing device (e.g., browser client computer, server computer, portable computing device, etc.).
- Computer system 100 of FIG. 1 comprises an address/data bus 110 for communicating information, one or more central processors 102 coupled with bus 110 for processing information and instructions.
- Central processor unit 102 may be a microprocessor or any other type of processor.
- the computer 100 also includes data storage features such as a computer usable volatile memory unit 104 (e.g., random access memory, static RAM, dynamic RAM, etc.) coupled with bus 110 for storing information and instructions for central processor(s) 102 , a computer usable non-volatile memory unit 106 (e.g., read only memory, programmable ROM, flash memory, EPROM, EEPROM, etc.) coupled with bus 110 for storing static information and instructions for processor(s) 102 .
- a computer usable volatile memory unit 104 e.g., random access memory, static RAM, dynamic RAM, etc.
- a computer usable non-volatile memory unit 106 e.g., read only memory, programmable ROM, flash memory, EPROM, EEPROM, etc
- System 100 also includes one or more signal generating and receiving devices (I/O circuit) 108 coupled with bus 110 for enabling system 100 to interface with other electronic devices.
- computer system 100 can include an alphanumeric input device 114 including alphanumeric and function keys coupled to the bus 110 for communicating information and command selections to the central processor(s) 102 .
- the computer 100 can include an optional cursor control or cursor directing device 116 coupled to the bus 110 for communicating user input information and command selections to the central processor(s) 102 .
- the system 100 also includes a computer usable mass data storage device 118 such as a magnetic or optical disk and disk drive (e.g., hard drive or floppy diskette) coupled with bus 110 for storing information and instructions.
- a computer usable mass data storage device 118 such as a magnetic or optical disk and disk drive (e.g., hard drive or floppy diskette) coupled with bus 110 for storing information and instructions.
- An optional display device 112 is coupled to bus 110 of system 100 for displaying video and/or graphics. It will be appreciated by one of ordinary skill in the art that computer 100 can be part of a larger system.
- a debugging system 200 effectuates a universal developer, according to an embodiment of the present invention.
- a component matching suite 203 is deployed upon a host computer 202 .
- Host computer 202 is any type of computer system capable of functioning as a platform for the software constituting debugger 206 .
- host computer may be a PC, with a high capacity RAM and disc storage, and powerful processors, deploying a WindowsTM application, upon which debugger 206 may function.
- a component matcher functionality 203 within debugger 206 deploys an array of plug-in modules 205 .
- a parallel cable 208 couples host computer 202 to an in circuit emulator (ICE) 210 .
- ICE 210 in one embodiment contains a field programmable gate array (FPGA) 214 , which may be programmed in response to code promulgated by the debugger 204 .
- the plug-in may be loaded into a microcontroller, a complex programmable logic device (CPLD), or another programmable functionality within the ICE.
- the circuit under test in the present embodiment is a microcontroller or other IC 10 inserted into a pod 218 .
- Pod 218 in the present embodiment, is connected to ICE 210 by a cable 216 , capable of transferring data at a rate of 100 Mbps or greater.
- ICE 210 has a data storage capacity of 128 Kbytes in one embodiment and is of limited computational power, relative to the host computer 202 . In another embodiment, these specific characteristics may change.
- Pod 218 mounts a device for testing and other purposes.
- the device mounted on pod 218 may be a microcontroller 10 or another IC.
- the microcontroller 10 supportable by pod 218 may be of a single, unique design.
- microcontroller 10 may exemplify more than a single device, and pod 218 may be capable of supporting various device pin-outs.
- the devices exemplified by microcontroller 10 may be similar, in particular, how they connect and communicate through pod 218 with the rest of system 200 .
- Each device exemplified herein by microcontroller 10 is identified by a unique identifier.
- the unique identifier is effectively programmed in upon manufacturing the device, and is not generally modifiable by a user.
- the unique identifier may be indexed to a database of information about the device. Such information may include connectivity information such as a number of pins and the connective function of those pins. Information may also be available regarding memory. For example, identified by its unique identifier, it may be determined that microcontroller 10 has, for example, 80 pins, a RAM capacity of 256 bytes and 16 Kbytes of program space. Information regarding the function and behavior of the device may also be available by the unique identifier of the device, for example, that the device has a certain feature set, and/or a certain kind of bug is known to exist or persist in its behavior.
- Pod 218 and the device it mounts has the capability to communicate with ICE 210 and exchange information therewith.
- ICE 210 according to embodiments of the present invention has the capability to recognize pod 218 and any device deployed thereon, exemplified herein by microcontroller 10 . This recognition may be effectuated by the unique identifier of microcontroller 10 .
- ICE 210 Upon interconnecting ICE 210 and pod 218 deploying microcontroller 10 , ICE 210 automatically reads the unique identifier of pod 218 and/or of microcontroller 218 and relays that information back to the debugger 206 and/or component matcher 203 .
- Component matcher 203 analyzes the information relayed to it by ICE 210 and responds by recognizing pod 218 and/or microcontroller 10 , also.
- Component matcher 204 also responds by instructing ICE 210 to behave in a certain way to properly interface with microcontroller 10 via pod 218 , and/or to proceed with its testing thereof.
- debugger 206 , component matcher 204 , and ICE 210 react accordingly to whatever combination of pod and pod-deployed device (exemplified herein by pod 218 and microcontroller 10 , respectively) are coupled to them.
- debugger 206 software and component matcher 203 , and ICE 210 share the same method for reading device and pod identifiers made available through pod 218 .
- debugger 206 software and component matcher 203 , and ICE 210 may not share the identical method for reading device and pod identifiers made available through pod 218 , however, they all share the ability to determine the identity of pods and devices mounted thereon in one way or another.
- this ability confers further flexibility upon system 200 .
- system 200 constitutes three different components, operating with different computational characteristics, including but are not limited to processing power and memory, and even internal structure and function.
- System 200 effectuates debugging operations in a low cost, flexible, distributed architecture.
- system 200 may be constituted by components different from those described herein, which are exemplary and one effective functional architecture, but in no way meant to express or imply exclusive applicability.
- system 200 is effectively adaptable to the limited supervisory capabilities of relatively lower level IC computing devices (e.g., chip), exemplified by microcontroller 10 .
- this adaptability allows changing supervisory capabilities handled by the chip, without necessitating modification of much if any of the higher level capabilities of debugger 206 .
- ICE 210 neither ICE 210 nor its FPGA 214 is limited to functioning with a single type of pod or device thereon.
- ICE 210 is fully capable of supporting any type of pod exemplified herein by pod 218 and/or any type of device mounted on pod 218 , as exemplified herein by microcontroller 10 .
- ICE 210 thus accords great flexibility to system 200 . This flexibility is especially advantageous vis-à-vis conventional debugging systems, wherein each different pod and/or device mounted thereon requires a unique ICE.
- the flexibility accorded by one present embodiment may accrue to functionalities within debugger 206 .
- ICE 210 and pod 218 execute program instructions in lock-step fashion.
- Host computer 202 accesses ICE 210 to determine the internal state of device 10 reflected therein, during debugging operations.
- host computer 202 serves as a platform for debugger software 206 .
- component matcher 204 is a part of debugger software 206 .
- component matcher 204 may be separate from, yet co-functional and interactive with debugger software 206 .
- Component matcher 204 has a directory 242 . Once microcontroller 10 is uniquely identified, its identifier can then be stored in directory. Upon identifying microcontroller 10 as a particular type of device, component matcher 204 consults a library of codes by which, in the present embodiment, FPGA 214 of ICE 210 ( FIG. 2 ) may be programmed accordingly to effectively and properly interact with that particular device. In another embodiment, a flash- or EEPROM-based microcontroller, a CPLD, or another programmable functionality within ICE 210 may be so programmed.
- Component matcher 204 will also select a plug-in from an array 246 of plug-ins based on the version identification code.
- the plug-in selected corresponds to the proper plug-in to allow interaction of the debugger 206 software with the particular device identified.
- Such interaction between the debugger 206 and microcontroller 10 may be further facilitated by selecting a graphical user interface (GUI) from an array 248 of GUIs available.
- GUI graphical user interface
- the proper GUI 248 is the one that will facilitate the best interface between a user of debugger 206 with microcontroller 10 .
- one embodiment allows component matcher 204 to access a database 288 of codes by which FPGA 214 of ICE 210 ( FIG. 2 ) may be programmed accordingly to effectively and properly interact with that particular device.
- database 288 may be remote from computer 202 .
- Access of component matcher 202 with database 288 is achieved through communicative coupling facilitated by communicative interconnections 269 , and via network 999 , which may be the Internet.
- the present embodiment has the advantage of allowing updates to library 244 ( FIG. 3 ) and/or downloading of ICE FPGA codes that are not in library 244 . Alternatively, it may dispense with the requirement of deploying a library within component matcher 204 , debugger 206 , or host computer 202 at all.
- a user connects pod 218 , mounting microcontroller 10 , via ICE 210 to host computer 202 to begin a debugging session.
- Microcontroller 10 and pod 218 have a certain set of specific features. Given that particular pod 218 , the FPGA 214 in ICE 210 will receive a program that exactly mirrors the capabilities of the pod 218 , such that it can emulate its behavior. Further, the FPGA 214 will be programmed with debugging features such that ICE 210 also matches microcontroller 10 . This information downloaded to the FPGA 214 is based on the identification code of the microcontroller 10 .
- FPGA 214 is re-programmed every time the debugging software 206 is run with ICE 218 , to program the ICE 210 to do something, e.g., debugger 206 downloads into FPGA 214 a bitstream. This download is based on the microcontroller's version identification. This bitstream carries a logic set containing everything FPGA 214 needs to configure its logic to perform useful functions with pod 218 and microcontroller 10 .
- one function may be a certain type of RAM paging wherein four RAM pages are made sequentially.
- ICE 210 may be re-programmed somewhat differently.
- a flash-based microcontroller suffices to validate the existing program.
- reprogramming occurs only as needed.
- the programming downloaded to FPGA 214 in ICE 210 in the present embodiment accomplishes at least two major functions.
- the debug features support the four RAM sequential pages above. They may effectuate, for instance, a break upon an exemplary stack going into the third page to allow an opportunity to examine the internal state of the microcontroller 10 at that particular point. Some of these debug features may be specific to particular microcontrollers or other IC's, which microcontroller 10 exemplifies herein.
- ICE 210 is to have some particular debugging feature for a particular microcontroller 10
- the software of debugger 206 needs to support it, as by providing a sufficient GUI (e.g., GUI 248 ; FIG. 3 ).
- the host computer 202 downloads the required data to allow the ICE 210 to properly co-operate with device 10 .
- Plug-in modules 205 match the needs of particular devices 10 and the host computer 202 . It is appreciated that software plug-in modules 205 may be distributed in more than one section of debugger 206 . However, they may also be viewed functionally as a single array.
- debugger 206 begins downloading an initial program, e.g., the bit stream logic set, for some particular device attached to the pod 218 , exemplified herein by microcontroller 10 .
- This initial program need only have sufficient capability to communicate with pods, exemplified by pod 218 herein.
- ICE 210 need only determine whether or not a pod 218 is connected, and establish communications with it if it is.
- simply determining that a pod 218 is connected will initiate communicative attempts, whether or not the ICE 210 actually has the capability to communicate with the particular pod connected or not. In this way, different communicative techniques will be attempted until communications are established between pod 218 and ICE 210 . In either embodiment, additional data transfer may then begin between all three components of system 200 .
- a flowchart describes a process 500 of communicating and transferring data between the three components of a debugging system (e.g., debugging system 200 ; FIG. 2 ), according to one embodiment of the present invention.
- Process 500 begins with step 501 , wherein a host computer (e.g., host computer 202 ; FIG. 2 ) connects to an ICE and initially programs the FPGA therein (e.g., ICE 210 , FPGA 214 ; FIG. 2 ).
- a host computer e.g., host computer 202 ; FIG. 2
- the FPGA therein e.g., ICE 210 , FPGA 214 ; FIG. 2 .
- step 502 the ICE ascertains that a pod (e.g., pod 218 ; FIG. 2 ) is connected, and establishes communications with it.
- the ICE reads the pod's unique identifier information.
- the ICE communicates the pod's unique identifier to the host computer.
- the host computer's component matching program indexes the pod's unique identifier to a library of ICE FPGA codes corresponding to various pods (e.g., library 244 ; FIG. 3 ). Further, the component matching program selects a plug-in module (e.g., plug-in module 205 ; FIG. 2 ) from an array of available plug-in modules (e.g., plug-in module array 246 ; FIG. 3 ). The plug-in module selected exactly matches the pod connected.
- a plug-in module e.g., plug-in module 205 ; FIG. 2
- an array of available plug-in modules e.g., plug-in module array 246 ; FIG. 3
- the host computer's component matching program re-programs the ICE's FPGA with a logic set (e.g., a bitstream) that matches the pod.
- a logic set e.g., a bitstream
- step 507 the host computer component matching program activates its software plug-in that matches the microcontroller or other IC deployed upon the pod.
- step 508 the debugging session may proceed with the debugging session, ending process 500 .
- the ICE FPGA is re-programmed (step 501 ) with a basic program giving the ICE just enough functionality to establish ICE-pod communications and read the pod's unique identifier.
- all pods respond to the same “Read” sequence, such that they can be read in the same way.
- a single generic FPGA bitstream suffices to interrogate any pods and determine their unique identifiers. From that point forward, the ICE and the pod may not match further. In fact, they may be incompatible, in so far as the ICE is presently programmed. However, the core function of establishing communication and reading the unique identifier is invariant.
- the ICE can read the pod's unique identifier and transmit it back to the host computer for further component matching functions. These may be effectuated by the host computer blanket-reprogramming the ICE's FPGA to make that ICE compatible with the pod and its microcontroller.
- An alternative embodiment supports situations wherein a pod may no longer be compatible with the initial ‘Read’ protocol.
- One conceivable such situation is the introduction of a new pod product of another kind, perhaps from a different manufacturer.
- the ICE upon attempting to open ICE-pod communications (step 402 ) and determining that the pod was incapable of being interrogated, the ICE informs the host computer.
- the host computer looks for other bitstreams to attempt, for instance, accessing a database and/or library, and downloads a bitstream its programs ascertains may be more compatible with the pod.
- this increases flexibility and applicability.
- an embodiment of the present invention effectuates a debugging system.
- the present embodiment allows communications between the device and the rest of the debugging system by programming the ICE with a first logic set.
- the first logic set enables the ICE to establish communications with the device and determining a unique identifier thereof.
- the ICE communicates the device's unique identifier back to the host computer.
- the host computer matches the unique identifier to a second logic set and a plug-in module, in one embodiment by referencing a database of corresponding device identifiers and programs and plug-in modules.
- the host computer then programs the ICE with the second logic set and activates the plug-in module.
- the second logic set allow the ICE and the device to execute program instructions downloaded with the second logic set in lock-step fashion.
- the plug-in module allows the host computer to interact in the debugging process as necessary. Any ICE may be programmed to communicate with any device; no unique additional hardware is needed for any particular device to be programmed and tested. Great flexibility is thus achieved. Further, this is achieved without any user intervention requirement, and in a fashion that is transparent to users of the system.
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