US6847101B2 - Microelectronic package having a compliant layer with bumped protrusions - Google Patents

Microelectronic package having a compliant layer with bumped protrusions Download PDF

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Publication number
US6847101B2
US6847101B2 US10/107,094 US10709402A US6847101B2 US 6847101 B2 US6847101 B2 US 6847101B2 US 10709402 A US10709402 A US 10709402A US 6847101 B2 US6847101 B2 US 6847101B2
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Prior art keywords
compliant
assembly
contacts
layer
microelectronic element
Prior art date
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US10/107,094
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US20020100961A1 (en
Inventor
Joseph Fjelstad
Konstantine Karavakis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
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Tessera LLC
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=27358284&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US6847101(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from US08/739,303 external-priority patent/US6211572B1/en
Priority to US10/107,094 priority Critical patent/US6847101B2/en
Application filed by Tessera LLC filed Critical Tessera LLC
Publication of US20020100961A1 publication Critical patent/US20020100961A1/en
Priority to US10/219,902 priority patent/US6847107B2/en
Priority to US10/873,883 priority patent/US7112879B2/en
Publication of US6847101B2 publication Critical patent/US6847101B2/en
Application granted granted Critical
Priority to US11/474,199 priority patent/US7872344B2/en
Priority to US11/487,263 priority patent/US7408260B2/en
Priority to US12/974,744 priority patent/US8338925B2/en
Anticipated expiration legal-status Critical
Assigned to ROYAL BANK OF CANADA, AS COLLATERAL AGENT reassignment ROYAL BANK OF CANADA, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DIGITALOPTICS CORPORATION, DigitalOptics Corporation MEMS, DTS, INC., DTS, LLC, IBIQUITY DIGITAL CORPORATION, INVENSAS CORPORATION, PHORUS, INC., TESSERA ADVANCED TECHNOLOGIES, INC., TESSERA, INC., ZIPTRONIX, INC.
Assigned to INVENSAS CORPORATION, DTS, INC., TESSERA, INC., INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.), IBIQUITY DIGITAL CORPORATION, FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS), PHORUS, INC., TESSERA ADVANCED TECHNOLOGIES, INC, DTS LLC reassignment INVENSAS CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: ROYAL BANK OF CANADA
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Definitions

  • the present invention relates to semiconductor chip packaging. More particularly, the present invention relates to an improved compliant semiconductor package structure and methods for making the same.
  • the present invention relates to semiconductor chip packaging. More particularly, the present invention relates to an improved compliant semiconductor package structure and methods for making the same.
  • Complex microelectronic devices such as modern semiconductor chips require numerous connections to other electronic components.
  • a complex microprocessor chip may require many hundreds of connections to external devices.
  • wire bonding the chip is positioned on a substrate with a bottom or back surface of the chip abutting the substrate and with the contact-bearing front or top surface of the chip facing upwardly, away from the substrate.
  • Individual gold or aluminum wires are connected between the contacts on the chip and pads on the substrate.
  • tape automated bonding a flexible dielectric tape with a prefabricated array of leads thereon is positioned over the chip and substrate and the individual leads are bonded to the contacts on the chip and to pads on the substrate.
  • the pads on the substrate are arranged outside of the area covered by the chip, so that the wires or leads fan out from the chip to the surrounding pads.
  • the area covered by the subassembly as a whole is considerably larger than the area covered by the chip. This makes the entire assembly substantially larger than it otherwise would be. Because the speed with which a microelectronic assembly can operate is inversely related to its size, this presents a serious drawback.
  • the wire bonding and tape automated bonding approaches are generally most workable with chips having contacts disposed in rows extending along the periphery of the chip. They generally do not lend themselves to use with chips having contacts disposed in a so-called area array, i.e., a grid-like pattern covering all or a substantial portion of the chip front surface.
  • the contact-bearing surface of the chip faces towards the substrate.
  • Each contact on the chip is joined by a solder bond to the corresponding pad on the substrate, as by positioning solder balls on the substrate or chip, juxtaposing the chip with the substrate in the front-face-down orientation and momentarily melting or reflowing the solder.
  • the flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself.
  • flip-chip assemblies suffer from significant problems with thermal stress.
  • the solder bonds between the chip contacts and substrate are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds.
  • interposers flexible, sheet-like structures referred to as “interposers” or “chip carriers”.
  • the preferred chip carriers have a plurality of terminals disposed on a flexible, sheet-like top layer.
  • the interposer is disposed on the front or contact-bearing surface of the chip with the terminals facing upwardly, away from the chip.
  • the terminals are then connected to the contacts of the chip. Most preferably, this connection is made by bonding prefabricated leads on the interposer to the chip contacts, using a tool engaged with the lead.
  • the completed assembly is then connected to a substrate, as by bonding the terminals of the chip carrier to the substrate.
  • the terminals on the chip carrier can move relative to the contacts on the chip without imposing significant stresses on the bonds between the leads and the chip, or on the bonds between the terminals and the substrate.
  • the assembly can compensate for thermal effects.
  • the assembly most preferably includes a compliant layer disposed between the terminals on the chip carrier and the face of the chip itself as, for example, an elastomeric layer incorporated in the chip carrier and disposed between the dielectric layer of the chip carrier and the chip. Such a compliant structure permits displacement of the individual terminals independently towards the chip.
  • Components of this type can be connected to microelectronic elements such as semiconductor chips or wafers by juxtaposing the bottom surface of the support layer with the contact-bearing surface of the chip so as to bring the lower ends of: the leads into engagement with the contacts on the chip, and then subjecting the assembly to elevated temperature and pressure conditions. All of the lower ends of the leads bond to the contacts on the chip substantially simultaneously.
  • the bonded leads connect the terminals of the top sheet with the contacts on the chip.
  • the support layer desirably is either formed from a relatively low-modulus, compliant material, or else is removed and replaced after the lead bonding step with such a compliant material.
  • the terminals desirably are movable with respect to the chip to permit testing and to compensate for thermal effects.
  • the components and methods of the '390 patent provide further advantages, including the ability to make all of the bonds to the chip or other component in a single lamination-like process step.
  • the components and methods of the '390 application are especially advantageous when used with chips or other microelectronic elements having contacts disposed in an area array.
  • the present invention contemplates a method of creating a compliant semiconductor chip package assembly and the semiconductor chip package assembly created therefrom.
  • a first dielectric protective layer is provided on a contact bearing surface of a semiconductor chip.
  • the semiconductor chip has a central region bounded by the chip contacts and a set of apertures.
  • the apertures in the dielectric protective layer are provided such that the chip contacts are exposed.
  • This first dielectric protective layer may actually be the silicon dioxide passivation layer of the semiconductor chip.
  • a compliant layer preferably consisting of silicone, flexibilized epoxy, a thermosetting polymer or polyimide is provided atop the first dielectric protective layer is provided within the central region.
  • the compliant layer is formed such that it has a substantially flat top surface and edges that gradually slope down to the top surface of the first dielectric protective layer.
  • the sloping edges of the compliant layer may be manufactured to have a first transition region near the top surface of the compliant layer and a second transition region near the bottom surface of the compliant layer such that both the first transition region and the second transition region have a radius of curvature.
  • bond ribbons are selectively formed atop both the first dielectric protective layer and the compliant layer such that each bond ribbon electrically connects each chip contact to a respective terminal position on the compliant layer.
  • the bond ribbons may be selectively formed using a variety of techniques, such as by electroplating or by electroless plating followed by selective etching.
  • the terminal positions are the conductive elements that connect the finished assembly to a separate substrate, e.g. a printed circuit board.
  • the method described above may further include the step of providing for a second dielectric protective layer atop the bond ribbons and the compliant layer after the bond ribbon electroplating step is performed.
  • This optional second dielectric protective layer is fabricated with a set of apertures that expose the underlying terminal positions on the compliant layer.
  • the method described above may further include the optional step of providing for an encapsulant layer above the bond ribbons. If this optional step is performed, it is performed after the step of selectively electroplating the bond ribbons. Like the first dielectric layer, the encapsulant layer is fabricated with a set of apertures so that the terminal positions are exposed.
  • the encapsulant layer material consists preferably of either a curable liquid, such as silicone, a flexibilized epoxy or a gel. This optional step may also be performed just prior to the optional step of providing for a second dielectric protective layer.
  • a method of making a compliant microelectronic assembly includes providing a microelectronic element, such as a semiconductor chip, having a first surface and a plurality of contacts disposed on the first surface thereof and forming a compliant layer over the first surface of the microelectronic element.
  • the compliant layer typically has a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces.
  • the edge surfaces of the compliant layer are preferably sloping surfaces that extend in both vertical and horizontal directions. At least some of the sloping edge surfaces preferably have first transition regions near the top surface of the compliant layer and second transition regions near the bottom surface of the compliant layer, the first and second transition regions having respective radii of curvature.
  • a first dielectric protective layer such as a layer including a silicon dioxide passivation layer, may be provided on the first surface of the microelectronic element.
  • the first dielectric protective layer may have a plurality of apertures therein so that the contacts are accessible therethrough.
  • the compliant layer described above can then be provided over the dielectric protective layer.
  • Bond ribbons may then be selectively formed over the compliant layer.
  • the bond ribbons preferably extend over both the top surface of the compliant layer and one or more edge surfaces of the compliant layer.
  • the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.
  • a barrier metal layer may be deposited over the contacts so as to prevent undesired chemical reactions between the contacts and the bond ribbons.
  • the bond ribbons are formed by selectively electroplating the bond ribbons atop the first dielectric protective layer and the compliant layer. After the bond ribbons have been formed, a dielectric cover layer may be formed over the compliant layer and the bond ribbons.
  • the dielectric cover layer may have a plurality of apertures therein so that the terminals are accessible therethrough.
  • an encapsulant layer may be provided atop the exposed surfaces of the bond ribbons.
  • the encapsulant layer is generally a material selected from the group consisting of silicone, flexibilized epoxy, thermoplastic and gel.
  • a second dielectric protective layer or cover layer may be provided over the encapsulant layer.
  • the second dielectric protective layer also preferably has a plurality of apertures therein so that the terminals are accessible therethrough.
  • the compliant layer may include one or more apertures therein so that the contacts are accessible through the apertures.
  • the one or more apertures may include one or more groups of apertures encompassing a plurality of the contacts.
  • the edge surfaces of the compliant layer may include one or more aperture edge surfaces bounding the apertures, with at least some of the bond ribbons being formed over the aperture edge surfaces.
  • the compliant layer may be formed by engaging the microelectronic element with a mold so that one or more projections on the mold contact the first surface of the microelectronic element.
  • a flowable composition may be introduced around the projections and the flowable composition set to provide a compliant layer.
  • the microelectronic layer may then be separated from the mold.
  • the one or more apertures are typically formed in the space occupied by the projections.
  • the contacts on the microelectronic element are disposed in an area array, and the one or more apertures in the compliant layer include a plurality of apertures disposed in an array corresponding to the array of contacts so that each contact is encompassed in a respective aperture.
  • the contacts on the microelectronic element may be disposed in a first region of the first surface, with the compliant layer overlying a second region of the first surface, and one or more edge surfaces including one or more border edge surfaces extending along one or more borders between the first and second regions.
  • the contacts on the microelectronic element are disposed in a central region of the first surface and the compliant layer overlies a peripheral region of the first surface.
  • a method of making a compliant microelectronic package includes providing a supporting element having an upwardly-facing top surface and juxtaposing a microelectronic element including a first surface having a plurality of contacts thereon with the supporting element so that the first surface of the microelectronic element is disposed alongside the top surface of the supporting element.
  • the first surface of the microelectronic element and the top surface of the supporting element may be substantially coplanar after the juxtaposing step.
  • a compliant layer may then be provided over the top surface of the supporting element, the compliant layer having a top surface remote from the top surface of the supporting element, a, bottom surface and an edge surface extending between the top surface and the bottom surface.
  • a portion of the compliant layer extends over the first surface of the microelectronic element, with one or more edge surfaces of the compliant layer overlying the first surface of the microelectronic element.
  • Bond ribbons may then be selectively formed atop the compliant layer, the bond ribbons electrically interconnecting the contacts of the microelectronic element with conductive terminals overlying the top surface of the compliant layer.
  • the supporting structure described above may have a central aperture therein so that the microelectronic element may be placed in the central aperture after being juxtaposed with the supporting element. After the juxtaposing step, the first surface of the microelectronic element and the top surface of the supporting structure are preferably substantially coplanar.
  • the compliant chip assembly may include a ground plane electrically interconnected with at least one of the bond ribbons.
  • the ground plane may include a plurality of apertures therein so that the terminals are accessible through the apertures.
  • the methods described above can be applied simultaneously to a multiplicity of undiced semiconductor chips on a wafer to form a corresponding multiplicity of compliant semiconductor chip packages. After the bond ribbons have been formed on the packages, individual packages may be severed or diced from the wafer to provide separate and distinct chip packages. The methods may also be applied to a multiplicity of adjacent semiconductor chips arranged in an array to form a corresponding multiplicity of compliant semiconductor chip packages, whereby the packages are diced after the bond ribbons have been formed.
  • a further aspect of the present invention includes the structure of a unique compliant semiconductor chip package having fan-in type leads.
  • the compliant semiconductor chip package is comprised of (1) a semiconductor chip having a plurality of peripheral bonding pads on a face surface thereof and a central region bound by the peripheral bonding pads; (2) a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface of the first dielectric layer is joined to the face surface of the semiconductor chip and the peripheral bonding pads are exposed through the apertures; (3) a compliant layer having a top surface and a bottom surface, wherein the bottom surface of the compliant layer is joined to the second surface of the first dielectric layer within the central region of the semiconductor chip package; and (4) a plurality of electrically conductive bond ribbons, each bond ribbon having a first end that electrically couples to a respective peripheral bonding pad of the semiconductor chip and a second end that joins to the top surface of the compliant layer to form a package terminal.
  • the package terminals of the completed package are configured in an array that has an area smaller than the area bound by the peripheral bonding pads on the face of the semiconductor chip.
  • the package has fan-in leads that permit minimization of the overall package size.
  • the compliant layer has sloped peripheral edges so that the overlying bond ribbons are curved rather than kinked.
  • the compliant semiconductor chip package may also have a compliant layer characterized by an array of bumped protrusions.
  • the bumped protrusions support the overlying conductive terminal position ends of the bond ribbons and function as conductive balls that join to a substrate thus forming a ball grid array type interconnection.
  • the compliant layer may have an array of concavities that are useful for placement of solder balls into each concavity. This arrangement is also useful for a ball grid array type interconnect.
  • FIG. 1A is a cross-sectional view of a semiconductor chip assembly at the beginning of a fabrication process.
  • FIG. 1B is a cross-sectional view of the semiconductor chip assembly after a first step of the fabrication process, showing a deposited or laminated dielectric passivation layer.
  • FIG. 1C is a cross-sectional view of the semiconductor chip assembly after a second step of the fabrication process, showing a deposited or laminated compliant layer within the central region of the semiconductor chip contact-bearing surface.
  • FIG. 1D is a cross-sectional view of the semiconductor chip assembly after a third step of the fabrication process, showing a conductive seed layer that has been sputtered over the assembly.
  • FIG. 1E is a cross-sectional view of the semiconductor chip assembly after a fourth step of the fabrication process, illustrating how after a photolithographic step conductive bond ribbons can be formed over the assembly.
  • FIG. 1F is a cross-sectional view of the semiconductor chip assembly after a fifth step of the fabrication process, showing how the assembly is coated with a second dielectric protective layer.
  • FIG. 2 is a perspective view of the semiconductor chip assembly after the bond ribbons have been formed over the compliant layer but before the second dielectric protective layer is coated.
  • FIG. 3 is a plan view of a wafer having a multiplicity of semiconductor chips, illustrating how said multiplicity of semiconductor chips can be simultaneously packaged using the semiconductor chip assembly process depicted in FIGS. 1A-1F .
  • FIG. 4 is a cross-sectional view of an alternate embodiment of the present invention, illustrating the use of a low modulus encapsulant material to provide further support and stress relief to the bond ribbons.
  • FIG. 5A is a cross-sectional view of an alternate embodiment of the present invention, illustrating the formation of bumped protrusions in the compliant layer that raise the overlying terminals such that the terminals form an array over the top surface of the compliant layer.
  • FIG. 5B is a perspective view of the embodiment shown in FIG. 5 A.
  • FIG. 6A is a cross-sectional view of an alternate embodiment of the present invention, illustrating the formation of concave areas in the compliant layer such that the overlying terminals have cup-like depressions useful for accurate placement of solder balls.
  • FIG. 6B is a perspective view of the embodiment shown in FIG. 6 A.
  • FIG. 7A is a cross-sectional view of a first step of a semiconductor chip assembly process according to another embodiment of the present invention.
  • FIG. 7B is a cross-sectional view of the assembly shown in FIG. 7A , showing a mold for forming a compliant layer on top of the assembly.
  • FIG. 7C is a cross-sectional view of the assembly shown in FIG. 7B after conductive bond ribbons have been formed atop the compliant layer.
  • FIG. 7D shows the assembly of FIG. 7C after the top of the assembly has been coated with an additional dielectric protective layer.
  • FIG. 8A is a perspective view of the semiconductor chip assembly shown in FIG. 7C , before the additional dielectric protective layer has been provided over the bond ribbons.
  • FIG. 8B is a close-up, fragmentary, cross-sectional view of the assembly shown in FIG. 7 D.
  • FIG. 9 is a cross-sectional view of another embodiment of the present invention, which includes a semiconductor chip having a plurality of contacts in a central region thereof.
  • FIG. 10 is a perspective view of the assembly shown in FIG. 9 .
  • FIG. 11 is a top view of a semiconductor chip having a plurality of non-uniform, staggered chip contacts in a peripheral region of a semiconductor chip, in accordance with another embodiment of the present invention.
  • FIG. 12 is a fragmentary top view of the chip shown in FIG. 11 after a compliant layer and bond ribbons have been formed atop the chip.
  • FIG. 13 is a cross-sectional view of a compliant chip assembly having a supporting element with a central opening and a semiconductor chip provided in the central opening of the supporting element in accordance with yet another embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of a compliant chip assembly including a flexible dielectric sheet in accordance with still another embodiment of the present invention.
  • FIG. 15 is a cross-sectional view of a compliant chip assembly including a ground plane in accordance with a further embodiment of the present invention.
  • FIG. 16 is a fragmentary top view of the compliant chip assembly shown in FIG. 15 .
  • FIG. 17 is a cross-sectional view of a compliant chip assembly including a ground plane in accordance with still further embodiments of the present invention.
  • FIGS. 1A-F illustrate a side view of the process of creating the compliant chip package of the present invention on the face surface of a single die, on the face surfaces of multiple die arranged in a coplanar array or on the face surface of an undiced silicon wafer which may be subsequently diced into individual packaged chips or multi-chip modules.
  • FIG. 1A shows a single semiconductor chip 100 with a contact bearing face surface 120 .
  • the contacts 110 on the face surface 120 are typically aligned in a peripheral region 112 and further define a central region 115 therein.
  • a dielectric passivation layer is deposited or adhered onto the face surface 120 of the chip 100 .
  • the passivation layer may simply be the SiO 2 passivation layer (not shown) commonly found on the contact bearing surface of semiconductor chips, or a separate dielectric passivation layer 130 may be used, such as an epoxy resin, a polyimide resin, photo-imagable dielectric, etc.
  • the passivation layer 130 may be spun onto and built up to a planar sheet-like form on the face surface 120 or a dielectric sheet may be laminated to the face surface 120 using any of a number of electronic grade adhesives commonly known and used by those skilled in the art.
  • the passivation layer 130 covers the face surface 120 of the chip 100 while leaving the chip contacts 110 exposed so that a bond ribbon may be plated thereon in a later step, as described below. Typically, this will be done by depositing or adhering the passivation layer 130 in a continuous sheet on the face surface 120 of the chip 100 .
  • a registering system such as an automatic vision system, is used to locate the contacts 110 .
  • the passivation layer 130 may be exposed and developed without exposing the area above the contacts 110 , that unexposed area may then be removed.
  • Another removal process that can be used is to use a pulse of directed energy, such as an excimer laser, to selectively remove the passivation layer 130 above the contacts 110 .
  • a continuous dielectric sheet already having set contact holes may be registered and laminated to the chip 100 .
  • a compliant layer 140 is deposited or laminated onto the exposed surface of the passivation layer 130 .
  • the compliant layer 140 may be stenciled, screened or transfer molded onto the passivation layer 130 using a curable liquid which, when cured, adheres to the passivation layer 130 .
  • the compliant layer 140 may be adhered to the exposed surface of the passivation layer 130 in the form of cured compliant pads using the aforementioned electronic grade adhesives.
  • the compliant layer 140 has a substantially flat top surface 147 , which further typically has a gradual, sloping transition 145 between the face surface 120 of the chip 100 and the top surface 147 .
  • This transition 145 may follow a line of curvature from the passivation layer 130 to a substantially flat top surface 147 or may simply be canted at an angle such that the transition 145 is not too vertically oriented in relation to the passivation layer 130 and the top surface 147 .
  • the compliant layer 140 itself may be formed from a wide variety of materials; however, preferably, a low modulus of elasticity material is used as the compliant layer 140 .
  • Compliant interposers typically are fabricated from polymeric and other materials such as silicones, flexibilized epoxy, polyimides and other thermosetting polymers, fluoropolymers and thermoplastic polymers. Also, the interposer may be a composite incorporating plural materials. The interposer may consist of, or incorporate, a foam or mesh layer.
  • the flexibility of the interposer depends on the thickness and configuration of the interposer, as well as on the properties of the materials used therein.
  • a flexible interposer capable of buckling or wrinkling to accommodate relative movement, can be fabricated from high elastic modulus materials, normally considered as “rigid” provided that these materials are present in thin layers.
  • Relatively soft materials and foams can be used in greater thicknesses and still provide a highly flexible interposer.
  • such soft materials and foams provide a highly compliant interposer, i.e., an interposer that is readily compressible in the directions perpendicular its surfaces and which therefore permits movement of the terminals in these directions.
  • a plating seed layer 150 is then deposited atop the aforementioned assembly, as shown in FIG. 1D , typically using a sputtering operation.
  • Typical plating seed layer materials include palladium (for electroless plating), titanium, tungsten, nickel, and chromium; however, primarily copper seed layers are used.
  • FIG. 1E shows the next step in which photoresist 160 is applied to the exposed top surfaces of the assembly and then exposed and developed such that bond ribbons 170 may be plated within defined areas to form conductive paths electrically connecting the chip contacts 110 near a first end region of the ribbons 170 to terminals 175 comprising the second end region of the ribbons 170 . This is perhaps more easily seen in the perspective view shown in FIG. 2 .
  • the ribbons 170 are plated directly onto the contacts 110 and extend in a “fan-in” arrangement from the peripheral region 112 to the central region 115 of the face surface 120 of the chip 100 atop the compliant layer 140 .
  • Possible bond ribbon materials include copper, gold, nickel, and alloys, combinations and composites thereof, among others. Since the bond ribbons 170 are plated directly onto the chip contact/compliant layer themselves, there is no need to develop a process for bonding the ribbons 170 to the contacts, as is necessary with most other approaches such as TAB, beam lead or wirebonding. This provides a significant cost savings because specialized thermocompression or ultrasonic bonders and their bonding tools need not be purchased or maintained.
  • the material selected for the bond ribbon 170 be compatible with the chip contact 110 material, which is typically aluminum. Otherwise, a phenomenon called Kirkendahl Voiding (voids created at the boundary of two metals having different interdiffusion coefficients) may cause voiding along the boundary of the two metals (ribbon/contact) leading to intermetallic degradation and embrittlement of the bond ribbon 170 itself making the lead/bond susceptible to failure during thermal cycling. Alternately, one or more barrier metals may be plated atop the chip contacts 110 prior to the bond ribbon plating step to thereby ensure the compatibility of materials.
  • Kirkendahl Voiding voids created at the boundary of two metals having different interdiffusion coefficients
  • one or more barrier metals may be plated atop the chip contacts 110 prior to the bond ribbon plating step to thereby ensure the compatibility of materials.
  • a dielectric layer 180 is deposited or laminated over the top of the assembly so that only the terminals 175 are exposed.
  • the dielectric layer may be comprised of a screened, exposed and developed or laminated sheet photo resist material or may be comprised of paralyne, epoxy resin, polyimide resin, fluoropolymer, etc. which is deposited or laminated on to the assembly, as described above in relation to the passivation layer 130 .
  • the terminals 175 may then be electrically connected to a circuitized substrate, such as a printed wiring board.
  • solder ball or a solid-core solder ball will be used to create this electrical connection.
  • the dielectric layer 180 is thus used as a solder mask to ensure that the solder does not electrically short between adjacent bond ribbons 170 .
  • Oxide layers and other surface contaminates typically build up on the surface of many types of metal (copper, nickel, etc.).
  • the terminals 175 are typically flash plated with a thin layer of gold (approximately 0.25 to 0.5 microns) to inhibit the formation of these oxide layers.
  • the gold layer is kept very thin so that it does not appreciably affect the aforementioned solder joint by dissolving into the solder to an amount which would embrittle the resulting solder joint between the terminal and a circuitized substrate.
  • the configuration of the above described chip package allows the package to mechanically decouple the chip 100 from an attached circuitized substrate (not shown). Typically, solder connections between the chip and the circuitized substrate are woefully inadequate to compensate for the thermal mismatch problem during temperature cycling of the chip.
  • the combination of the compliant layer 140 and the flexible bond ribbons plated thereon allow the package to compensate for much of the TCE mismatch problem by giving limited movement of the terminals in the X, Y and Z directions with respect to the chip contacts 110 thereby minimizing the stress placed on the solder connections themselves, without imposing substantial forces on the bond between the ribbons 170 and the chip contacts 110 .
  • the compliant layer 140 is compressible, it also has the effect of compensating for any terminals 175 which are not perfectly planar with respect to its adjacent terminals when the terminals 175 are abutted against and coupled to the circuitized substrate.
  • the top surface 147 of the compliant layer 140 should be made as flat and planar as possible so that the terminals 175 all lie in or near the same plane in order to minimize the amount of pressure needed to be placed on the bottom surface 125 of the chip 100 to ensure that all of the terminals/solder balls are electrically connected to a circuitized substrate.
  • the chip package described above in relation to FIGS. 1 and 2 may also be provided in the form of a multiplicity of packages on a wafer incorporating a plurality of individual, undiced chips, all of the same design or of differing designs.
  • an array of individual passivation layers 230 may be deposited or laminated onto the face surface 220 of the wafer 200 leaving the chip contacts 210 of the various individual chips exposed, as described above. This arrangement is shown to better define the individual chips within the wafer.
  • a single passivation layer 230 is deposited or laminated onto the face surface 220 leaving the contacts 210 exposed.
  • Individual compliant layers 240 are deposited or laminated onto the central regions of each of the individual chips within the wafer 200 .
  • the steps found in FIGS. 1A-F are then performed, as described above, to create a plurality of connected individually packaged chips on the face surface 220 of the wafer 200 .
  • Each packaged chip having bond ribbons 270 which are connected at one end to contacts 210 and extending in to a central region of the respective chip in a fan-in fashion atop a respective compliant layer 240 and ending with a terminal 275 on the top surface 247 of the compliant layer 240 .
  • the individual chips may be separated from the wafer 200 and from one another, as by cutting the wafer 200 using conventional wafer severing or “dicing” equipment commonly utilized to sever wafers into individual chips. This procedure yields a plurality of packaged chip subassemblies, each of which may be secured to an individual circuitized substrate. Alternately, the chips may be separated from the wafer 200 in multi-chip arrangements of multiples of the same or different operational chips.
  • the wafer level embodiment shown in FIG. 3 could be simulated using a panel of individual chips spaced apart from one another in a processing boat. The face surfaces of the individual chips would be coplanar with respect to one another to simulate the face surface 220 of the wafer 200 .
  • the chips above described steps would be performed and the chips would be separated if desired.
  • a low modulus encapsulant material 290 may be deposited around the exposed surfaces of the bond ribbons 170 ′ leads prior to the step shown in FIG. 1F of depositing or laminating the assembly with the dielectric layer 180 ′.
  • the encapsulant material 290 may have properties similar to those of rubber, gum or gel.
  • Typical encapsulation materials include curable liquid or cured pads comprised of silicone, flexibilized epoxy, gels, thermoplastics, etc.
  • a fixture may be made such that the liquid flows around the bond ribbons 170 ′ but does not flow on top of the terminals 175 ′ to ensure that solder balls may be subsequently electrically connected to the terminals 175 ′, as described above.
  • a machine such as a Camalot 1818 manufactured by Camalot Systems, Inc. of Havermill, Mass. may be used to flow the liquid encapsulant into the desired areas. After the liquid is deposited, it may be cured by any number of ways depending on the encapsulant material 290 used, e.g. heat, infrared energy, etc.
  • a flash plated layer of gold may be plated atop the exposed surface of the terminal.
  • the entire exposed surface of the bond ribbon could be plated with a thin layer of gold to increase the overall conductivity of such super plastic leads.
  • a dielectric layer is next deposited or laminated as shown in FIG. 1 F.
  • FIG. 5A shows a side view and FIG. 5B a perspective view of another embodiment, according to the present invention.
  • the compliant layer 140 ′ has protrusions 300 on its top surface 147 ′. These protrusions 300 may be integral with the compliant layer 140 ′ or may be deposited or laminated onto the top surface 147 ′ subsequent to the formation of the compliant layer 140 ′.
  • the protrusions 300 may be formed of compliant, elastomeric material, such as the material comprising the compliant layer 140 ′, or may be comprised of a semi-rigid or rigid material.
  • the bond ribbon terminals 175 ′ are plated on top of the protrusions 300 thereby providing raised surfaces that may be connected to a circuitized substrate. This technique allows for connection to such a substrate using less solder and without the need to accurately position solid-core solder balls.
  • FIG. 6A shows a side view and FIG. 6B a perspective view of another embodiment, according to the present invention.
  • concave areas 310 are created in the compliant layer 140 ′′. These concave areas 310 may be create in the formation of the compliant layer 140 ′′ or may be created subsequent to the formation of the compliant layer 140 ′′.
  • the bond ribbon terminals 175 ′′ are plated within the concave areas 310 creating conductive “cup-like” areas on the top surface 147 ′′ of the compliant layer 140 ′′. Solder or solid-core solder balls are then placed within these areas 310 and reflowed to attach the package to a circuitized substrate, as described earlier. This technique allows for the accurate placement of solder or solid-core solder balls by allowing them to be deposited and retained within the cup-like areas.
  • FIGS. 7A-7D illustrate a side view of a method of making a compliant microelectronic package including a semiconductor chip having an area array of contacts on a first surface thereof.
  • the package is preferably assembled by using the method steps described above.
  • FIG. 7A shows a single semiconductor chip 400 having a first surface 420 including a plurality of contacts 410 provided in an area array over the first surface 400 .
  • a dielectric passivation layer 430 is deposited over the first surface 420 of the chip 400 and preferably covers the first surface 420 of the chip 400 while leaving the chip contacts 410 exposed so that a bond ribbon (not shown) may be plated thereon, as will be described in more detail below.
  • the chip 400 is placed in a frame 491 and the mold is closed on top of the chip 400 so that the projections 489 completely cover the contacts 410 .
  • a curable liquid 440 is introduced into the mold and fills the open spaces 493 between the projections 489 .
  • the curable liquid is then cured while the mold remains in the closed position so as to form the compliant layer 440 having a substantially flat top surface 447 including a plurality of openings 495 aligned with the contacts 410 .
  • the height of projections 489 is exaggerated in FIG. 7B for clarity of illustration.
  • projections 489 typically are about 75-200 microns high, and hence compliant layer 440 typically is about 74-200 microns thick.
  • each opening 495 has a gradual sloping edge 497 or transition between the first surface 420 of the chip 400 and the top surface 447 of the compliant layer 440 .
  • This sloping edge 497 will preferably follow a line of curvature from the passivation layer 430 to the substantially flat top surface 447 , or may simply be canted at an angle such that the sloping edge 497 is not too vertically oriented in relation to the passivation layer 430 and the top surface 447 of the compliant layer.
  • sloping edge 497 typically is disposed at an angle of about 20-70° to the plane of the chip front surface, and more typically about 40-60°.
  • the sloping surface typically is curved to define a radius at the juncture of sloping surface 497 and top surface 447 .
  • a further radius or fillet can be provided at the junction of the sloping surface and the front surface of the chip.
  • bond ribbons 470 are selectively formed within defined areas to create conductive paths electrically connecting the chip contacts 410 near a first end of the bond ribbons 470 to conductive terminals 475 at a second end of the bond ribbons.
  • the bond ribbons 470 may be formed using selective electroplating or other selective deposition techniques.
  • the selection forming step used to make bond ribbons 470 may include one or more non-selective deposition techniques such as electroless plating or sputtering of a conductive layer over the assembly, with or without an additional non-selective electroplating step, followed by selectively etching of the conductive layer to provide electrically isolated bond ribbons.
  • FIG. 8A shows a perspective view of the bond ribbons after they have been selectively formed over the compliant layer.
  • one or more barrier metal layers 415 may be plated atop the chip contacts 410 prior to forming the bond ribbons 470 so as to insure the compatibility of materials.
  • FIG. 8B shows a close-up, fragmentary, cross-sectional view of FIG. 7 D.
  • the assembly includes the compliant layer 440 having a plurality of apertures 495 therein so the contacts 410 are accessible through the apertures 495 .
  • Each aperture 495 in the compliant layer 440 preferably includes at least one sloping edge side wall 497 that provides a gradual sloping transition between the first surface 420 of the chip 400 and the top surface 447 of the compliant layer 440 .
  • the transition preferably follows a line of curvature from the passivation layer 430 to the top surface 447 or may simply be canted at an angle so that the transition from the first surface 420 of the chip 400 to the top surface 447 of the compliant layer 440 is not too vertically oriented in relation to the passivation layer 430 .
  • the top surface 447 of the passivation layer is preferably substantially flat, however, in certain embodiments the top surface 447 may be slightly rounded.
  • the low points in the compliant layer may next be filled with compliant material to encase the leads and/or cover sheets of material.
  • a compliant chip package in accordance with another preferred embodiment of the present invention includes a single semiconductor chip 500 having a first surface 520 with a first or central region 515 and a second or peripheral region 517 surrounding the central region 515 .
  • the chip 500 includes a plurality of contacts 510 disposed in the central region 515 thereof.
  • a passivation layer 530 is preferably deposited over the first surface 520 of the chip 500 .
  • the passivation layer 530 includes apertures aligned with the contacts 510 so that the chip contacts 510 are accessible through the passivation layer 530 .
  • a compliant layer 540 is then formed over the passivation layer, the compliant layer having openings 595 in alignment with the chip contacts 510 so that the contacts are accessible through the compliant layer openings 595 .
  • the steps described above are then performed to create a plurality of bond ribbons 570 which are connected at one end to the chip contacts 510 and at a second end to conductive terminals 575 accessible at the substantially flat surface 547 of the compliant layer 540 .
  • the final assembly provides a compliant chip package having a plurality of contacts 510 in the central region 515 thereof and bond ribbons 570 extending outwardly from the contacts 510 to conductive terminals 575 overlying the peripheral region 517 of the chip 500 .
  • the centrally located low point in the compliant layer can be filled in with compliant material to encapsulate the leads.
  • FIG. 10 shows a perspective view of the package illustrated in FIG. 9 .
  • the plurality of contacts 510 is located in the central region 515 of the chip 500 .
  • Compliant layer 540 defines two sloping edges 572 at the border of the first or central region of the chip surface and the second or peripheral region.
  • Bond ribbons 570 have first ends electrically connected to the contacts 510 and second ends extending to conductive terminals 575 provided at the top surface 547 of the compliant layer 540 .
  • the specific embodiment shown in FIG. 10 includes a compliant layer 540 having a first section on the left side of the chip 500 and a second section on the right side of the chip 500 , however, other preferred embodiments may include compliant layers having more than two distinct portions.
  • FIG. 12 shows four different contacts, designated 610 A- 610 D, located in the peripheral region 612 of the chip 600 .
  • the contacts are staggered with respect to one another so that contacts 610 B and 610 D are closer to the edge 617 of the chip than contacts 610 A and 610 C.
  • the contacts 610 are electrically connected to terminals 675 by bond ribbons 670 .
  • the actual length of bond ribbons 670 may vary based upon the position of the contact 610 and the desired position of the terminal 675 .
  • bond ribbon 670 C is longer than bond ribbon 670 A.
  • the terminal 675 C connected to bond ribbon 670 C may be positioned at a more central location than terminal 675 A.
  • the ability to modify the length of the bond ribbons 670 allows the terminals 675 to be positioned at an infinite number of different locations over the top surface 647 of the compliant layer 640 so that the chip package can be reliably interconnected with an external circuit element, regardless of the location of contact pads on the external circuit element.
  • bond ribbons 770 are formed using the techniques described above, and a dielectric layer 780 is formed over the bond ribbons 770 so that only conductive terminals 775 are accessible at the top of the assembly.
  • the supporting element 792 may include a heat sink and the compliant layer may be formed on the top surface of flanges extending laterally from central opening in the heat sink.
  • the compliant chip package includes a flexible dielectric sheet 865 , such as a polyimide sheet, secured over the top of the compliant layer 840 .
  • the package includes a semiconductor chip 800 having a first surface 820 with contacts 810 .
  • a dielectric passivation layer 830 including openings in substantial alignment with the contacts 810 , is then formed over the first surface 820 of the chip 800 .
  • the flexible dielectric sheet 865 is provided over the top surface 847 of the compliant layer 840 .
  • the flexible dielectric sheet 865 generally improves the structural integrity of the package and protects the compliant layer 840 from external contaminants.
  • Bond ribbons 870 are then formed atop the passivation layer 830 , the compliant layer 840 and the flexible dielectric sheet 865 .
  • the bonds ribbons 870 have first ends which are connected to chip contacts 810 and second ends which provide conductive terminals 875 over the flexible dielectric sheet 865 .
  • the dielectric sheet 865 is provided as a separate sheet which is laminated or secured over the top surface 847 of the compliant layer 840 .
  • the conductive terminals 875 may be pre-formed on the dielectric sheet 865 , with the bond ribbon forming step electrically interconnecting the contacts 810 and the pre-formed conductive terminals 875 .
  • the flexible dielectric sheet 865 may be spun onto the top surface 847 of the compliant layer 8340 .
  • the edges of the spun-on dielectric sheet have radii of curvature which substantially match the radii of curvature of the edges of the compliant layer.
  • the matched edges provide a smooth transition from the dielectric sheet 865 to the compliant layer 840 , thereby providing a more uniform surface for forming the bond ribbons 870 .
  • a second dielectric protective layer 880 may then be formed over the bond ribbons 870 to further protect the bond ribbons and electrically isolate the bond ribbons from one another.
  • a compliant chip package in another embodiment, illustrated in FIGS. 15 and 16 , includes a ground plane 981 .
  • a semiconductor chip 900 is provided within a central opening 995 of a supporting element 992 so that a first contact bearing surface 920 of the chip 900 is substantially parallel with a top surface 994 of the supporting element 992 .
  • a first compliant layer 940 having a substantially flat top surface 947 and a bottom surface and sloping edges 997 therebetween is then formed atop the top surface 994 of the supporting element 992 .
  • the compliant layer 940 preferably fills gaps 955 between the peripheral edges of the chip 900 and the support element 992 .
  • the sloping edges 997 preferably provide a smooth transition between the top surface 947 of the compliant layer 940 and the chip 900 .
  • Bond ribbons are then formed over the compliant layer 940 using the techniques described above.
  • the sloping edges 997 of the compliant layer 940 will increase the reliability of the bond ribbons 970 because the bond ribbons will be gently curved rather than kinked.
  • a second compliant layer 941 is formed atop the bond ribbons 970 so as to encapsulate the bond ribbons 970 .
  • a dielectric layer 980 is then formed over the second compliant layer 941 and the bond ribbons 970 so that only conductive terminals 975 are accessible at the top of the assembly.
  • the ground plane 981 is then provided atop the dielectric layer 980 .
  • the ground plane preferably includes a highly conductive material, such as copper, having a plurality of openings therein.
  • the openings are preferably formed using photolithographic and etching techniques.
  • the openings are sized to fit over the terminals 975 and a relatively small portion of the bond ribbon 970 extending away from each terminal 975 .
  • the ground plane 981 is assembled to the dielectric layer by aligning the openings 983 therein with the terminals 975 and abutting the ground plane 981 against the top of the dielectric layer 980 .
  • the package is then subjected to a curing process so as to cure the compliant layers 940 and 941 and the dielectric layer 980 .
  • FIG. 17 shows yet another embodiment of a compliant chip package which is similar to that shown in FIG. 15 , however, the FIG. 17 embodiment lacks the top dielectric cover layer shown in FIG. 15 .
  • a ground plane 1081 similar to that shown in FIG. 16 is provided over the second compliant layer 1041 .
  • the ground plane 1081 may be compressed against the second compliant layer 1041 so that the ground plane 1081 is slightly sunk into the second compliant layer 1041 .
  • the ground plane preferably includes openings 1083 which are in alignment with terminals 1075 so that the terminals 1075 are accessible through the openings 1083 .
  • the package is then subjected to a curing process so as to cure the compliant layers 1040 and 1041 .
  • the ground plane 1081 is preferably electrically connected to at least one of the bond ribbons 1070 .
  • the low modulus encapsulant material shown in FIG. 4 may be used to assemble any of the compliant chip packages shown in FIGS. 7A-14 to provide additional stress relief for the bond ribbons.
  • the assembly shown in FIG. 13 may be modified so as to provide conductive terminals over the central region of the chip, thereby providing a “fan-in/fan-out” compliant chip package.
  • all of the chip package assemblies disclosed above may be assembled on a wafer prior to severing the individual chips from the wafer.

Abstract

A microelectronic assembly includes a microelectronic element having a first surface with a plurality of contacts accessible at the first surface, and a compliant layer over the first surface of the microelectronic element, the compliant layer including a plurality of bumped protrusions and openings adjacent the bumped protrusions for providing access to the contacts, wherein each bumped protrusion includes a top surface and at least one sloping edge. The microelectronic assembly also includes conductive terminals over the top surfaces of the bumped protrusions, and a plurality of conductive bond ribbons having first ends in engagement with the contacts, second ends in engagement with the terminals and intermediate sections extending along the sloping edges for electrically interconnecting the contacts and the terminals.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
The present application is a continuation of U.S. patent application Ser. No. 09/777,782, filed Feb. 6, 2001, which is a continuation of U.S. patent application Ser. No. 09/071,412, filed May 1, 1998,now U.S. Pat. No. 6,284,563 , which is a continuation-in-part of U.S. patent application Ser. No. 08/739,303, filed Oct. 29, 1996, now U.S. Pat. No. 6,211,572, which, in turn, claims benefit of U.S. Provisional Application No. 60/007,128, filed Oct. 31, 1995, the disclosures of which are hereby incorporated by reference herein.
FIELD OF THE INVENTION
The present invention relates to semiconductor chip packaging. More particularly, the present invention relates to an improved compliant semiconductor package structure and methods for making the same.
FIELD OF THE INVENTION
The present invention relates to semiconductor chip packaging. More particularly, the present invention relates to an improved compliant semiconductor package structure and methods for making the same.
BACKGROUND OF THE INVENTION
Complex microelectronic devices such as modern semiconductor chips require numerous connections to other electronic components. For example, a complex microprocessor chip may require many hundreds of connections to external devices.
Semiconductor chips commonly have been connected to electrical traces on mounting substrates by one of three methods: wire bonding, tape automated bonding, and flip-chip bonding. In wire bonding, the chip is positioned on a substrate with a bottom or back surface of the chip abutting the substrate and with the contact-bearing front or top surface of the chip facing upwardly, away from the substrate. Individual gold or aluminum wires are connected between the contacts on the chip and pads on the substrate. In tape automated bonding a flexible dielectric tape with a prefabricated array of leads thereon is positioned over the chip and substrate and the individual leads are bonded to the contacts on the chip and to pads on the substrate. In both wire bonding and conventional tape automated bonding, the pads on the substrate are arranged outside of the area covered by the chip, so that the wires or leads fan out from the chip to the surrounding pads. The area covered by the subassembly as a whole is considerably larger than the area covered by the chip. This makes the entire assembly substantially larger than it otherwise would be. Because the speed with which a microelectronic assembly can operate is inversely related to its size, this presents a serious drawback. Moreover, the wire bonding and tape automated bonding approaches are generally most workable with chips having contacts disposed in rows extending along the periphery of the chip. They generally do not lend themselves to use with chips having contacts disposed in a so-called area array, i.e., a grid-like pattern covering all or a substantial portion of the chip front surface.
In the flip-chip mounting technique, the contact-bearing surface of the chip faces towards the substrate. Each contact on the chip is joined by a solder bond to the corresponding pad on the substrate, as by positioning solder balls on the substrate or chip, juxtaposing the chip with the substrate in the front-face-down orientation and momentarily melting or reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. However, flip-chip assemblies suffer from significant problems with thermal stress. The solder bonds between the chip contacts and substrate are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds. Moreover, it is difficult to test the chip before attaching it to the substrate, and hence difficult to maintain the required outgoing quality level in the finished assembly, particularly where the assembly includes numerous chips.
Numerous attempts have been made to solve the foregoing problem. Useful solutions are disclosed in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266. Preferred embodiments of the structures disclosed in these patents incorporate flexible, sheet-like structures referred to as “interposers” or “chip carriers”. The preferred chip carriers have a plurality of terminals disposed on a flexible, sheet-like top layer. In use, the interposer is disposed on the front or contact-bearing surface of the chip with the terminals facing upwardly, away from the chip. The terminals are then connected to the contacts of the chip. Most preferably, this connection is made by bonding prefabricated leads on the interposer to the chip contacts, using a tool engaged with the lead. The completed assembly is then connected to a substrate, as by bonding the terminals of the chip carrier to the substrate. Because the leads and the dielectric layer of the chip carrier are flexible, the terminals on the chip carrier can move relative to the contacts on the chip without imposing significant stresses on the bonds between the leads and the chip, or on the bonds between the terminals and the substrate. Thus, the assembly can compensate for thermal effects. Moreover, the assembly most preferably includes a compliant layer disposed between the terminals on the chip carrier and the face of the chip itself as, for example, an elastomeric layer incorporated in the chip carrier and disposed between the dielectric layer of the chip carrier and the chip. Such a compliant structure permits displacement of the individual terminals independently towards the chip. This permits effective engagement between the subassembly and a test fixture. Thus, a test fixture incorporating numerous electrical contacts can be engaged with all of the terminals in the subassembly despite minor variations in the height of the terminals. The subassembly can be tested before it is bonded to a substrate so as to provide a tested, known, good part to the substrate assembly operation. This in turn provides very substantial economic and quality advantages.
Commonly owned U.S. Pat. No. 5,455,390 describes a further improvement. Components according to preferred embodiments of the '390 patent use a flexible, dielectric top sheet having top and bottom surfaces. A plurality of terminals is mounted on the top sheet. A support layer is disposed underneath the top sheet, the support layer having a bottom surface remote from the top sheet. A plurality of electrically conductive, elongated leads are connected to the terminals on the top sheet and extend generally side by side downwardly from the terminals through the support layer. Each lead has a lower end at the bottom surface of the support layer. The lower ends of the leads have conductive bonding materials as, for example, eutectic bonding metals. The support layer surrounds and supports the leads.
Components of this type can be connected to microelectronic elements such as semiconductor chips or wafers by juxtaposing the bottom surface of the support layer with the contact-bearing surface of the chip so as to bring the lower ends of: the leads into engagement with the contacts on the chip, and then subjecting the assembly to elevated temperature and pressure conditions. All of the lower ends of the leads bond to the contacts on the chip substantially simultaneously. The bonded leads connect the terminals of the top sheet with the contacts on the chip. The support layer desirably is either formed from a relatively low-modulus, compliant material, or else is removed and replaced after the lead bonding step with such a compliant material. In the finished assembly, the terminals desirably are movable with respect to the chip to permit testing and to compensate for thermal effects. However, the components and methods of the '390 patent provide further advantages, including the ability to make all of the bonds to the chip or other component in a single lamination-like process step. The components and methods of the '390 application are especially advantageous when used with chips or other microelectronic elements having contacts disposed in an area array.
Despite the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.
SUMMARY OF THE INVENTION
The present invention contemplates a method of creating a compliant semiconductor chip package assembly and the semiconductor chip package assembly created therefrom.
In a fabrication process according to one aspect of the invention, a first dielectric protective layer is provided on a contact bearing surface of a semiconductor chip. The semiconductor chip has a central region bounded by the chip contacts and a set of apertures. The apertures in the dielectric protective layer are provided such that the chip contacts are exposed. This first dielectric protective layer may actually be the silicon dioxide passivation layer of the semiconductor chip.
Second, a compliant layer, preferably consisting of silicone, flexibilized epoxy, a thermosetting polymer or polyimide is provided atop the first dielectric protective layer is provided within the central region. The compliant layer is formed such that it has a substantially flat top surface and edges that gradually slope down to the top surface of the first dielectric protective layer. The sloping edges of the compliant layer may be manufactured to have a first transition region near the top surface of the compliant layer and a second transition region near the bottom surface of the compliant layer such that both the first transition region and the second transition region have a radius of curvature.
Finally, bond ribbons are selectively formed atop both the first dielectric protective layer and the compliant layer such that each bond ribbon electrically connects each chip contact to a respective terminal position on the compliant layer. The bond ribbons may be selectively formed using a variety of techniques, such as by electroplating or by electroless plating followed by selective etching. The terminal positions are the conductive elements that connect the finished assembly to a separate substrate, e.g. a printed circuit board.
The method described above may further include the step of providing for a second dielectric protective layer atop the bond ribbons and the compliant layer after the bond ribbon electroplating step is performed. This optional second dielectric protective layer is fabricated with a set of apertures that expose the underlying terminal positions on the compliant layer.
Additionally, the method described above may further include the optional step of providing for an encapsulant layer above the bond ribbons. If this optional step is performed, it is performed after the step of selectively electroplating the bond ribbons. Like the first dielectric layer, the encapsulant layer is fabricated with a set of apertures so that the terminal positions are exposed. The encapsulant layer material consists preferably of either a curable liquid, such as silicone, a flexibilized epoxy or a gel. This optional step may also be performed just prior to the optional step of providing for a second dielectric protective layer.
In another aspect of the invention, a method of making a compliant microelectronic assembly includes providing a microelectronic element, such as a semiconductor chip, having a first surface and a plurality of contacts disposed on the first surface thereof and forming a compliant layer over the first surface of the microelectronic element. The compliant layer typically has a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. The edge surfaces of the compliant layer are preferably sloping surfaces that extend in both vertical and horizontal directions. At least some of the sloping edge surfaces preferably have first transition regions near the top surface of the compliant layer and second transition regions near the bottom surface of the compliant layer, the first and second transition regions having respective radii of curvature.
In certain embodiments, before the compliant layer is formed, a first dielectric protective layer, such as a layer including a silicon dioxide passivation layer, may be provided on the first surface of the microelectronic element. The first dielectric protective layer may have a plurality of apertures therein so that the contacts are accessible therethrough. The compliant layer described above can then be provided over the dielectric protective layer.
Bond ribbons may then be selectively formed over the compliant layer. The bond ribbons preferably extend over both the top surface of the compliant layer and one or more edge surfaces of the compliant layer. The bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer. Before the bond ribbons are formed, a barrier metal layer may be deposited over the contacts so as to prevent undesired chemical reactions between the contacts and the bond ribbons. In one embodiment, the bond ribbons are formed by selectively electroplating the bond ribbons atop the first dielectric protective layer and the compliant layer. After the bond ribbons have been formed, a dielectric cover layer may be formed over the compliant layer and the bond ribbons. The dielectric cover layer may have a plurality of apertures therein so that the terminals are accessible therethrough. In other embodiments, an encapsulant layer may be provided atop the exposed surfaces of the bond ribbons. The encapsulant layer is generally a material selected from the group consisting of silicone, flexibilized epoxy, thermoplastic and gel. Next, a second dielectric protective layer or cover layer may be provided over the encapsulant layer. The second dielectric protective layer also preferably has a plurality of apertures therein so that the terminals are accessible therethrough.
The compliant layer may include one or more apertures therein so that the contacts are accessible through the apertures. The one or more apertures may include one or more groups of apertures encompassing a plurality of the contacts. The edge surfaces of the compliant layer may include one or more aperture edge surfaces bounding the apertures, with at least some of the bond ribbons being formed over the aperture edge surfaces. The compliant layer may be formed by engaging the microelectronic element with a mold so that one or more projections on the mold contact the first surface of the microelectronic element. A flowable composition may be introduced around the projections and the flowable composition set to provide a compliant layer. The microelectronic layer may then be separated from the mold. The one or more apertures are typically formed in the space occupied by the projections.
In certain embodiments, the contacts on the microelectronic element are disposed in an area array, and the one or more apertures in the compliant layer include a plurality of apertures disposed in an array corresponding to the array of contacts so that each contact is encompassed in a respective aperture. In other embodiments, the contacts on the microelectronic element may be disposed in a first region of the first surface, with the compliant layer overlying a second region of the first surface, and one or more edge surfaces including one or more border edge surfaces extending along one or more borders between the first and second regions. In still other embodiments, the contacts on the microelectronic element are disposed in a central region of the first surface and the compliant layer overlies a peripheral region of the first surface.
In another embodiment, a method of making a compliant microelectronic package includes providing a supporting element having an upwardly-facing top surface and juxtaposing a microelectronic element including a first surface having a plurality of contacts thereon with the supporting element so that the first surface of the microelectronic element is disposed alongside the top surface of the supporting element. The first surface of the microelectronic element and the top surface of the supporting element may be substantially coplanar after the juxtaposing step.
A compliant layer may then be provided over the top surface of the supporting element, the compliant layer having a top surface remote from the top surface of the supporting element, a, bottom surface and an edge surface extending between the top surface and the bottom surface. In certain embodiments, a portion of the compliant layer extends over the first surface of the microelectronic element, with one or more edge surfaces of the compliant layer overlying the first surface of the microelectronic element. Bond ribbons may then be selectively formed atop the compliant layer, the bond ribbons electrically interconnecting the contacts of the microelectronic element with conductive terminals overlying the top surface of the compliant layer.
The supporting structure described above may have a central aperture therein so that the microelectronic element may be placed in the central aperture after being juxtaposed with the supporting element. After the juxtaposing step, the first surface of the microelectronic element and the top surface of the supporting structure are preferably substantially coplanar.
In certain embodiments, the compliant chip assembly may include a ground plane electrically interconnected with at least one of the bond ribbons. The ground plane may include a plurality of apertures therein so that the terminals are accessible through the apertures.
The methods described above can be applied simultaneously to a multiplicity of undiced semiconductor chips on a wafer to form a corresponding multiplicity of compliant semiconductor chip packages. After the bond ribbons have been formed on the packages, individual packages may be severed or diced from the wafer to provide separate and distinct chip packages. The methods may also be applied to a multiplicity of adjacent semiconductor chips arranged in an array to form a corresponding multiplicity of compliant semiconductor chip packages, whereby the packages are diced after the bond ribbons have been formed.
A further aspect of the present invention includes the structure of a unique compliant semiconductor chip package having fan-in type leads. The compliant semiconductor chip package is comprised of (1) a semiconductor chip having a plurality of peripheral bonding pads on a face surface thereof and a central region bound by the peripheral bonding pads; (2) a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface of the first dielectric layer is joined to the face surface of the semiconductor chip and the peripheral bonding pads are exposed through the apertures; (3) a compliant layer having a top surface and a bottom surface, wherein the bottom surface of the compliant layer is joined to the second surface of the first dielectric layer within the central region of the semiconductor chip package; and (4) a plurality of electrically conductive bond ribbons, each bond ribbon having a first end that electrically couples to a respective peripheral bonding pad of the semiconductor chip and a second end that joins to the top surface of the compliant layer to form a package terminal.
The package terminals of the completed package are configured in an array that has an area smaller than the area bound by the peripheral bonding pads on the face of the semiconductor chip. In other words, the package has fan-in leads that permit minimization of the overall package size.
For increased reliability, the compliant layer has sloped peripheral edges so that the overlying bond ribbons are curved rather than kinked.
The compliant semiconductor chip package may also have a compliant layer characterized by an array of bumped protrusions. The bumped protrusions support the overlying conductive terminal position ends of the bond ribbons and function as conductive balls that join to a substrate thus forming a ball grid array type interconnection. Alternate to the bumped protrusions, the compliant layer may have an array of concavities that are useful for placement of solder balls into each concavity. This arrangement is also useful for a ball grid array type interconnect.
The foregoing and other objects and advantages of the present invention will be better understood from the following Detailed Description of a Preferred Embodiment, taken together with the attached figures.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a cross-sectional view of a semiconductor chip assembly at the beginning of a fabrication process.
FIG. 1B is a cross-sectional view of the semiconductor chip assembly after a first step of the fabrication process, showing a deposited or laminated dielectric passivation layer.
FIG. 1C is a cross-sectional view of the semiconductor chip assembly after a second step of the fabrication process, showing a deposited or laminated compliant layer within the central region of the semiconductor chip contact-bearing surface.
FIG. 1D is a cross-sectional view of the semiconductor chip assembly after a third step of the fabrication process, showing a conductive seed layer that has been sputtered over the assembly.
FIG. 1E is a cross-sectional view of the semiconductor chip assembly after a fourth step of the fabrication process, illustrating how after a photolithographic step conductive bond ribbons can be formed over the assembly.
FIG. 1F is a cross-sectional view of the semiconductor chip assembly after a fifth step of the fabrication process, showing how the assembly is coated with a second dielectric protective layer.
FIG. 2 is a perspective view of the semiconductor chip assembly after the bond ribbons have been formed over the compliant layer but before the second dielectric protective layer is coated.
FIG. 3 is a plan view of a wafer having a multiplicity of semiconductor chips, illustrating how said multiplicity of semiconductor chips can be simultaneously packaged using the semiconductor chip assembly process depicted in FIGS. 1A-1F.
FIG. 4 is a cross-sectional view of an alternate embodiment of the present invention, illustrating the use of a low modulus encapsulant material to provide further support and stress relief to the bond ribbons.
FIG. 5A is a cross-sectional view of an alternate embodiment of the present invention, illustrating the formation of bumped protrusions in the compliant layer that raise the overlying terminals such that the terminals form an array over the top surface of the compliant layer.
FIG. 5B is a perspective view of the embodiment shown in FIG. 5A.
FIG. 6A is a cross-sectional view of an alternate embodiment of the present invention, illustrating the formation of concave areas in the compliant layer such that the overlying terminals have cup-like depressions useful for accurate placement of solder balls.
FIG. 6B is a perspective view of the embodiment shown in FIG. 6A.
FIG. 7A is a cross-sectional view of a first step of a semiconductor chip assembly process according to another embodiment of the present invention.
FIG. 7B is a cross-sectional view of the assembly shown in FIG. 7A, showing a mold for forming a compliant layer on top of the assembly.
FIG. 7C is a cross-sectional view of the assembly shown in FIG. 7B after conductive bond ribbons have been formed atop the compliant layer.
FIG. 7D shows the assembly of FIG. 7C after the top of the assembly has been coated with an additional dielectric protective layer.
FIG. 8A is a perspective view of the semiconductor chip assembly shown in FIG. 7C, before the additional dielectric protective layer has been provided over the bond ribbons.
FIG. 8B is a close-up, fragmentary, cross-sectional view of the assembly shown in FIG. 7D.
FIG. 9 is a cross-sectional view of another embodiment of the present invention, which includes a semiconductor chip having a plurality of contacts in a central region thereof.
FIG. 10 is a perspective view of the assembly shown in FIG. 9.
FIG. 11 is a top view of a semiconductor chip having a plurality of non-uniform, staggered chip contacts in a peripheral region of a semiconductor chip, in accordance with another embodiment of the present invention.
FIG. 12 is a fragmentary top view of the chip shown in FIG. 11 after a compliant layer and bond ribbons have been formed atop the chip.
FIG. 13 is a cross-sectional view of a compliant chip assembly having a supporting element with a central opening and a semiconductor chip provided in the central opening of the supporting element in accordance with yet another embodiment of the present invention.
FIG. 14 is a cross-sectional view of a compliant chip assembly including a flexible dielectric sheet in accordance with still another embodiment of the present invention.
FIG. 15 is a cross-sectional view of a compliant chip assembly including a ground plane in accordance with a further embodiment of the present invention.
FIG. 16 is a fragmentary top view of the compliant chip assembly shown in FIG. 15.
FIG. 17 is a cross-sectional view of a compliant chip assembly including a ground plane in accordance with still further embodiments of the present invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
FIGS. 1A-F illustrate a side view of the process of creating the compliant chip package of the present invention on the face surface of a single die, on the face surfaces of multiple die arranged in a coplanar array or on the face surface of an undiced silicon wafer which may be subsequently diced into individual packaged chips or multi-chip modules.
FIG. 1A shows a single semiconductor chip 100 with a contact bearing face surface 120. The contacts 110 on the face surface 120 are typically aligned in a peripheral region 112 and further define a central region 115 therein. In FIG. 1B, a dielectric passivation layer is deposited or adhered onto the face surface 120 of the chip 100. The passivation layer may simply be the SiO2 passivation layer (not shown) commonly found on the contact bearing surface of semiconductor chips, or a separate dielectric passivation layer 130 may be used, such as an epoxy resin, a polyimide resin, photo-imagable dielectric, etc. If the separate passivation layer 130 is used, the passivation layer 130 may be spun onto and built up to a planar sheet-like form on the face surface 120 or a dielectric sheet may be laminated to the face surface 120 using any of a number of electronic grade adhesives commonly known and used by those skilled in the art. The passivation layer 130 covers the face surface 120 of the chip 100 while leaving the chip contacts 110 exposed so that a bond ribbon may be plated thereon in a later step, as described below. Typically, this will be done by depositing or adhering the passivation layer 130 in a continuous sheet on the face surface 120 of the chip 100. A registering system, such as an automatic vision system, is used to locate the contacts 110. If a photo-imagable dielectric is used, the passivation layer 130 may be exposed and developed without exposing the area above the contacts 110, that unexposed area may then be removed. Another removal process that can be used is to use a pulse of directed energy, such as an excimer laser, to selectively remove the passivation layer 130 above the contacts 110. Alternately, a continuous dielectric sheet already having set contact holes may be registered and laminated to the chip 100.
In the next step, as illustrated in FIG. 1C, a compliant layer 140 is deposited or laminated onto the exposed surface of the passivation layer 130. The compliant layer 140 may be stenciled, screened or transfer molded onto the passivation layer 130 using a curable liquid which, when cured, adheres to the passivation layer 130. Alternately, the compliant layer 140 may be adhered to the exposed surface of the passivation layer 130 in the form of cured compliant pads using the aforementioned electronic grade adhesives. The compliant layer 140 has a substantially flat top surface 147, which further typically has a gradual, sloping transition 145 between the face surface 120 of the chip 100 and the top surface 147. This transition 145 may follow a line of curvature from the passivation layer 130 to a substantially flat top surface 147 or may simply be canted at an angle such that the transition 145 is not too vertically oriented in relation to the passivation layer 130 and the top surface 147. The compliant layer 140 itself may be formed from a wide variety of materials; however, preferably, a low modulus of elasticity material is used as the compliant layer 140. Compliant interposers typically are fabricated from polymeric and other materials such as silicones, flexibilized epoxy, polyimides and other thermosetting polymers, fluoropolymers and thermoplastic polymers. Also, the interposer may be a composite incorporating plural materials. The interposer may consist of, or incorporate, a foam or mesh layer. The flexibility of the interposer depends on the thickness and configuration of the interposer, as well as on the properties of the materials used therein. Thus, a flexible interposer, capable of buckling or wrinkling to accommodate relative movement, can be fabricated from high elastic modulus materials, normally considered as “rigid” provided that these materials are present in thin layers. Relatively soft materials and foams can be used in greater thicknesses and still provide a highly flexible interposer. Moreover, such soft materials and foams provide a highly compliant interposer, i.e., an interposer that is readily compressible in the directions perpendicular its surfaces and which therefore permits movement of the terminals in these directions.
A plating seed layer 150 is then deposited atop the aforementioned assembly, as shown in FIG. 1D, typically using a sputtering operation. Typical plating seed layer materials include palladium (for electroless plating), titanium, tungsten, nickel, and chromium; however, primarily copper seed layers are used. FIG. 1E shows the next step in which photoresist 160 is applied to the exposed top surfaces of the assembly and then exposed and developed such that bond ribbons 170 may be plated within defined areas to form conductive paths electrically connecting the chip contacts 110 near a first end region of the ribbons 170 to terminals 175 comprising the second end region of the ribbons 170. This is perhaps more easily seen in the perspective view shown in FIG. 2. As shown, the ribbons 170 are plated directly onto the contacts 110 and extend in a “fan-in” arrangement from the peripheral region 112 to the central region 115 of the face surface 120 of the chip 100 atop the compliant layer 140. Possible bond ribbon materials include copper, gold, nickel, and alloys, combinations and composites thereof, among others. Since the bond ribbons 170 are plated directly onto the chip contact/compliant layer themselves, there is no need to develop a process for bonding the ribbons 170 to the contacts, as is necessary with most other approaches such as TAB, beam lead or wirebonding. This provides a significant cost savings because specialized thermocompression or ultrasonic bonders and their bonding tools need not be purchased or maintained. It is important, however, that the material selected for the bond ribbon 170 be compatible with the chip contact 110 material, which is typically aluminum. Otherwise, a phenomenon called Kirkendahl Voiding (voids created at the boundary of two metals having different interdiffusion coefficients) may cause voiding along the boundary of the two metals (ribbon/contact) leading to intermetallic degradation and embrittlement of the bond ribbon 170 itself making the lead/bond susceptible to failure during thermal cycling. Alternately, one or more barrier metals may be plated atop the chip contacts 110 prior to the bond ribbon plating step to thereby ensure the compatibility of materials.
As shown in FIG. 1F, preferably, a dielectric layer 180 is deposited or laminated over the top of the assembly so that only the terminals 175 are exposed. The dielectric layer may be comprised of a screened, exposed and developed or laminated sheet photo resist material or may be comprised of paralyne, epoxy resin, polyimide resin, fluoropolymer, etc. which is deposited or laminated on to the assembly, as described above in relation to the passivation layer 130. The terminals 175 may then be electrically connected to a circuitized substrate, such as a printed wiring board.
Typically, a solder ball or a solid-core solder ball will be used to create this electrical connection. The dielectric layer 180 is thus used as a solder mask to ensure that the solder does not electrically short between adjacent bond ribbons 170. Oxide layers and other surface contaminates typically build up on the surface of many types of metal (copper, nickel, etc.). Although not shown in FIG. 1F, the terminals 175 are typically flash plated with a thin layer of gold (approximately 0.25 to 0.5 microns) to inhibit the formation of these oxide layers. The gold layer is kept very thin so that it does not appreciably affect the aforementioned solder joint by dissolving into the solder to an amount which would embrittle the resulting solder joint between the terminal and a circuitized substrate.
The configuration of the above described chip package allows the package to mechanically decouple the chip 100 from an attached circuitized substrate (not shown). Typically, solder connections between the chip and the circuitized substrate are woefully inadequate to compensate for the thermal mismatch problem during temperature cycling of the chip. The combination of the compliant layer 140 and the flexible bond ribbons plated thereon allow the package to compensate for much of the TCE mismatch problem by giving limited movement of the terminals in the X, Y and Z directions with respect to the chip contacts 110 thereby minimizing the stress placed on the solder connections themselves, without imposing substantial forces on the bond between the ribbons 170 and the chip contacts 110. Further, because the compliant layer 140 is compressible, it also has the effect of compensating for any terminals 175 which are not perfectly planar with respect to its adjacent terminals when the terminals 175 are abutted against and coupled to the circuitized substrate. However, the top surface 147 of the compliant layer 140 should be made as flat and planar as possible so that the terminals 175 all lie in or near the same plane in order to minimize the amount of pressure needed to be placed on the bottom surface 125 of the chip 100 to ensure that all of the terminals/solder balls are electrically connected to a circuitized substrate.
As illustrated in FIG. 3, the chip package described above in relation to FIGS. 1 and 2 may also be provided in the form of a multiplicity of packages on a wafer incorporating a plurality of individual, undiced chips, all of the same design or of differing designs. As shown, an array of individual passivation layers 230 may be deposited or laminated onto the face surface 220 of the wafer 200 leaving the chip contacts 210 of the various individual chips exposed, as described above. This arrangement is shown to better define the individual chips within the wafer. Preferably, however, a single passivation layer 230 is deposited or laminated onto the face surface 220 leaving the contacts 210 exposed. Individual compliant layers 240, as described above, are deposited or laminated onto the central regions of each of the individual chips within the wafer 200. The steps found in FIGS. 1A-F are then performed, as described above, to create a plurality of connected individually packaged chips on the face surface 220 of the wafer 200. Each packaged chip having bond ribbons 270 which are connected at one end to contacts 210 and extending in to a central region of the respective chip in a fan-in fashion atop a respective compliant layer 240 and ending with a terminal 275 on the top surface 247 of the compliant layer 240. After the individual packages are completed, the individual chips may be separated from the wafer 200 and from one another, as by cutting the wafer 200 using conventional wafer severing or “dicing” equipment commonly utilized to sever wafers into individual chips. This procedure yields a plurality of packaged chip subassemblies, each of which may be secured to an individual circuitized substrate. Alternately, the chips may be separated from the wafer 200 in multi-chip arrangements of multiples of the same or different operational chips. The wafer level embodiment shown in FIG. 3 could be simulated using a panel of individual chips spaced apart from one another in a processing boat. The face surfaces of the individual chips would be coplanar with respect to one another to simulate the face surface 220 of the wafer 200. The chips above described steps would be performed and the chips would be separated if desired.
In the alternate embodiment shown in FIG. 4, a low modulus encapsulant material 290 may be deposited around the exposed surfaces of the bond ribbons 170′ leads prior to the step shown in FIG. 1F of depositing or laminating the assembly with the dielectric layer 180′. The encapsulant material 290 may have properties similar to those of rubber, gum or gel. Typical encapsulation materials include curable liquid or cured pads comprised of silicone, flexibilized epoxy, gels, thermoplastics, etc. If the encapsulant 290 is applied as a curable liquid, a fixture may be made such that the liquid flows around the bond ribbons 170′ but does not flow on top of the terminals 175′ to ensure that solder balls may be subsequently electrically connected to the terminals 175′, as described above. Alternately, a machine such as a Camalot 1818 manufactured by Camalot Systems, Inc. of Havermill, Mass. may be used to flow the liquid encapsulant into the desired areas. After the liquid is deposited, it may be cured by any number of ways depending on the encapsulant material 290 used, e.g. heat, infrared energy, etc. The encapsulant 290 gives each of the bond ribbons 170′ more support and further spreads some of the stress away from the ribbons 170′ thus allowing a larger TCE mismatch between the chip and a circuitized substrate, as described above. After curing of the encapsulant 290, the dielectric layer 180′ may be deposited or laminated thereto.
In another alternate embodiment, a conductive material such as beryllium copper, or a super plastic or shape memory alloy (such as Nitinol), is sputtered or otherwise deposited across the entire exposed surface of the chip/passivation layer/compliant layer (100/130/140) combination, shown in FIG. 1C. The conductive material may then be etched using industry standard photolithographic techniques resulting in a multiplicity of bond ribbons positioned and configured much like the bond ribbons 170 shown in FIG. 1E and FIG. 2. In this embodiment, as described above, a barrier metal, such as a flash plated layer of gold, may first be plated to the chip contacts to ensure compatibility of the electrical connection between the chip contact and the bond ribbon. Likewise, a flash plated layer of gold may be plated atop the exposed surface of the terminal. Also, the entire exposed surface of the bond ribbon could be plated with a thin layer of gold to increase the overall conductivity of such super plastic leads. A dielectric layer is next deposited or laminated as shown in FIG. 1F.
FIG. 5A shows a side view and FIG. 5B a perspective view of another embodiment, according to the present invention. In this embodiment, the compliant layer 140′ has protrusions 300 on its top surface 147′. These protrusions 300 may be integral with the compliant layer 140′ or may be deposited or laminated onto the top surface 147′ subsequent to the formation of the compliant layer 140′. The protrusions 300 may be formed of compliant, elastomeric material, such as the material comprising the compliant layer 140′, or may be comprised of a semi-rigid or rigid material. The bond ribbon terminals 175′ are plated on top of the protrusions 300 thereby providing raised surfaces that may be connected to a circuitized substrate. This technique allows for connection to such a substrate using less solder and without the need to accurately position solid-core solder balls.
FIG. 6A shows a side view and FIG. 6B a perspective view of another embodiment, according to the present invention. In this embodiment, concave areas 310 are created in the compliant layer 140″. These concave areas 310 may be create in the formation of the compliant layer 140″ or may be created subsequent to the formation of the compliant layer 140″. The bond ribbon terminals 175″ are plated within the concave areas 310 creating conductive “cup-like” areas on the top surface 147″ of the compliant layer 140″. Solder or solid-core solder balls are then placed within these areas 310 and reflowed to attach the package to a circuitized substrate, as described earlier. This technique allows for the accurate placement of solder or solid-core solder balls by allowing them to be deposited and retained within the cup-like areas.
FIGS. 7A-7D illustrate a side view of a method of making a compliant microelectronic package including a semiconductor chip having an area array of contacts on a first surface thereof. The package is preferably assembled by using the method steps described above.
FIG. 7A shows a single semiconductor chip 400 having a first surface 420 including a plurality of contacts 410 provided in an area array over the first surface 400. A dielectric passivation layer 430 is deposited over the first surface 420 of the chip 400 and preferably covers the first surface 420 of the chip 400 while leaving the chip contacts 410 exposed so that a bond ribbon (not shown) may be plated thereon, as will be described in more detail below.
Next, as illustrated in FIG. 7B, the chip 400, including the passivation layer 430, is placed in a mold 488 so that a compliant layer may be formed atop the passivation layer 430. The compliant layer 440 is preferably molded onto the passivation layer 430 using a curable liquid which, when cured, adheres to the passivation layer 430. In one preferred embodiment, the mold 488 has downwardly extending projections 489 which are shaped to completely cover the chip contacts 410 when the mold 488 is in a closed position. The mold 488 includes open spaces 493 between the projections 489. In order to form the compliant layer 440, the chip 400 is placed in a frame 491 and the mold is closed on top of the chip 400 so that the projections 489 completely cover the contacts 410. Next, a curable liquid 440 is introduced into the mold and fills the open spaces 493 between the projections 489. The curable liquid is then cured while the mold remains in the closed position so as to form the compliant layer 440 having a substantially flat top surface 447 including a plurality of openings 495 aligned with the contacts 410. The height of projections 489 is exaggerated in FIG. 7B for clarity of illustration. In practice, projections 489 typically are about 75-200 microns high, and hence compliant layer 440 typically is about 74-200 microns thick. In each opening 495 has a gradual sloping edge 497 or transition between the first surface 420 of the chip 400 and the top surface 447 of the compliant layer 440. This sloping edge 497 will preferably follow a line of curvature from the passivation layer 430 to the substantially flat top surface 447, or may simply be canted at an angle such that the sloping edge 497 is not too vertically oriented in relation to the passivation layer 430 and the top surface 447 of the compliant layer. For example, sloping edge 497 typically is disposed at an angle of about 20-70° to the plane of the chip front surface, and more typically about 40-60°. Also, the sloping surface typically is curved to define a radius at the juncture of sloping surface 497 and top surface 447. A further radius or fillet can be provided at the junction of the sloping surface and the front surface of the chip.
In the next step, illustrated in FIG. 7C, bond ribbons 470 are selectively formed within defined areas to create conductive paths electrically connecting the chip contacts 410 near a first end of the bond ribbons 470 to conductive terminals 475 at a second end of the bond ribbons. In certain embodiments, the bond ribbons 470 may be formed using selective electroplating or other selective deposition techniques. In other embodiments, the selection forming step used to make bond ribbons 470 may include one or more non-selective deposition techniques such as electroless plating or sputtering of a conductive layer over the assembly, with or without an additional non-selective electroplating step, followed by selectively etching of the conductive layer to provide electrically isolated bond ribbons. FIG. 8A shows a perspective view of the bond ribbons after they have been selectively formed over the compliant layer. In alternative embodiments, one or more barrier metal layers 415 (FIG. 8B) may be plated atop the chip contacts 410 prior to forming the bond ribbons 470 so as to insure the compatibility of materials.
Referring to FIG. 7D, a dielectric layer 480 is then deposited or laminated over the top of the assembly so that only the conductive terminals 475 are accessible at the top of the assembly. The terminals 475 may then be electrically interconnected with an external circuit element, such as a printed circuit board. Typically, a solder ball or solid core solder ball will be used to create this electrical connection. Thus, the dielectric layer 480 serves as a solder mask, thereby insuring that the solder does not electrically short between adjacent bond ribbons 470.
FIG. 8B shows a close-up, fragmentary, cross-sectional view of FIG. 7D. The assembly includes the compliant layer 440 having a plurality of apertures 495 therein so the contacts 410 are accessible through the apertures 495. Each aperture 495 in the compliant layer 440 preferably includes at least one sloping edge side wall 497 that provides a gradual sloping transition between the first surface 420 of the chip 400 and the top surface 447 of the compliant layer 440. The transition preferably follows a line of curvature from the passivation layer 430 to the top surface 447 or may simply be canted at an angle so that the transition from the first surface 420 of the chip 400 to the top surface 447 of the compliant layer 440 is not too vertically oriented in relation to the passivation layer 430. The top surface 447 of the passivation layer is preferably substantially flat, however, in certain embodiments the top surface 447 may be slightly rounded. As stated above, the low points in the compliant layer may next be filled with compliant material to encase the leads and/or cover sheets of material.
As illustrated in FIG. 9, a compliant chip package in accordance with another preferred embodiment of the present invention includes a single semiconductor chip 500 having a first surface 520 with a first or central region 515 and a second or peripheral region 517 surrounding the central region 515. The chip 500 includes a plurality of contacts 510 disposed in the central region 515 thereof. A passivation layer 530 is preferably deposited over the first surface 520 of the chip 500. The passivation layer 530 includes apertures aligned with the contacts 510 so that the chip contacts 510 are accessible through the passivation layer 530. A compliant layer 540 is then formed over the passivation layer, the compliant layer having openings 595 in alignment with the chip contacts 510 so that the contacts are accessible through the compliant layer openings 595. The steps described above are then performed to create a plurality of bond ribbons 570 which are connected at one end to the chip contacts 510 and at a second end to conductive terminals 575 accessible at the substantially flat surface 547 of the compliant layer 540. The final assembly provides a compliant chip package having a plurality of contacts 510 in the central region 515 thereof and bond ribbons 570 extending outwardly from the contacts 510 to conductive terminals 575 overlying the peripheral region 517 of the chip 500. The centrally located low point in the compliant layer can be filled in with compliant material to encapsulate the leads.
FIG. 10 shows a perspective view of the package illustrated in FIG. 9. As shown in FIG. 10, the plurality of contacts 510 is located in the central region 515 of the chip 500. Compliant layer 540 defines two sloping edges 572 at the border of the first or central region of the chip surface and the second or peripheral region. Bond ribbons 570 have first ends electrically connected to the contacts 510 and second ends extending to conductive terminals 575 provided at the top surface 547 of the compliant layer 540. The specific embodiment shown in FIG. 10 includes a compliant layer 540 having a first section on the left side of the chip 500 and a second section on the right side of the chip 500, however, other preferred embodiments may include compliant layers having more than two distinct portions.
In still another embodiment, illustrated in FIG. 11, a compliant chip package includes a semiconductor chip 600 having a first surface with a central region 615 and a peripheral region 612 surrounding the central region 615. The peripheral region 612 includes a plurality of contacts 610 which are arranged in a staggered or non-uniform configuration. In other words, the peripheral region 612 includes contacts 610 which are positioned at non-uniform distances from an edge 617 of the chip 600. In other embodiments, the chip may include contacts clumped together in groups and/or disposed in a non-uniform pattern throughout the entire first surface of the chip.
The method steps described above are then utilized to provide a final compliant chip package, as shown in FIG. 12, whereby the contacts 610 are positioned at varying distances from the edge 617 of the chip 600. FIG. 12 shows four different contacts, designated 610A-610D, located in the peripheral region 612 of the chip 600. The contacts are staggered with respect to one another so that contacts 610B and 610D are closer to the edge 617 of the chip than contacts 610A and 610C. The contacts 610 are electrically connected to terminals 675 by bond ribbons 670. The actual length of bond ribbons 670 may vary based upon the position of the contact 610 and the desired position of the terminal 675. For example, although contacts 610A and 610C are positioned at a uniform distance from the edge 617 of the chip 600, bond ribbon 670C is longer than bond ribbon 670A. As a result, the terminal 675C connected to bond ribbon 670C may be positioned at a more central location than terminal 675A. The ability to modify the length of the bond ribbons 670 allows the terminals 675 to be positioned at an infinite number of different locations over the top surface 647 of the compliant layer 640 so that the chip package can be reliably interconnected with an external circuit element, regardless of the location of contact pads on the external circuit element.
In a further embodiment, illustrated in FIG. 13, the compliant chip package includes a supporting element 792 adjacent a semiconductor chip 700, with conductive terminals 775 formed over a top surface 794 of the supporting element 792. The supporting element 792 may include a bar or alternatively a ring having an opening 795 in the center thereof. In the latter embodiment, the semiconductor chip 700 is provided within the opening 795 so that a first contact bearing surface 720 of the chip 700 is substantially parallel with the top surface 794 of the supporting element 792. The first surface 720 of the semiconductor chip 700 preferably includes a passivation layer 730 having openings therein so that the contacts 710 are accessible through the openings. A compliant layer 740 having a substantially flat top surface 747 and a bottom surface and sloping edges 797 therebetween is then formed atop the top surface 794 of the supporting element 792 and a portion of the passivation layer 730. The compliant layer 740 preferably fills gaps 755 between the peripheral edges of the chip 700 and the support element 792. In addition, the compliant layer 740 preferably has a meniscus-shaped top surface so that the transition from the passivation layer 730 to the compliant layer 740 is smooth. This smooth transition will increase the reliability of any bond ribbons formed atop the compliant layer because the bond ribbons will be gently curved rather than kinked. Next, bond ribbons 770 are formed using the techniques described above, and a dielectric layer 780 is formed over the bond ribbons 770 so that only conductive terminals 775 are accessible at the top of the assembly. In certain embodiments the supporting element 792 may include a heat sink and the compliant layer may be formed on the top surface of flanges extending laterally from central opening in the heat sink.
In still another embodiment, illustrated in FIG. 14, the compliant chip package includes a flexible dielectric sheet 865, such as a polyimide sheet, secured over the top of the compliant layer 840. The package includes a semiconductor chip 800 having a first surface 820 with contacts 810. A dielectric passivation layer 830, including openings in substantial alignment with the contacts 810, is then formed over the first surface 820 of the chip 800. After the compliant layer 840 has been formed, the flexible dielectric sheet 865 is provided over the top surface 847 of the compliant layer 840. The flexible dielectric sheet 865 generally improves the structural integrity of the package and protects the compliant layer 840 from external contaminants. Bond ribbons 870 are then formed atop the passivation layer 830, the compliant layer 840 and the flexible dielectric sheet 865. The bonds ribbons 870 have first ends which are connected to chip contacts 810 and second ends which provide conductive terminals 875 over the flexible dielectric sheet 865. In certain embodiments the dielectric sheet 865 is provided as a separate sheet which is laminated or secured over the top surface 847 of the compliant layer 840. In these embodiments, the conductive terminals 875 may be pre-formed on the dielectric sheet 865, with the bond ribbon forming step electrically interconnecting the contacts 810 and the pre-formed conductive terminals 875. In still further embodiments, the flexible dielectric sheet 865 may be spun onto the top surface 847 of the compliant layer 8340. As such, the edges of the spun-on dielectric sheet have radii of curvature which substantially match the radii of curvature of the edges of the compliant layer. The matched edges provide a smooth transition from the dielectric sheet 865 to the compliant layer 840, thereby providing a more uniform surface for forming the bond ribbons 870. A second dielectric protective layer 880 may then be formed over the bond ribbons 870 to further protect the bond ribbons and electrically isolate the bond ribbons from one another.
In another embodiment, illustrated in FIGS. 15 and 16, a compliant chip package includes a ground plane 981. As shown in FIG. 15, a semiconductor chip 900 is provided within a central opening 995 of a supporting element 992 so that a first contact bearing surface 920 of the chip 900 is substantially parallel with a top surface 994 of the supporting element 992. A first compliant layer 940 having a substantially flat top surface 947 and a bottom surface and sloping edges 997 therebetween is then formed atop the top surface 994 of the supporting element 992. The compliant layer 940 preferably fills gaps 955 between the peripheral edges of the chip 900 and the support element 992. The sloping edges 997 preferably provide a smooth transition between the top surface 947 of the compliant layer 940 and the chip 900. Bond ribbons are then formed over the compliant layer 940 using the techniques described above. The sloping edges 997 of the compliant layer 940 will increase the reliability of the bond ribbons 970 because the bond ribbons will be gently curved rather than kinked. Next, a second compliant layer 941 is formed atop the bond ribbons 970 so as to encapsulate the bond ribbons 970. A dielectric layer 980 is then formed over the second compliant layer 941 and the bond ribbons 970 so that only conductive terminals 975 are accessible at the top of the assembly. The ground plane 981 is then provided atop the dielectric layer 980. Referring to FIG. 16, the ground plane preferably includes a highly conductive material, such as copper, having a plurality of openings therein. The openings are preferably formed using photolithographic and etching techniques. The openings are sized to fit over the terminals 975 and a relatively small portion of the bond ribbon 970 extending away from each terminal 975. The ground plane 981 is assembled to the dielectric layer by aligning the openings 983 therein with the terminals 975 and abutting the ground plane 981 against the top of the dielectric layer 980. The package is then subjected to a curing process so as to cure the compliant layers 940 and 941 and the dielectric layer 980.
FIG. 17 shows yet another embodiment of a compliant chip package which is similar to that shown in FIG. 15, however, the FIG. 17 embodiment lacks the top dielectric cover layer shown in FIG. 15. Referring to FIG. 17, after the second compliant layer 1041 is formed atop the bond ribbons 1070, a ground plane 1081, similar to that shown in FIG. 16 is provided over the second compliant layer 1041. During assembly, the ground plane 1081 may be compressed against the second compliant layer 1041 so that the ground plane 1081 is slightly sunk into the second compliant layer 1041. The ground plane preferably includes openings 1083 which are in alignment with terminals 1075 so that the terminals 1075 are accessible through the openings 1083. The package is then subjected to a curing process so as to cure the compliant layers 1040 and 1041. The ground plane 1081 is preferably electrically connected to at least one of the bond ribbons 1070.
These and other variations and combinations of the features described above may be utilized without departing from the present invention as defined by the claims. For example, the low modulus encapsulant material shown in FIG. 4 may be used to assemble any of the compliant chip packages shown in FIGS. 7A-14 to provide additional stress relief for the bond ribbons. In addition, the assembly shown in FIG. 13 may be modified so as to provide conductive terminals over the central region of the chip, thereby providing a “fan-in/fan-out” compliant chip package. Moreover, all of the chip package assemblies disclosed above may be assembled on a wafer prior to severing the individual chips from the wafer. Thus, the foregoing description of the preferred embodiments should be taken by way of illustration rather than by way of limitation of the invention set forth in the claims.
As these and other variations and combinations of the features discussed above can be utilized without departing from the present invention as defined by the claims, the foregoing description of the preferred embodiments should be taken by way of illustration rather than by way of limitation of the invention set forth in the claims.

Claims (47)

1. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts accessible at the first surface;
a compliant layer over said first surface of said microelectronic element, said compliant layer including a plurality of compliant bumped protrusions and openings adjacent said bumped protrusions for providing access to said contacts, wherein each said compliant bumped protrusion includes a top surface and at least one sloping edge;
conductive terminals over said top surfaces of said bumped protrusions;
a plurality of conductive bond ribbons having first ends in engagement with said contacts, second ends in engagement with said terminals and intermediate sections extending along said sloping edges of said compliant bumped protrusions for electrically interconnecting said contacts and said terminals.
2. The microelectronic assembly as claimed in claim 1, wherein said bumped protrusions are integrally formed with said compliant layer.
3. The microelectronic assembly as claimed in claim 2, wherein said compliant bumped protrusions enable said conductive terminals and said conductive bond ribbons to move relative to said first surface of said microelectronic element.
4. The microelectronic assembly as claimed in claim 1, wherein said microelectronic element is a semiconductor chip.
5. The microelectronic assembly as claimed in claim 1, further comprising a dielectric passivation layer between the first surface of said microelectronic element and said compliant layer, wherein said dielectric passivation layer has apertures extending therethrough in substantial alignment with said contacts.
6. The microelectronic assembly as claimed in claim 1, further comprising a dielectric layer overlying the top surface of said bond ribbons.
7. The microelectronic assembly as claimed in claim 1, wherein the top surface of each said bumped protrusion has an apex, and wherein said terminals are substantially aligned over said apexes of said bumped protrusions.
8. The microelectronic assembly as claimed in claim 1, wherein said contacts are spaced apart from one another in an array.
9. The microelectronic assembly as claimed in claim 1, wherein said bumped protrusions have a height of approximately 50-225 microns.
10. The microelectronic assembly as claimed in claim 1, wherein the sloping edge of each said bumped protrusion forms an angle with the first surface of said microelectronic element of approximately 20-70 degrees.
11. The microelectronic assembly as claimed in claim 10, wherein the sloping edge of each said bumped protrusion forms an angle with the first surface of said microelectronic element of approximately 40-60 degrees.
12. The microelectronic assembly as claimed in claim 1, wherein each said bumped protrusion has a first radius of curvature at the juncture of the top surface and the sloping edge thereof and a second radius of curvature at the juncture of the sloping edge and the first surface of said microelectronic element.
13. The microelectronic assembly as claimed in claim 1, further comprising one or more barrier metal layers between said contacts and the first ends of said conductive bond ribbons.
14. A compliant semiconductor chip package assembly comprising:
a semiconductor chip having an array of contacts on a first surface thereof;
a compliant layer overlying the first surface of said semiconductor chip, said compliant layer including a plurality of compliant bumped protrusions integrally formed therewith, wherein each said compliant bumped protrusion has a top surface and a sloping edge that slopes between the top surface and the first surface of said semiconductor chip; and
a plurality of electrically conductive bond ribbons, each said bond ribbon having a first end attached to one of said contacts and a second end attached to a conductive terminal at the top surface of one of said compliant bumped protrusions.
15. The package assembly as claimed in claim 14, wherein each said bumped protrusion has a first transition region with a radius of curvature near the top surface of said compliant layer and a second transition region with a radius of curvature near the first surface of said semiconductor chip.
16. The package assembly as claimed in claim 14, wherein said compliant layer is selected from the group of materials consisting of a curable liquid, silicone, flexibilized epoxy, a thermosetting polymer, flouropolymer, thermoplastic polymer, polyimide and gel.
17. The package assembly as claimed in claim 16, further comprising a top dielectric layer overlying said bond ribbons so that only the conductive terminals are accessible at a top surface of said compliant layer.
18. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts accessible at the first surface;
a compliant layer over said first surface of said microelectronic element having a plurality of compliant bumped protrusions and openings adjacent said compliant bumped protrusions for providing access to said contacts, wherein each said compliant bumped protrusion is associated with one of said contacts;
conductive bond ribbons formed over said compliant bumped protrusions, said bond ribbons having first ends attached to said contacts, second ends attached to conductive terminals provided atop said compliant bumped protrusions and intermediate sections extending over sloping edges of said compliant bumped protrusions for electrically interconnecting said contacts and said terminals.
19. The assembly as claimed in claim 18, further comprising a fusible mass attached to at least one of said conductive terminals.
20. The assembly as claimed in claim 19, wherein said fusible mass comprises solder.
21. The assembly as claimed in claim 18, wherein said microelectronic element is a semiconductor chip.
22. The assembly as claimed in claim 18, further comprising a first dielectric passivation layer between the first surface of said microelectronic element and said compliant layer, said passivation layer having contacts in substantial alignment with said contacts.
23. The assembly as claimed in claim 18, wherein said bumped protrusions are integrally formed with said compliant layer, and wherein said bumped protrusions have top surfaces movable relative to the first surface of said microelectronic element.
24. The assembly as claimed in claim 23, wherein said conductive terminals are formed over the top surfaces of said bumped projections.
25. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;
a dielectric layer adhered to the first surface of said microelectronic element, said dielectric layer having a bottom surface facing toward the first surface of said microelectronic element and a top surface facing away from the first surface of said microelectronic element;
bumps of a dielectric material connected with and overlying the top surface of said dielectric layer, wherein said dielectric material bumps have curved surfaces;
conductive metal overlying said dielectric material bumps defining conductive terminals, said conductive terminals conforming to the curved surfaces of said dielectric material bumps; and
conductive traces electrically connecting said contacts and said conductive terminals.
26. The assembly as claimed in claim 25, wherein said conductive metal is plated on top of said dielectric material bumps.
27. The assembly as claimed in claim 25, wherein said bumps of a dielectric material are integrally formed with said dielectric layer.
28. The assembly as claimed in claim 25, wherein said bumps of a dielectric material are laminated onto said dielectric layer.
29. The assembly as claimed in claim 25, wherein said protruding terminals are made of a rigid material.
30. The assembly as claimed in claim 25, wherein said bumps of a dielectric material are made of a semi-rigid material.
31. The assembly as claimed in claim 25, wherein said bumps of a dielectric material are made of a compliant material.
32. The assembly as claimed in claim 25, wherein said conductive terminals are dome shaped.
33. The assembly as claimed in claim 25, wherein said dielectric layer is formed of a compliant layer.
34. The assembly as claimed in claim 25, wherein said dielectric layer is formed of an elastomeric layer.
35. The assembly as claimed in claim 25, further comprising: a dielectric passivation layer between said first surface of said microelectronic element and the dielectric layer, said passivation layer having a plurality of apertures therein so that said contacts are accessible therethrough.
36. The assembly as claimed in claim 35, wherein said traces overlie said passivation layer and said dielectric layer.
37. The assembly as claimed in claim 25, wherein said microelectronic element, includes a plurality of undiced semiconductor chips on a wafer, said dielectric layer including a plurality of regions, each said region overlying one said chip and having one or more of the conductive terminals electrically connected to said chip.
38. The assembly as claimed in claim 25, wherein said microelectronic element includes a plurality of adjacent semiconductor chips arranged in an array to form a corresponding plurality of semiconductor chip packages, said dielectric layer including a plurality of regions, each said region overlying one said chip and having one or more of the conductive terminals electrically connected to said chip.
39. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;
a first dielectric passivation layer overlying the first surface of said microelectronic element, said passivation layer including openings for said plurality of contacts;
a dielectric layer overlying said passivation layer, said dielectric layer having a bottom surface facing toward the first surface of said microelectronic element and a top surface facing away from the first surface of said microelectronic element;
bumps of a dielectric material protruding from the top surface of said dielectric layer;
conductive material overlying said dielectric material bumps defining conductive terminals; and
conductive traces electrically connecting said contacts and said conductive terminals.
40. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;
a dielectric layer having a bottom surface facing toward the first surface of said microelectronic element and a top surface facing away from the first surface of said microelectronic element;
bumps of a dielectric material integrally connected with and protruding from the top surface of said dielectric layer;
conductive material overlying said dielectric material bumps for forming conductive terminals; and
conductive traces electrically connecting said contacts and said conductive terminals.
41. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;
a dielectric layer adhered to the first surface of said microelectronic element, said dielectric layer having a bottom surface facing toward the first surface of said microelectronic element and a top surface facing away from the first surface of said microelectronic element;
bumps of a dielectric material connected with the top surface of said dielectric layer, wherein said dielectric material bumps have hemispherical surfaces;
conductive material overlying said dielectric material bumps for forming conductive terminals, wherein said conductive terminals at least partially conform to the radial surfaces of said dielectric material bumps; and
conductive traces electrically connecting said contacts and said conductive terminals.
42. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;
a dielectric layer adhered to the first surface of said microelectronic element, said dielectric layer having a bottom surface facing toward the first surface of said microelectronic element and a top surface facing away from the first surface of said microelectronic element;
bumps of a dielectric material connected with and overlying the top surface of said dielectric layer, wherein said dielectric material bumps have curved surfaces;
conductive metal permanently secured to and overlying said dielectric material bumps for forming conductive terminals, said conductive terminals conforming to the curved surfaces of said dielectric material bumps; and
conductive traces electrically connecting said contacts and said conductive terminals.
43. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;
a compliant, dielectric layer adhered to the first surface of said microelectronic element, said compliant, dielectric layer having a bottom surface facing toward the first surface of said microelectronic element and a top surface facing away from the first surface of said microelectronic element;
bumps of a rigid, dielectric material connected with and overlying the top surface of said compliant, dielectric layer, wherein said rigid, dielectric material bumps have curved surfaces;
conductive metal overlying said rigid, dielectric material bumps for forming conductive terminals, said conductive terminals conforming to the curved surfaces of said rigid, dielectric material bumps; and
conductive traces electrically connecting said contacts and said conductive terminals.
44. A microelectronic assembly comprising:
a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;
a compliant, dielectric layer adhered to the first surface of said microelectronic element, said compliant, dielectric layer having a bottom surface facing toward the first surface of said microelectronic element and a top surface facing away from the first surface of said microelectronic element;
compliant bumps connected with and overlying the top surface of said compliant, dielectric layer, wherein said compliant bumps have curved surfaces;
conductive metal overlying said compliant bumps for forming conductive terminals, said conductive terminals conforming to the curved surfaces of said compliant bumps; and
conductive traces electrically connecting said contacts and said conductive terminals.
45. The assembly as claimed in any one of claims 25 and 39-44, wherein at least one entire bump is substantially covered by the conductive material.
46. The assembly as claimed in any one of claims 25 and 39-44, wherein at least one bump has an exposed portion that is not covered by any conductive terminal or trace.
47. The assembly as claimed in claim 46, wherein each bump has an exposed portion that is not covered by any conductive terminal or trace.
US10/107,094 1995-10-31 2002-03-26 Microelectronic package having a compliant layer with bumped protrusions Expired - Lifetime US6847101B2 (en)

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US10/107,094 US6847101B2 (en) 1995-10-31 2002-03-26 Microelectronic package having a compliant layer with bumped protrusions
US10/219,902 US6847107B2 (en) 1995-10-31 2002-08-15 Image forming apparatus with improved transfer efficiency
US10/873,883 US7112879B2 (en) 1995-10-31 2004-06-22 Microelectronic assemblies having compliant layers
US11/474,199 US7872344B2 (en) 1995-10-31 2006-06-23 Microelectronic assemblies having compliant layers
US11/487,263 US7408260B2 (en) 1995-10-31 2006-07-14 Microelectronic assemblies having compliant layers
US12/974,744 US8338925B2 (en) 1995-10-31 2010-12-21 Microelectronic assemblies having compliant layers

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US712895P 1995-10-31 1995-10-31
US08/739,303 US6211572B1 (en) 1995-10-31 1996-10-29 Semiconductor chip package with fan-in leads
US09/071,412 US6284563B1 (en) 1995-10-31 1998-05-01 Method of making compliant microelectronic assemblies
US09/777,782 US6465878B2 (en) 1995-10-31 2001-02-06 Compliant microelectronic assemblies
US10/107,094 US6847101B2 (en) 1995-10-31 2002-03-26 Microelectronic package having a compliant layer with bumped protrusions

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US10/107,094 Expired - Lifetime US6847101B2 (en) 1995-10-31 2002-03-26 Microelectronic package having a compliant layer with bumped protrusions
US10/219,902 Expired - Lifetime US6847107B2 (en) 1995-10-31 2002-08-15 Image forming apparatus with improved transfer efficiency
US10/873,883 Expired - Fee Related US7112879B2 (en) 1995-10-31 2004-06-22 Microelectronic assemblies having compliant layers
US11/474,199 Expired - Fee Related US7872344B2 (en) 1995-10-31 2006-06-23 Microelectronic assemblies having compliant layers
US11/487,263 Expired - Fee Related US7408260B2 (en) 1995-10-31 2006-07-14 Microelectronic assemblies having compliant layers
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US11/474,199 Expired - Fee Related US7872344B2 (en) 1995-10-31 2006-06-23 Microelectronic assemblies having compliant layers
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Cited By (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040252477A1 (en) * 2003-06-11 2004-12-16 Brown Dirk D. Contact grid array formed on a printed circuit board
US20050052423A1 (en) * 2000-03-15 2005-03-10 Harris Glen Mclean Online remote control configuration system
US20050093128A1 (en) * 2003-09-05 2005-05-05 Canon Kabushiki Kaisha Semiconductor device, process of producing semiconductor device, and ink jet recording head
US20050124181A1 (en) * 2003-12-08 2005-06-09 Brown Dirk D. Connector for making electrical contact at semiconductor scales
US20050120553A1 (en) * 2003-12-08 2005-06-09 Brown Dirk D. Method for forming MEMS grid array connector
US20050164527A1 (en) * 2003-04-11 2005-07-28 Radza Eric M. Method and system for batch forming spring elements in three dimensions
US20050208786A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Interposer and method for making same
US20050205988A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Die package with higher useable die contact pad area
US20050208788A1 (en) * 2004-03-19 2005-09-22 Dittmann Larry E Electrical connector in a flexible host
US20050208787A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Interposer with compliant pins
US20050227510A1 (en) * 2004-04-09 2005-10-13 Brown Dirk D Small array contact with precision working range
US20060000642A1 (en) * 2004-07-01 2006-01-05 Epic Technology Inc. Interposer with compliant pins
US7019410B1 (en) * 1999-12-21 2006-03-28 Micron Technology, Inc. Die attach material for TBGA or flexible circuitry
US7056131B1 (en) 2003-04-11 2006-06-06 Neoconix, Inc. Contact grid array system
US20060194365A1 (en) * 2005-02-25 2006-08-31 Tessera, Inc. Microelectronic assemblies having compliancy
US20060192855A1 (en) * 2000-03-15 2006-08-31 Harris Glen M State-based remote control system
US20060258182A1 (en) * 2004-07-20 2006-11-16 Dittmann Larry E Interposer with compliant pins
US20060258183A1 (en) * 2003-04-11 2006-11-16 Neoconix, Inc. Electrical connector on a flexible carrier
US20070037522A1 (en) * 2005-04-20 2007-02-15 Logitech Europe S.A. System and method for adaptive programming of a remote control
US20070050738A1 (en) * 2005-08-31 2007-03-01 Dittmann Larry E Customer designed interposer
US20070054515A1 (en) * 2003-04-11 2007-03-08 Williams John D Method for fabricating a contact grid array
US20070108607A1 (en) * 2005-11-07 2007-05-17 Seiko Epson Corporation Semiconductor device
US20070134949A1 (en) * 2005-12-12 2007-06-14 Dittmann Larry E Connector having staggered contact architecture for enhanced working range
US20070141863A1 (en) * 2003-04-11 2007-06-21 Williams John D Contact grid array system
US20070145550A1 (en) * 2005-12-27 2007-06-28 Tessera, Inc. Microelectronic elements with compliant terminal mountings and methods for making the same
US20070182022A1 (en) * 2006-02-08 2007-08-09 Jong Hoon Kim Wafer level chip scale package (WLCSP) with high reliability against thermal stress
US20070218710A1 (en) * 2003-06-11 2007-09-20 Brown Dirk D Structure and process for a contact grid array formed in a circuitized substrate
US20070233731A1 (en) * 2006-02-22 2007-10-04 Logitech Europe S.A. System and method for configuring media systems
US20070232053A1 (en) * 2002-10-24 2007-10-04 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
US20070259539A1 (en) * 2003-04-11 2007-11-08 Brown Dirk D Method and system for batch manufacturing of spring elements
WO2007133806A2 (en) * 2006-05-16 2007-11-22 Tessera, Inc. Wafer level semiconductor chip packages and methods of making the same
US20080036642A1 (en) * 2000-03-15 2008-02-14 Logitech Europe S.A. Remote Control Multimedia Content Listing System
US20080150121A1 (en) * 2006-12-20 2008-06-26 Tessera Technologies Hungary Kft. Microelectronic assemblies having compliancy and methods therefor
US20080284011A1 (en) * 2007-05-18 2008-11-20 Taiwan Tft Lcd Association Bump structure
US20080315424A1 (en) * 2001-03-30 2008-12-25 Megica Corporation Structure and manufactruing method of chip scale package
US20090057901A1 (en) * 2001-09-17 2009-03-05 Megica Corporation Structure of high performance combo chip and processing method
US20090057919A1 (en) * 2000-05-19 2009-03-05 Megica Corporation Multiple chips bonded to packaging structure with low noise and multiple selectable functions
US20090174043A1 (en) * 2008-01-03 2009-07-09 Linear Technology Corporation Flexible contactless wire bonding structure and methodology for semiconductor device
US20090193654A1 (en) * 2004-03-19 2009-08-06 Dittmann Larry E Contact and method for making same
US20100035382A1 (en) * 1995-10-31 2010-02-11 Tessera, Inc. Methods of making compliant semiconductor chip packages
US20100052120A1 (en) * 2008-09-02 2010-03-04 Linear Technology Corporation Semiconductor device having a suspended isolating interconnect
US20100140794A1 (en) * 2001-10-08 2010-06-10 Chia Yong Poo Apparatus and method for packaging circuits
US20100167561A1 (en) * 2003-04-11 2010-07-01 Neoconix, Inc. Structure and process for a contact grid array formed in a circuitized substrate
US7872344B2 (en) 1995-10-31 2011-01-18 Tessera, Inc. Microelectronic assemblies having compliant layers
US20110063855A1 (en) * 2008-05-30 2011-03-17 Koninklijke Philips Electronics N.V. Round illumination device
US8026789B2 (en) 2000-03-15 2011-09-27 Logitech Europe S.A. State-based remote control system
US8508401B1 (en) 2010-08-31 2013-08-13 Logitech Europe S.A. Delay fixing for command codes in a remote control system
US8641428B2 (en) 2011-12-02 2014-02-04 Neoconix, Inc. Electrical connector and method of making it
US8918544B2 (en) 2011-03-31 2014-12-23 Logitech Europe S.A. Apparatus and method for configuration and operation of a remote-control system
US9239837B2 (en) 2011-04-29 2016-01-19 Logitech Europe S.A. Remote control system for connected devices
US9680273B2 (en) 2013-03-15 2017-06-13 Neoconix, Inc Electrical connector with electrical contacts protected by a layer of compressible material and method of making it

Families Citing this family (122)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6870272B2 (en) 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
SG73490A1 (en) 1998-01-23 2000-06-20 Texas Instr Singapore Pte Ltd High density internal ball grid array integrated circuit package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
WO2000055898A1 (en) * 1999-03-16 2000-09-21 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
WO2000077844A1 (en) * 1999-06-15 2000-12-21 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package
KR20020011440A (en) * 1999-06-17 2002-02-08 마이클 골위저, 호레스트 쉐퍼 Electronic component with flexible contact structures and method for the production of said component
US6228687B1 (en) * 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
JP4441974B2 (en) * 2000-03-24 2010-03-31 ソニー株式会社 Manufacturing method of semiconductor device
DE10016132A1 (en) * 2000-03-31 2001-10-18 Infineon Technologies Ag Electronic component for electronic devices comprises electronic switch and conducting paths on surface of the component to electrically connect the switch with metal-coated protrusions made from rubber-elastic insulating material
JP3596864B2 (en) * 2000-05-25 2004-12-02 シャープ株式会社 Semiconductor device
US6875640B1 (en) * 2000-06-08 2005-04-05 Micron Technology, Inc. Stereolithographic methods for forming a protective layer on a semiconductor device substrate and substrates including protective layers so formed
US6459150B1 (en) * 2000-08-17 2002-10-01 Industrial Technology Research Institute Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
US6580165B1 (en) * 2000-11-16 2003-06-17 Fairchild Semiconductor Corporation Flip chip with solder pre-plated leadframe including locating holes
US6617674B2 (en) 2001-02-20 2003-09-09 Dow Corning Corporation Semiconductor package and method of preparing same
DE10116069C2 (en) * 2001-04-02 2003-02-20 Infineon Technologies Ag Electronic component with a semiconductor chip and method for its production
SG120858A1 (en) 2001-08-06 2006-04-26 Micron Technology Inc Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same
DE10143790B4 (en) * 2001-09-06 2007-08-02 Infineon Technologies Ag Electronic component with at least one semiconductor chip
US7317091B2 (en) * 2002-03-01 2008-01-08 Xencor, Inc. Optimized Fc variants
US7423336B2 (en) * 2002-04-08 2008-09-09 Micron Technology, Inc. Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices
US6940177B2 (en) * 2002-05-16 2005-09-06 Dow Corning Corporation Semiconductor package and method of preparing same
JP3969295B2 (en) 2002-12-02 2007-09-05 セイコーエプソン株式会社 SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE
DE10258094B4 (en) * 2002-12-11 2009-06-18 Qimonda Ag Method of forming 3-D structures on wafers
US7230339B2 (en) * 2003-03-28 2007-06-12 Intel Corporation Copper ring solder mask defined ball grid array pad
US20040217488A1 (en) 2003-05-02 2004-11-04 Luechinger Christoph B. Ribbon bonding
DE10324450A1 (en) * 2003-05-28 2005-01-05 Infineon Technologies Ag Contacting device for electronic circuit units and manufacturing method
JP3906921B2 (en) * 2003-06-13 2007-04-18 セイコーエプソン株式会社 Bump structure and manufacturing method thereof
US20050093170A1 (en) * 2003-10-29 2005-05-05 Texas Instruments Incorporated Integrated interconnect package
US7294929B2 (en) * 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
GB0402960D0 (en) * 2004-02-10 2004-03-17 Plastic Logic Ltd Thermal imaging of catalyst in electroless deposition of metal films
DE102004009296B4 (en) * 2004-02-26 2011-01-27 Siemens Ag Method for producing an arrangement of an electrical component
JP5085012B2 (en) * 2004-04-14 2012-11-28 三星電子株式会社 Semiconductor device including bump structure and method of manufacturing the same
KR100632472B1 (en) * 2004-04-14 2006-10-09 삼성전자주식회사 Microelectronic device chip having a fine pitch bump structure having non-conductive sidewalls, a package thereof, a liquid crystal display device comprising the same, and a manufacturing method thereof
US7259468B2 (en) * 2004-04-30 2007-08-21 Advanced Chip Engineering Technology Inc. Structure of package
CN100385657C (en) * 2004-09-09 2008-04-30 精工爱普生株式会社 Electronic device and method of manufacturing the same
US7190157B2 (en) * 2004-10-25 2007-03-13 Agilent Technologies, Inc. Method and apparatus for layout independent test point placement on a printed circuit board
US7208820B2 (en) * 2004-12-29 2007-04-24 Tessera, Inc. Substrate having a plurality of I/O routing arrangements for a microelectronic device
US20060138599A1 (en) * 2004-12-29 2006-06-29 Tessera, Inc. Semiconductor members having a halogenated polymeric coating and methods for their formation
CA2548857C (en) * 2005-06-01 2015-01-06 Rohm And Haas Electronic Materials Llc Optical assemblies
US20060284313A1 (en) * 2005-06-15 2006-12-21 Yongqian Wang Low stress chip attachment with shape memory materials
JP4145902B2 (en) * 2005-07-19 2008-09-03 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
JP4273347B2 (en) * 2005-08-03 2009-06-03 セイコーエプソン株式会社 Semiconductor device
US7829793B2 (en) * 2005-09-09 2010-11-09 Magnecomp Corporation Additive disk drive suspension manufacturing using tie layers for vias and product thereof
US8553364B1 (en) 2005-09-09 2013-10-08 Magnecomp Corporation Low impedance, high bandwidth disk drive suspension circuit
DE102005043657B4 (en) * 2005-09-13 2011-12-15 Infineon Technologies Ag Chip module, method for encapsulating a chip and using an encapsulation material
TWI317164B (en) * 2006-07-28 2009-11-11 Taiwan Tft Lcd Ass Contact structure having a compliant bump and a testing area and manufacturing method for the same
US7582966B2 (en) 2006-09-06 2009-09-01 Megica Corporation Semiconductor chip and method for fabricating the same
US8133808B2 (en) * 2006-09-18 2012-03-13 Tessera, Inc. Wafer level chip package and a method of fabricating thereof
US20080123335A1 (en) * 2006-11-08 2008-05-29 Jong Kun Yoo Printed circuit board assembly and display having the same
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) * 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
JP4956173B2 (en) * 2006-12-19 2012-06-20 新光電気工業株式会社 Flip chip mounting board
JP2008198916A (en) * 2007-02-15 2008-08-28 Spansion Llc Semiconductor device and manufacturing method thereof
EP2575166A3 (en) * 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US7928582B2 (en) * 2007-03-09 2011-04-19 Micron Technology, Inc. Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces
US7994622B2 (en) * 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
US8208266B2 (en) 2007-05-29 2012-06-26 Avx Corporation Shaped integrated passives
US7691682B2 (en) * 2007-06-26 2010-04-06 Micron Technology, Inc. Build-up-package for integrated circuit devices, and methods of making same
KR101538648B1 (en) 2007-07-31 2015-07-22 인벤사스 코포레이션 Semiconductor packaging process using through silicon vias
US8193092B2 (en) 2007-07-31 2012-06-05 Micron Technology, Inc. Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices
TWI381464B (en) * 2008-08-29 2013-01-01 Hannstar Display Corp The bump structure and its making method
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
JP4535295B2 (en) * 2008-03-03 2010-09-01 セイコーエプソン株式会社 Semiconductor module and manufacturing method thereof
TWI377632B (en) * 2008-03-27 2012-11-21 Taiwan Tft Lcd Ass Contact structure and forming method thereof and connecting structure thereof
GB2464549B (en) * 2008-10-22 2013-03-27 Cambridge Silicon Radio Ltd Improved wafer level chip scale packaging
US20110067910A1 (en) * 2009-09-18 2011-03-24 International Business Machines Corporation Component securing system and associated method
JP5386302B2 (en) * 2009-10-27 2014-01-15 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
JP5400597B2 (en) * 2009-12-15 2014-01-29 ルネサスエレクトロニクス株式会社 Semiconductor device and electronic device
US8542465B2 (en) 2010-03-17 2013-09-24 Western Digital Technologies, Inc. Suspension assembly having a microactuator electrically connected to a gold coating on a stainless steel surface
JP5478331B2 (en) * 2010-03-31 2014-04-23 日本発條株式会社 Electronic equipment and disk device suspension
US8885299B1 (en) 2010-05-24 2014-11-11 Hutchinson Technology Incorporated Low resistance ground joints for dual stage actuation disk drive suspensions
US8665567B2 (en) 2010-06-30 2014-03-04 Western Digital Technologies, Inc. Suspension assembly having a microactuator grounded to a flexure
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8569167B2 (en) * 2011-03-29 2013-10-29 Micron Technology, Inc. Methods for forming a semiconductor structure
US20120282437A1 (en) * 2011-05-04 2012-11-08 Saint-Gobain Performance Plastics Corporation Film for photovoltaic devices
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8912668B2 (en) 2012-03-01 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
KR20130044050A (en) * 2011-10-21 2013-05-02 에스케이하이닉스 주식회사 Semiconductor package and stacked semiconductor package
WO2013138619A1 (en) 2012-03-16 2013-09-19 Hutchinson Technology Incorporated Mid-loadbeam dual stage actuated (dsa) disk drive head suspension
US8900929B2 (en) * 2012-03-21 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation
WO2013142711A1 (en) 2012-03-22 2013-09-26 Hutchinson Technology Incorporated Ground feature for disk drive head suspension flexures
US20130294042A1 (en) * 2012-05-07 2013-11-07 Guo-Quan Lu Methods and apparatus for connecting planar power electronics devices
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
WO2014043498A2 (en) 2012-09-14 2014-03-20 Hutchinson Technology Incorporated Co-located gimbal-based dual stage actuation disk drive suspensions
JP6356682B2 (en) 2012-10-10 2018-07-11 ハッチンソン テクノロジー インコーポレイテッドHutchinson Technology Incorporated Suspension with two-stage operation structure
US8941951B2 (en) 2012-11-28 2015-01-27 Hutchinson Technology Incorporated Head suspension flexure with integrated strain sensor and sputtered traces
US8891206B2 (en) 2012-12-17 2014-11-18 Hutchinson Technology Incorporated Co-located gimbal-based dual stage actuation disk drive suspensions with motor stiffener
TWI549243B (en) * 2013-03-07 2016-09-11 精材科技股份有限公司 Semiconductor structure and manufacturing method thereof
US8896969B1 (en) 2013-05-23 2014-11-25 Hutchinson Technology Incorporated Two-motor co-located gimbal-based dual stage actuation disk drive suspensions with motor stiffeners
US8717712B1 (en) 2013-07-15 2014-05-06 Hutchinson Technology Incorporated Disk drive suspension assembly having a partially flangeless load point dimple
TWI576973B (en) * 2013-07-24 2017-04-01 精材科技股份有限公司 Chip package and method for forming the same
EP2838114A3 (en) * 2013-08-12 2015-04-08 Xintec Inc. Chip package
US8896970B1 (en) 2013-12-31 2014-11-25 Hutchinson Technology Incorporated Balanced co-located gimbal-based dual stage actuation disk drive suspensions
US8867173B1 (en) 2014-01-03 2014-10-21 Hutchinson Technology Incorporated Balanced multi-trace transmission in a hard disk drive flexure
US9070392B1 (en) 2014-12-16 2015-06-30 Hutchinson Technology Incorporated Piezoelectric disk drive suspension motors having plated stiffeners
US9318136B1 (en) 2014-12-22 2016-04-19 Hutchinson Technology Incorporated Multilayer disk drive motors having out-of-plane bending
US9296188B1 (en) 2015-02-17 2016-03-29 Hutchinson Technology Incorporated Partial curing of a microactuator mounting adhesive in a disk drive suspension
US10011478B2 (en) * 2015-05-18 2018-07-03 Innovative Micro Technology Thermocompression bonding with raised feature
JP6689294B2 (en) 2015-06-30 2020-04-28 ハッチンソン テクノロジー インコーポレイテッドHutchinson Technology Incorporated Disk drive head suspension structure with improved reliability of gold-dielectric joint
US9640496B2 (en) * 2015-09-17 2017-05-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device
US9570373B1 (en) 2015-12-09 2017-02-14 International Business Machines Corporation Near-chip compliant layer for reducing perimeter stress during assembly process
US9646638B1 (en) 2016-05-12 2017-05-09 Hutchinson Technology Incorporated Co-located gimbal-based DSA disk drive suspension with traces routed around slider pad
US10103114B2 (en) * 2016-09-21 2018-10-16 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
TWI607535B (en) * 2016-11-23 2017-12-01 南茂科技股份有限公司 Re-distribution layer structure and manufacturing method thereof
US10529788B2 (en) * 2017-06-05 2020-01-07 Samsung Display Co., Ltd. Pattern structure for display device and manufacturing method thereof
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US20190043794A1 (en) * 2017-08-03 2019-02-07 General Electric Company Electronics package including integrated structure with backside functionality and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10978313B2 (en) 2018-02-20 2021-04-13 International Business Machines Corporation Fixture facilitating heat sink fabrication
CN115000024B (en) * 2022-04-18 2023-09-08 锐石创芯(重庆)科技有限公司 Chip packaging structure and method

Citations (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001870A (en) 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
JPS57121255A (en) 1981-01-21 1982-07-28 Hitachi Ltd Electric circuit element with metallic bump and mounting method of the seme
US4365264A (en) 1978-07-31 1982-12-21 Hitachi, Ltd. Semiconductor device with high density low temperature deposited Siw Nx Hy Oz passivating layer
US4618878A (en) 1983-06-18 1986-10-21 Kabushiki Kaisha Toshiba Semiconductor device having a multilayer wiring structure using a polyimide resin
US4813129A (en) * 1987-06-19 1989-03-21 Hewlett-Packard Company Interconnect structure for PC boards and integrated circuits
US4885126A (en) 1986-10-17 1989-12-05 Polonio John D Interconnection mechanisms for electronic components
US4902606A (en) 1985-12-20 1990-02-20 Hughes Aircraft Company Compressive pedestal for microminiature connections
US5070297A (en) 1990-06-04 1991-12-03 Texas Instruments Incorporated Full wafer integrated circuit testing device
US5072520A (en) 1990-10-23 1991-12-17 Rogers Corporation Method of manufacturing an interconnect device having coplanar contact bumps
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
JPH04280458A (en) 1991-03-08 1992-10-06 Hitachi Ltd Semiconductor integrated circuit device, and its manufacture and mounting structure
US5180311A (en) 1991-01-22 1993-01-19 Hughes Aircraft Company Resilient interconnection bridge
JPH05251455A (en) 1992-03-04 1993-09-28 Toshiba Corp Semiconductor device
US5430329A (en) 1991-01-29 1995-07-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with bonding pad electrode
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US5508228A (en) 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5604380A (en) 1993-10-07 1997-02-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a multilayer interconnection structure
US5666270A (en) 1993-10-18 1997-09-09 Fujitsu Limited Bump electrode, semiconductor integrated circuit device using the same, multi-chip module having the semiconductor integrated circuit devices and method for producing semicondutcor device having the bump electrode
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5734547A (en) 1995-02-13 1998-03-31 Iversen; Arthur H. Power switchgear
US5749997A (en) 1995-12-27 1998-05-12 Industrial Technology Research Institute Composite bump tape automated bonding method and bonded structure
US5777379A (en) 1995-08-18 1998-07-07 Tessera, Inc. Semiconductor assemblies with reinforced peripheral regions
WO1998052225A1 (en) 1997-05-13 1998-11-19 Chipscale, Inc. An electronic component package with posts on the active surface
WO1999005895A1 (en) 1997-07-22 1999-02-04 Gerhard Naundorf Conducting path structures situated on a non-conductive support material, especially fine conducting path structures and method for producing same
US5874782A (en) 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
US5937758A (en) 1997-11-26 1999-08-17 Motorola, Inc. Micro-contact printing stamp
US6043563A (en) 1997-05-06 2000-03-28 Formfactor, Inc. Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals
US6147401A (en) 1996-12-13 2000-11-14 Tessera, Inc. Compliant multichip package
US6337445B1 (en) 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US20020089058A1 (en) 1999-06-17 2002-07-11 Harry Hedler Electronic component with flexible bonding pads and method of producing such a component
US6638870B2 (en) 2002-01-10 2003-10-28 Infineon Technologies Ag Forming a structure on a wafer

Family Cites Families (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3680206A (en) 1969-06-23 1972-08-01 Ferranti Ltd Assemblies of semiconductor devices having mounting pillars as circuit connections
GB1487945A (en) * 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
JPS5321771A (en) * 1976-08-11 1978-02-28 Sharp Kk Electronic parts mounting structure
US4300153A (en) * 1977-09-22 1981-11-10 Sharp Kabushiki Kaisha Flat shaped semiconductor encapsulation
US4284563A (en) * 1978-02-08 1981-08-18 Research Corporation 9,10,11,12,12-Pentachloro 4,6-dioxa-5-thia-1-aza-tricyclo[7.2.1.02,8 ]d
US4381602A (en) * 1980-12-29 1983-05-03 Honeywell Information Systems Inc. Method of mounting an I.C. chip on a substrate
US4396936A (en) * 1980-12-29 1983-08-02 Honeywell Information Systems, Inc. Integrated circuit chip package with improved cooling means
US5310699A (en) * 1984-08-28 1994-05-10 Sharp Kabushiki Kaisha Method of manufacturing a bump electrode
US4642889A (en) * 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
US4671849A (en) * 1985-05-06 1987-06-09 International Business Machines Corporation Method for control of etch profile
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
US5302550A (en) 1985-12-24 1994-04-12 Mitsubishi Denki Kabushiki Kaisha Method of bonding a microelectronic device
US4977441A (en) * 1985-12-25 1990-12-11 Hitachi, Ltd. Semiconductor device and tape carrier
JPH01129431A (en) * 1987-11-16 1989-05-22 Sharp Corp Mounting system of semiconductor chip
US4783594A (en) * 1987-11-20 1988-11-08 Santa Barbara Research Center Reticular detector array
JPH01155633A (en) 1987-12-14 1989-06-19 Hitachi Ltd Semiconductor device
JPH01164054A (en) 1987-12-21 1989-06-28 Hitachi Ltd Integrated circuit
JPH01235261A (en) 1988-03-15 1989-09-20 Hitachi Ltd Semiconductor device and manufacture thereof
JPH01253926A (en) 1988-04-04 1989-10-11 Mitsui Toatsu Chem Inc Lead frame of semiconductor device
JPH01278755A (en) 1988-05-02 1989-11-09 Matsushita Electron Corp Lead frame and resin-sealed semiconductor device using the same
JPH0715087B2 (en) * 1988-07-21 1995-02-22 リンテック株式会社 Adhesive tape and method of using the same
JPH0256941A (en) 1988-08-20 1990-02-26 Matsushita Electric Works Ltd Sealing of semiconductor device
US5001542A (en) * 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
US4962985A (en) * 1989-10-02 1990-10-16 At&T Bell Laboratories Protective coatings for optical devices comprising Langmuir-Blodgett films
US5082811A (en) * 1990-02-28 1992-01-21 E. I. Du Pont De Nemours And Company Ceramic dielectric compositions and method for enhancing dielectric properties
US5656862A (en) * 1990-03-14 1997-08-12 International Business Machines Corporation Solder interconnection structure
US5187020A (en) * 1990-07-31 1993-02-16 Texas Instruments Incorporated Compliant contact pad
JP2892117B2 (en) 1990-08-01 1999-05-17 株式会社東芝 Method for manufacturing semiconductor device
JP2786734B2 (en) 1990-09-28 1998-08-13 株式会社東芝 Semiconductor device
US5140404A (en) * 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
US5265329A (en) * 1991-06-12 1993-11-30 Amp Incorporated Fiber-filled elastomeric connector attachment method and product
US5225966A (en) * 1991-07-24 1993-07-06 At&T Bell Laboratories Conductive adhesive film techniques
US5316788A (en) * 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5194930A (en) * 1991-09-16 1993-03-16 International Business Machines Dielectric composition and solder interconnection structure for its use
JP2927081B2 (en) * 1991-10-30 1999-07-28 株式会社デンソー Resin-sealed semiconductor device
JPH05175280A (en) * 1991-12-20 1993-07-13 Rohm Co Ltd Packaging structure of semiconductor device and method of packaging
US5203076A (en) * 1991-12-23 1993-04-20 Motorola, Inc. Vacuum infiltration of underfill material for flip-chip devices
US5401983A (en) 1992-04-08 1995-03-28 Georgia Tech Research Corporation Processes for lift-off of thin film materials or devices for fabricating three dimensional integrated circuits, optical detectors, and micromechanical devices
US5249101A (en) * 1992-07-06 1993-09-28 International Business Machines Corporation Chip carrier with protective coating for circuitized surface
US5915752A (en) * 1992-07-24 1999-06-29 Tessera, Inc. Method of making connections to a semiconductor chip assembly
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5414298A (en) 1993-03-26 1995-05-09 Tessera, Inc. Semiconductor chip assemblies and components with pressure contact
JP3269171B2 (en) * 1993-04-08 2002-03-25 セイコーエプソン株式会社 Semiconductor device and clock having the same
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
JP3445641B2 (en) * 1993-07-30 2003-09-08 株式会社デンソー Semiconductor device
US5483741A (en) 1993-09-03 1996-01-16 Micron Technology, Inc. Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice
US6326678B1 (en) * 1993-09-03 2001-12-04 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US5477611A (en) * 1993-09-20 1995-12-26 Tessera, Inc. Method of forming interface between die and chip carrier
US5772451A (en) * 1993-11-16 1998-06-30 Form Factor, Inc. Sockets for electronic components and methods of connecting to electronic components
US5431571A (en) * 1993-11-22 1995-07-11 W. L. Gore & Associates, Inc. Electrical conductive polymer matrix
US5583445A (en) 1994-02-04 1996-12-10 Hughes Aircraft Company Opto-electronic membrane probe
US5431328A (en) 1994-05-06 1995-07-11 Industrial Technology Research Institute Composite bump flip chip bonding
US5393697A (en) 1994-05-06 1995-02-28 Industrial Technology Research Institute Composite bump structure and methods of fabrication
US5656547A (en) 1994-05-11 1997-08-12 Chipscale, Inc. Method for making a leadless surface mounted device with wrap-around flange interface contacts
US6359335B1 (en) 1994-05-19 2002-03-19 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US6870272B2 (en) * 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US5659952A (en) * 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5929517A (en) * 1994-12-29 1999-07-27 Tessera, Inc. Compliant integrated circuit package and method of fabricating the same
US5707902A (en) 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
US5801446A (en) * 1995-03-28 1998-09-01 Tessera, Inc. Microelectronic connections with solid core joining units
US5874781A (en) 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
US6284563B1 (en) 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US5789271A (en) 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice
WO1997044859A1 (en) 1996-05-24 1997-11-27 Tessera, Inc. Connectors for microelectronic elements
US6030856A (en) * 1996-06-10 2000-02-29 Tessera, Inc. Bondable compliant pads for packaging of a semiconductor chip and method therefor
US5790377A (en) 1996-09-12 1998-08-04 Packard Hughes Interconnect Company Integral copper column with solder bump flip chip
US6255738B1 (en) * 1996-09-30 2001-07-03 Tessera, Inc. Encapsulant for microelectronic devices
US6130116A (en) * 1996-12-13 2000-10-10 Tessera, Inc. Method of encapsulating a microelectronic assembly utilizing a barrier
US6515370B2 (en) 1997-03-10 2003-02-04 Seiko Epson Corporation Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board
US6313402B1 (en) 1997-10-29 2001-11-06 Packard Hughes Interconnect Company Stress relief bend useful in an integrated circuit redistribution patch
US5956235A (en) * 1998-02-12 1999-09-21 International Business Machines Corporation Method and apparatus for flexibly connecting electronic devices
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6184576B1 (en) * 1998-09-21 2001-02-06 Advantest Corp. Packaging and interconnection of contact structure
US6197613B1 (en) * 1999-03-23 2001-03-06 Industrial Technology Research Institute Wafer level packaging method and devices formed
WO2000059033A1 (en) * 1999-03-25 2000-10-05 Seiko Epson Corporation Wiring board, connection board, semiconductor device, method of manufacture thereof, circuit board, and electronic device
US6537854B1 (en) * 1999-05-24 2003-03-25 Industrial Technology Research Institute Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed
US6499958B2 (en) * 1999-07-02 2002-12-31 Ingersoll-Rand Company Device and method for detachably connecting an impeller to a pinion shaft in a high speed fluid compressor
US6277669B1 (en) 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
DE10014300A1 (en) 2000-03-23 2001-10-04 Infineon Technologies Ag Semiconductor component and method for its production
US6767818B1 (en) * 2000-08-07 2004-07-27 Industrial Technology Research Institute Method for forming electrically conductive bumps and devices formed
US6462575B1 (en) * 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
US6710456B1 (en) 2000-08-31 2004-03-23 Micron Technology, Inc. Composite interposer for BGA packages
JP4174174B2 (en) 2000-09-19 2008-10-29 株式会社ルネサステクノロジ Semiconductor device, manufacturing method thereof, and semiconductor device mounting structure
US6433427B1 (en) * 2001-01-16 2002-08-13 Industrial Technology Research Institute Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication
US6388322B1 (en) * 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
US6643739B2 (en) 2001-03-13 2003-11-04 Koninklijke Philips Electronics N.V. Cache way prediction based on instruction base register
US7148566B2 (en) * 2001-03-26 2006-12-12 International Business Machines Corporation Method and structure for an organic package with improved BGA life
US20050097727A1 (en) * 2001-03-28 2005-05-12 Tomoo Iijima Multi-layer wiring board, method for producing multi-layer wiring board, polishing machine for multi-layer wiring board, and metal sheet for producing wiring board
US6767819B2 (en) 2001-09-12 2004-07-27 Dow Corning Corporation Apparatus with compliant electrical terminals, and methods for forming same
US6780272B2 (en) * 2001-09-17 2004-08-24 3M Innovative Properties Company Method for producing web for use in making shaped elastic ears disposable absorbent article diapers
JP4338340B2 (en) * 2001-09-20 2009-10-07 株式会社高純度化学研究所 Method for producing high purity lanthanum isopropoxide
TW517360B (en) 2001-12-19 2003-01-11 Ind Tech Res Inst Enhanced type wafer level package structure and its manufacture method
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US6940177B2 (en) 2002-05-16 2005-09-06 Dow Corning Corporation Semiconductor package and method of preparing same
DE10223738B4 (en) 2002-05-28 2007-09-27 Qimonda Ag Method for connecting integrated circuits
TWI223363B (en) 2003-11-06 2004-11-01 Ind Tech Res Inst Bonding structure with compliant bumps
US7294929B2 (en) * 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure

Patent Citations (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001870A (en) 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
US4365264A (en) 1978-07-31 1982-12-21 Hitachi, Ltd. Semiconductor device with high density low temperature deposited Siw Nx Hy Oz passivating layer
JPS57121255A (en) 1981-01-21 1982-07-28 Hitachi Ltd Electric circuit element with metallic bump and mounting method of the seme
US4618878A (en) 1983-06-18 1986-10-21 Kabushiki Kaisha Toshiba Semiconductor device having a multilayer wiring structure using a polyimide resin
US4902606A (en) 1985-12-20 1990-02-20 Hughes Aircraft Company Compressive pedestal for microminiature connections
US4885126A (en) 1986-10-17 1989-12-05 Polonio John D Interconnection mechanisms for electronic components
US4813129A (en) * 1987-06-19 1989-03-21 Hewlett-Packard Company Interconnect structure for PC boards and integrated circuits
US5070297A (en) 1990-06-04 1991-12-03 Texas Instruments Incorporated Full wafer integrated circuit testing device
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5072520A (en) 1990-10-23 1991-12-17 Rogers Corporation Method of manufacturing an interconnect device having coplanar contact bumps
US5180311A (en) 1991-01-22 1993-01-19 Hughes Aircraft Company Resilient interconnection bridge
US5430329A (en) 1991-01-29 1995-07-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with bonding pad electrode
JPH04280458A (en) 1991-03-08 1992-10-06 Hitachi Ltd Semiconductor integrated circuit device, and its manufacture and mounting structure
JPH05251455A (en) 1992-03-04 1993-09-28 Toshiba Corp Semiconductor device
US5604380A (en) 1993-10-07 1997-02-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a multilayer interconnection structure
US5666270A (en) 1993-10-18 1997-09-09 Fujitsu Limited Bump electrode, semiconductor integrated circuit device using the same, multi-chip module having the semiconductor integrated circuit devices and method for producing semicondutcor device having the bump electrode
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US5508228A (en) 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5734547A (en) 1995-02-13 1998-03-31 Iversen; Arthur H. Power switchgear
US5777379A (en) 1995-08-18 1998-07-07 Tessera, Inc. Semiconductor assemblies with reinforced peripheral regions
US5874782A (en) 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
US5749997A (en) 1995-12-27 1998-05-12 Industrial Technology Research Institute Composite bump tape automated bonding method and bonded structure
US6147401A (en) 1996-12-13 2000-11-14 Tessera, Inc. Compliant multichip package
US6043563A (en) 1997-05-06 2000-03-28 Formfactor, Inc. Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals
WO1998052225A1 (en) 1997-05-13 1998-11-19 Chipscale, Inc. An electronic component package with posts on the active surface
WO1999005895A1 (en) 1997-07-22 1999-02-04 Gerhard Naundorf Conducting path structures situated on a non-conductive support material, especially fine conducting path structures and method for producing same
US5937758A (en) 1997-11-26 1999-08-17 Motorola, Inc. Micro-contact printing stamp
US6337445B1 (en) 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US20020089058A1 (en) 1999-06-17 2002-07-11 Harry Hedler Electronic component with flexible bonding pads and method of producing such a component
US6638870B2 (en) 2002-01-10 2003-10-28 Infineon Technologies Ag Forming a structure on a wafer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
* "Methods of Testing Chips and Joining Chips to Substrates," 2244 Research Disclosure, Feb. 1991, Elmsworth, GB, 32290.

Cited By (116)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100035382A1 (en) * 1995-10-31 2010-02-11 Tessera, Inc. Methods of making compliant semiconductor chip packages
US7872344B2 (en) 1995-10-31 2011-01-18 Tessera, Inc. Microelectronic assemblies having compliant layers
US8338925B2 (en) 1995-10-31 2012-12-25 Tessera, Inc. Microelectronic assemblies having compliant layers
US8558386B2 (en) 1995-10-31 2013-10-15 Tessera, Inc. Methods of making compliant semiconductor chip packages
US7019410B1 (en) * 1999-12-21 2006-03-28 Micron Technology, Inc. Die attach material for TBGA or flexible circuitry
US20060197233A1 (en) * 1999-12-21 2006-09-07 Tongbi Jiang Die attach material for TBGA or flexible circuitry
US20060103032A1 (en) * 1999-12-21 2006-05-18 Tongbi Jiang Die attach material for TBGA or flexible circuitry
US8674815B1 (en) 2000-03-15 2014-03-18 Logitech Europe S.A. Configuration method for a remote
US8854192B1 (en) 2000-03-15 2014-10-07 Logitech Europe S.A. Configuration method for a remote
US8674814B2 (en) 2000-03-15 2014-03-18 Logitech Europe S.A. State-based remote control system
US20080198059A1 (en) * 2000-03-15 2008-08-21 Logitech Europe S.A. Online remote control configuration system
US8653950B2 (en) 2000-03-15 2014-02-18 Logitech Europe S.A. State-based remote control system
US8742905B2 (en) 2000-03-15 2014-06-03 Logitech Europe S.A. Easy to use and intuitive user interface for a remote control
US20080062034A1 (en) * 2000-03-15 2008-03-13 Logitech Europe S.A. Online remote control configuration system
US8797149B2 (en) 2000-03-15 2014-08-05 Logitech Europe S.A. State-based control systems and methods
US8531276B2 (en) 2000-03-15 2013-09-10 Logitech Europe S.A. State-based remote control system
US8704643B2 (en) 2000-03-15 2014-04-22 Logitech Europe S.A. Convenient and easy to use button layout for a remote control
US20060192855A1 (en) * 2000-03-15 2006-08-31 Harris Glen M State-based remote control system
US20050052423A1 (en) * 2000-03-15 2005-03-10 Harris Glen Mclean Online remote control configuration system
US20080036642A1 (en) * 2000-03-15 2008-02-14 Logitech Europe S.A. Remote Control Multimedia Content Listing System
US8330582B2 (en) 2000-03-15 2012-12-11 Logitech Europe S.A. Online remote control configuration system
US7612685B2 (en) 2000-03-15 2009-11-03 Logitech Europe S.A. Online remote control configuration system
US20080302582A1 (en) * 2000-03-15 2008-12-11 Logitech Europe S.A. Easy to Use and Intuitive User Interface for a Remote Control
US8026789B2 (en) 2000-03-15 2011-09-27 Logitech Europe S.A. State-based remote control system
US7944370B1 (en) 2000-03-15 2011-05-17 Logitech Europe S.A. Configuration method for a remote control via model number entry for a controlled device
US20090224955A1 (en) * 2000-03-15 2009-09-10 Logitech Europe S,A, Convenient and Easy to Use Button Layout for a Remote Control
US20110133976A1 (en) * 2000-03-15 2011-06-09 Logitech Europe S.A. State-based remote control system
US20090057919A1 (en) * 2000-05-19 2009-03-05 Megica Corporation Multiple chips bonded to packaging structure with low noise and multiple selectable functions
US8148806B2 (en) 2000-05-19 2012-04-03 Megica Corporation Multiple chips bonded to packaging structure with low noise and multiple selectable functions
US8426982B2 (en) 2001-03-30 2013-04-23 Megica Corporation Structure and manufacturing method of chip scale package
US9018774B2 (en) 2001-03-30 2015-04-28 Qualcomm Incorporated Chip package
US20090289346A1 (en) * 2001-03-30 2009-11-26 Megica Corporation Structure and manufacturing method of chip scale package
US20090008778A1 (en) * 2001-03-30 2009-01-08 Megica Corporation Structure and manufactruing method of chip scale package
US20080315424A1 (en) * 2001-03-30 2008-12-25 Megica Corporation Structure and manufactruing method of chip scale package
US8912666B2 (en) 2001-03-30 2014-12-16 Qualcomm Incorporated Structure and manufacturing method of chip scale package
US8748227B2 (en) 2001-03-30 2014-06-10 Megit Acquisition Corp. Method of fabricating chip package
US7919873B2 (en) 2001-09-17 2011-04-05 Megica Corporation Structure of high performance combo chip and processing method
US7960212B2 (en) 2001-09-17 2011-06-14 Megica Corporation Structure of high performance combo chip and processing method
US7960842B2 (en) 2001-09-17 2011-06-14 Megica Corporation Structure of high performance combo chip and processing method
US20090057901A1 (en) * 2001-09-17 2009-03-05 Megica Corporation Structure of high performance combo chip and processing method
US8124446B2 (en) 2001-09-17 2012-02-28 Megica Corporation Structure of high performance combo chip and processing method
US8138617B2 (en) 2001-10-08 2012-03-20 Round Rock Research, Llc Apparatus and method for packaging circuits
US20100140794A1 (en) * 2001-10-08 2010-06-10 Chia Yong Poo Apparatus and method for packaging circuits
US8115306B2 (en) * 2001-10-08 2012-02-14 Round Rock Research, Llc Apparatus and method for packaging circuits
US20070232053A1 (en) * 2002-10-24 2007-10-04 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
US7960272B2 (en) 2002-10-24 2011-06-14 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
US8334588B2 (en) 2002-10-24 2012-12-18 Megica Corporation Circuit component with conductive layer structure
US20110204522A1 (en) * 2002-10-24 2011-08-25 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
US20060258183A1 (en) * 2003-04-11 2006-11-16 Neoconix, Inc. Electrical connector on a flexible carrier
US20070141863A1 (en) * 2003-04-11 2007-06-21 Williams John D Contact grid array system
US20070259539A1 (en) * 2003-04-11 2007-11-08 Brown Dirk D Method and system for batch manufacturing of spring elements
US20070054515A1 (en) * 2003-04-11 2007-03-08 Williams John D Method for fabricating a contact grid array
US20100167561A1 (en) * 2003-04-11 2010-07-01 Neoconix, Inc. Structure and process for a contact grid array formed in a circuitized substrate
US20050164527A1 (en) * 2003-04-11 2005-07-28 Radza Eric M. Method and system for batch forming spring elements in three dimensions
US7891988B2 (en) 2003-04-11 2011-02-22 Neoconix, Inc. System and method for connecting flat flex cable with an integrated circuit, such as a camera module
US20060276059A1 (en) * 2003-04-11 2006-12-07 Neoconix Inc. System for connecting a camera module, or like device, using flat flex cables
US20100075514A1 (en) * 2003-04-11 2010-03-25 Neoconix, Inc. Method of making electrical connector on a flexible carrier
US7758351B2 (en) 2003-04-11 2010-07-20 Neoconix, Inc. Method and system for batch manufacturing of spring elements
US20060189179A1 (en) * 2003-04-11 2006-08-24 Neoconix Inc. Flat flex cable (FFC) with embedded spring contacts for connecting to a PCB or like electronic device
US8584353B2 (en) 2003-04-11 2013-11-19 Neoconix, Inc. Method for fabricating a contact grid array
US20100055941A1 (en) * 2003-04-11 2010-03-04 Neoconix, Inc. System and method for connecting flat flx cable with an integrated circuit, such as a camera module
US7056131B1 (en) 2003-04-11 2006-06-06 Neoconix, Inc. Contact grid array system
US20070218710A1 (en) * 2003-06-11 2007-09-20 Brown Dirk D Structure and process for a contact grid array formed in a circuitized substrate
US20040252477A1 (en) * 2003-06-11 2004-12-16 Brown Dirk D. Contact grid array formed on a printed circuit board
US7115975B2 (en) * 2003-09-05 2006-10-03 Canon Kabushiki Kaisha Semiconductor device, process of producing semiconductor device, and ink jet recording head
US20050093128A1 (en) * 2003-09-05 2005-05-05 Canon Kabushiki Kaisha Semiconductor device, process of producing semiconductor device, and ink jet recording head
US20050120553A1 (en) * 2003-12-08 2005-06-09 Brown Dirk D. Method for forming MEMS grid array connector
US7989945B2 (en) 2003-12-08 2011-08-02 Neoconix, Inc. Spring connector for making electrical contact at semiconductor scales
US20050124181A1 (en) * 2003-12-08 2005-06-09 Brown Dirk D. Connector for making electrical contact at semiconductor scales
US20070275572A1 (en) * 2003-12-08 2007-11-29 Williams John D Connector for making electrical contact at semiconductor scales
US20060211296A1 (en) * 2004-03-19 2006-09-21 Dittmann Larry E Electrical connector in a flexible host
US7645147B2 (en) 2004-03-19 2010-01-12 Neoconix, Inc. Electrical connector having a flexible sheet and one or more conductive connectors
US20090193654A1 (en) * 2004-03-19 2009-08-06 Dittmann Larry E Contact and method for making same
US20050208787A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Interposer with compliant pins
US20050208788A1 (en) * 2004-03-19 2005-09-22 Dittmann Larry E Electrical connector in a flexible host
US20050205988A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Die package with higher useable die contact pad area
US20050208786A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Interposer and method for making same
US20050227510A1 (en) * 2004-04-09 2005-10-13 Brown Dirk D Small array contact with precision working range
US20060000642A1 (en) * 2004-07-01 2006-01-05 Epic Technology Inc. Interposer with compliant pins
US20060258182A1 (en) * 2004-07-20 2006-11-16 Dittmann Larry E Interposer with compliant pins
US20060194365A1 (en) * 2005-02-25 2006-08-31 Tessera, Inc. Microelectronic assemblies having compliancy
US7999379B2 (en) 2005-02-25 2011-08-16 Tessera, Inc. Microelectronic assemblies having compliancy
US8509400B2 (en) 2005-04-20 2013-08-13 Logitech Europe S.A. System and method for adaptive programming of a remote control
US20070037522A1 (en) * 2005-04-20 2007-02-15 Logitech Europe S.A. System and method for adaptive programming of a remote control
US9207652B2 (en) 2005-04-20 2015-12-08 Logitech Europe S.A. System and method for adaptive programming of a remote control
US20070050738A1 (en) * 2005-08-31 2007-03-01 Dittmann Larry E Customer designed interposer
US8115309B2 (en) * 2005-11-07 2012-02-14 Seiko Epson Corporation Semiconductor device
US7777332B2 (en) * 2005-11-07 2010-08-17 Seiko Epson Corporation Semiconductor device
US20070108607A1 (en) * 2005-11-07 2007-05-17 Seiko Epson Corporation Semiconductor device
US20100252925A1 (en) * 2005-11-07 2010-10-07 Seiko Epson Corporation Semiconductor device
US20080134502A1 (en) * 2005-12-12 2008-06-12 Dittmann Larry E Connector having staggered contact architecture for enhanced working range
US20070134949A1 (en) * 2005-12-12 2007-06-14 Dittmann Larry E Connector having staggered contact architecture for enhanced working range
US7534652B2 (en) 2005-12-27 2009-05-19 Tessera, Inc. Microelectronic elements with compliant terminal mountings and methods for making the same
US20070145550A1 (en) * 2005-12-27 2007-06-28 Tessera, Inc. Microelectronic elements with compliant terminal mountings and methods for making the same
US7446405B2 (en) 2006-02-08 2008-11-04 Hynix Semiconductor Inc. Wafer level chip scale package (WLCSP) with high reliability against thermal stress
US20070182022A1 (en) * 2006-02-08 2007-08-09 Jong Hoon Kim Wafer level chip scale package (WLCSP) with high reliability against thermal stress
US20070233731A1 (en) * 2006-02-22 2007-10-04 Logitech Europe S.A. System and method for configuring media systems
US20070267730A1 (en) * 2006-05-16 2007-11-22 Tessera, Inc. Wafer level semiconductor chip packages and methods of making the same
WO2007133806A3 (en) * 2006-05-16 2008-04-24 Tessera Inc Wafer level semiconductor chip packages and methods of making the same
WO2007133806A2 (en) * 2006-05-16 2007-11-22 Tessera, Inc. Wafer level semiconductor chip packages and methods of making the same
US8759973B2 (en) 2006-12-20 2014-06-24 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
US8115308B2 (en) 2006-12-20 2012-02-14 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
US20080150121A1 (en) * 2006-12-20 2008-06-26 Tessera Technologies Hungary Kft. Microelectronic assemblies having compliancy and methods therefor
US7749886B2 (en) 2006-12-20 2010-07-06 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
US20080284011A1 (en) * 2007-05-18 2008-11-20 Taiwan Tft Lcd Association Bump structure
US7960845B2 (en) * 2008-01-03 2011-06-14 Linear Technology Corporation Flexible contactless wire bonding structure and methodology for semiconductor device
US8269355B2 (en) 2008-01-03 2012-09-18 Linear Technology Corporation Flexible contactless wire bonding structure and methodology for semiconductor device
US20090174043A1 (en) * 2008-01-03 2009-07-09 Linear Technology Corporation Flexible contactless wire bonding structure and methodology for semiconductor device
US20110063855A1 (en) * 2008-05-30 2011-03-17 Koninklijke Philips Electronics N.V. Round illumination device
US7902665B2 (en) 2008-09-02 2011-03-08 Linear Technology Corporation Semiconductor device having a suspended isolating interconnect
US20100052120A1 (en) * 2008-09-02 2010-03-04 Linear Technology Corporation Semiconductor device having a suspended isolating interconnect
US8508401B1 (en) 2010-08-31 2013-08-13 Logitech Europe S.A. Delay fixing for command codes in a remote control system
US8918544B2 (en) 2011-03-31 2014-12-23 Logitech Europe S.A. Apparatus and method for configuration and operation of a remote-control system
US9239837B2 (en) 2011-04-29 2016-01-19 Logitech Europe S.A. Remote control system for connected devices
US8641428B2 (en) 2011-12-02 2014-02-04 Neoconix, Inc. Electrical connector and method of making it
US9680273B2 (en) 2013-03-15 2017-06-13 Neoconix, Inc Electrical connector with electrical contacts protected by a layer of compressible material and method of making it

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US20110095441A1 (en) 2011-04-28
US7408260B2 (en) 2008-08-05
US7872344B2 (en) 2011-01-18
US8338925B2 (en) 2012-12-25
US20040227225A1 (en) 2004-11-18
US6284563B1 (en) 2001-09-04
US6465878B2 (en) 2002-10-15
US20060237836A1 (en) 2006-10-26
US6847107B2 (en) 2005-01-25
US20060261476A1 (en) 2006-11-23
US7112879B2 (en) 2006-09-26
US20020195685A1 (en) 2002-12-26
US20010007375A1 (en) 2001-07-12
US20020100961A1 (en) 2002-08-01

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