US5652583A - Apparatus for encoding variable-length codes and segmenting variable-length codewords thereof - Google Patents
Apparatus for encoding variable-length codes and segmenting variable-length codewords thereof Download PDFInfo
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- US5652583A US5652583A US08/556,530 US55653095A US5652583A US 5652583 A US5652583 A US 5652583A US 55653095 A US55653095 A US 55653095A US 5652583 A US5652583 A US 5652583A
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- barrel shifter
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- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- 238000013507 mapping Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000013144 data compression Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
- H03M7/42—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code using table look-up for the coding or decoding process, e.g. using read-only memory
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
Definitions
- the present invention relates to an apparatus for encoding variable length codes (VLCs) represented by variable-length codewords and their lengths, and segmenting variable-length codewords of the VLCs into fixed-length segments for the transmission thereof; and, more particularly, to a VLC encoding and segmenting apparatus which is capable of processing the length part of the VLCs in an encoded form.
- VLCs variable length codes
- Variable-length coding is a technique often used for lossless data compression. This technique is used to convert fixed-length data to variable-length codewords based on the statistical occurrences of the data. Each length of the variable-length codewords is chosen in such a manner that shorter codewords are used to represent more frequently occurring data and longer codewords to represent less frequently occurring data. By properly assigning the variable-length codewords to a library of all possible source data, the average word length of the variable-length codewords becomes shorter than that of the source data, thereby rendering it possible to achieve data compression.
- the encoding process of the VLCs represented by variable-length codewords and their lengths, and the segmenting process of the variable-length codewords of the VLCs for the transmission can be implemented by using a lookup table in which the variable-length codewords and their length data are stored as the contents thereof.
- a lookup table based VLC encoding and segmenting apparatus is disclosed in, e.g., Shaw-Min Lei et al., "An Entropy Coding System for Digital HDTV Applications", IEEE Transactions on Circuits and Systems for Video Technology, 1, No. 1, pp. 147-154 (March 1991).
- Some of the major circuit components of the VLC encoding and segmenting apparatus include a PLA (Programmable Logic Array) and three barrel shifters.
- the PLA is a lookup table which maps the input data to variable-length codewords to produce the VLCs, i.e., the variable-length codewords and their lengths.
- a first barrel shifter concatenates these variable-length codewords together based on each length of the variable-length codewords to provide a chain of variable-length codewords; and a second barrel shifter segments the chain of variable-length codewords into n-bit words for output; and a third barrel shifter accumulates each length of the variable-length codewords to generate a control signal which indicates whether the output of the VLC encoding and segmenting apparatus is available.
- the information on the lengths of the variable-length codewords produced from the PLA is supplied to the first and the third barrel shifters in a decoded form which means the position of the only 1 indicates the length. That is, if the maximum length of a variable-length codeword is sixteen, a set of 16-bit lines must be employed to represent each length of the variable-length codewords.
- the decoded form of the length of the variable-length codewords enables the third barrel shifter to rapidly produce a control signal of the second barrel shifter.
- an apparatus for encoding VLCs represented by variable-length codewords and their lengths, and segmenting variable-length codewords of the VLCs into n-bit words for the transmission thereof, wherein the lengths of the variable-length codewrods are processed in an encoded form comprising: a first register for storing a series of source codes and producing each of the source codes in response to a enable signal which is associated with each input time of the source codes; a lookup table for mapping each of the source codes into each of the VLCs to produce each of the variable-length codewords and its length; a second register for storing each of the variable-length codewords, and, in response to the enable signal, for producing each stored variable-length codeword; a third register for storing each length of the variable-length codewords, and, in response to the enable signal, producing each stored length; a first barrel shifter, in response to a first control signal representative of the length of a present input variable-length codeword
- FIG. 1 represents a block diagram of a VLC encoding and segmenting apparatus in accordance with the present invention
- FIG. 2 provides an explanatory diagram for illustrating the operation of the VLC encoding and segmenting apparatus shown in FIG. 1;
- FIG. 3 schematically shows a first barrel shifter for concatenating variable-length codewords
- FIG. 4 schematically illustrates a second barrel shifter for segmenting a chain of concatenated variable-length codewords.
- VLCs variable length codes
- a series of source codes is inputted to a first register 10.
- each of the source codes consists of a maximum run-length of 63 and a level ranging from -2047 to 2047.
- the term ⁇ run-length ⁇ means the number of successive runs with a zero value, and the non-zero value following the successive zeros is called a level.
- the first register 10 sequentially stores the source codes which are derived by a RLC (Run-Length Coding) encoder and outputs them to a lookup table 20 in response to a enable signal which is associated with each input time of the source codes.
- RLC Raster-Length Coding
- the lookup table 20 maps each of the source codes into a VLC to produce each variable-length codeword and its length corresponding to each of the source codes onto leads 27 and 29, respectively.
- the lookup table 20 is implemented by a programmable logic array (PLA).
- PPA programmable logic array
- the lookup table 20 shown in FIG. 1 consists of an uncoded word table AND-plane 22, a codeword table OR-plane 24 and a code length table OR-plane 26.
- the lookup table 20 is described in Shaw-Min Lei et al., supra.
- variable-length codeword since the length of the variable-length codeword is processed in an encoded form, if a variable-length codeword has a maximum of 16-bit length, the length can be represented using 5 bits because the value of a codeword length ranges from 1 to 16.
- Each of the variable-length codewords from the codeword table 24 and its length from the code length table 26 are provided to a second register 28 and a third register 30 via the lead 27 and the lead 29, respectively.
- the second and the third registers 28 and 30 sequentially store each of the variable-length codewords from the codeword table 24 and each corresponding length of the variable-length codewords from the length table 26, respectively; and output each of the stored variable-length codewords and each of the stored lengths in response to the above-described enable signal, respectively.
- the 16-bits stored in the register 28 are inputted to a first and a second barrel shifters 32 and 40 over parallel leads 25.
- another 16-bits in a fourth register 34 are also inputted to the first and the second barrel shifters 32 and 40 over parallel leads 35.
- the first barrel shifter 32 is responsive to a codeword length signal on a lead 31 generated by the third register 30, to form a 16-bit window on its 32-bit inputs.
- the 16-bit window is shiftable across the 32-bit inputs on leads 25 and 35 and its position is directly determined by the codeword length signal inputted through the lead 31.
- the codeword length signal indicates a shift of the 16-bit window between zero and fifteen. If each bit is numbered as 0, 1, 2, . . .
- a codeword length signal of "M" indicates that the 16-bit window encompasses the Mth through (M+15)th bit on leads 25 and 35.
- the first barrel shifter 32 produces a 16 bit-string to the fourth register 34 via a lead 33.
- the fourth register 34 stores the bit-string produced by the first barrel shifter 32 and, in response to the enable signal, provides the stored bit-string to the inputs of the first and the second barrel shifters 32 and 40.
- each of the lengths stored in the third register 30 is sequentially inputted to an adder 36 in response to the enable signal.
- the adder 36 serves to add the length of the present variable-length codeword to an added length stored in a fifth register 38.
- the fifth register 38 if a newly added length from the adder 36 does not exceed a predetermined positive integer value which represents the bit number of a segment for transmission, i.e., 16, stores the newly added length at the fifth register 38. Otherwise, the fifth register 38 stores a residue representative of the number of exceeding bits after the adding as the added length; and produces an output available signal which represents whether the bit-string stored in the sixth register 42 is an available n-bit word and, in response to the enable signal, produces each stored added length to the second barrel shifter 40.
- the second barrel shifter 40 is responsive to the value of the added length stored in the fifth register 38 on a lead 39, to form a 16-bit window on its 32-bit inputs which are provided by both the leads 25 and 35.
- the 16-bit window is shiftable across the 32-bit inputs on leads 25 and 35 and its position is directly determined by the added length signal.
- the added length signal indicates a shift of the 16-bit window between zero and fifteen.
- the 16 bit-window of the second barrel shifter 40 encompasses the (16-N)th through (31-N)th bit on leads 25 and 35.
- the second barrel shifter 40 produces a 16-bit string to a sixth register 42 via a lead 41.
- the sixth register 42 stores the 16-bit window output bit-string from the second barrel shifter 40 and produces the stored bits to a video buffer (not shown) in response to the enable signal.
- a video buffer not shown
- the bit-string from the sixth register 42 will be stored in the buffer which stores only available 16-bit words for the transmission thereof.
- VLC encoding and segmenting apparatus in FIG. 1 may be more readily understood with reference to an example shown in a tabular form in FIG. 2. It is assumed that the maximum length of the variable-length codewords is 8 bits.
- the first column of FIG. 2 is made for each input order of following registers: the second register 28 for the variable-length codewords from the codeword table 24; the third register 30 for each corresponding length of the variable-length codewords stored in the second register 28; the fourth register 34 for storing the output segment of the first barrel shifter 32; the fifth register 38 for storing an added length from the adder 36; and the sixth register 42 for storing the output segment of the second barrel shifter 40.
- the last column of FIG. 2 is built for the output available signal which represents whether the output segment of the second barrel shifter 40 is available or not.
- the six numbers of the variable-length codewords are sequentially produced as shown in the second column, and each length corresponding to each of the variable-length codewords is stored as shown in the third column.
- the marks of "X" contained in the second column represent entirely meaningless bits out of all bits of a segment provided from the codeword table 24.
- FIG. 3 there is schematically shown the operation of the first barrel shifter 32 for concatenating variable-length codewords, for example, in case of input order 2. As shown in FIG.
- M codeword length signal
- the position of the 8-bit window is determined by shifting the window by M bits from the lefthand side of the 16-bit inputs.
- the selection of M bits out of the first segment "111X XXXX" from the left-hand side and another selection of (8-M) bits out of the second segment "1000 0011" from the right-hand side remove the five meaningless bits of the first segment "111X XXXX", thereby to concatenate the variable-length codewords.
- the first barrel shifter 32 After forming the window, the first barrel shifter 32 produces an 8-bit window output segment "0001 1111" to the fourth register 34 via the lead 33.
- the fifth register 38 stores an added length or a residue of an added length subtracted by eight.
- the adder 36 serves to add the length of the present variable-length codeword stored in the third register 30 to the previous added length stored in the fifth register 38.
- the value "1" in the input order 5 of the fifth register of FIG. 2 is a residue after summing and subtracting operations of two values "4" and "5" in the input order 4 of the third and the fifth registers: the value "4" is the length of the present variable-length codeword stored in the third register 30 and the value "5" is the previous added codeword length stored in the fifth register 38.
- FIG. 2 there are depicted five number of output segments of the second barrel shifter 40 which serve to segment a bit-string which consists of the concatenated variable-length codewords from the first barrel shifter 32 and the present variable-length codeword from the second register 28.
- FIG. 4 there is schematically shown the operation of the second barrel shifter 40 for segmenting the bit-string, for example, in case of input order 4. As shown in FIG.
- the position of the 8-bit window is determined by shifting the window by (8-N) bits from the lefthand of the 16-bit inputs.
- the output-available signal of "1" is produced whenever the added length from the adder 36 exceeds 8, thereby to indicate whether the bit-string stored in the sixth register 42 is an available n-bit word.
Abstract
Description
Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR95-19183 | 1995-06-30 | ||
KR1019950019183A KR0180169B1 (en) | 1995-06-30 | 1995-06-30 | A variable length coder |
Publications (1)
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US5652583A true US5652583A (en) | 1997-07-29 |
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US08/556,530 Expired - Lifetime US5652583A (en) | 1995-06-30 | 1995-11-13 | Apparatus for encoding variable-length codes and segmenting variable-length codewords thereof |
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US (1) | US5652583A (en) |
JP (1) | JPH0916373A (en) |
KR (1) | KR0180169B1 (en) |
CN (1) | CN1144371C (en) |
Cited By (24)
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---|---|---|---|---|
US5913229A (en) * | 1995-12-13 | 1999-06-15 | Samsung Electronics Co., Ltd. | Buffer memory controller storing and extracting data of varying bit lengths |
WO2001016758A2 (en) * | 1999-09-01 | 2001-03-08 | Intel Corporation | Double shift instruction for micro engine used in multithreaded parallel processor architecture |
US6272257B1 (en) * | 1997-04-30 | 2001-08-07 | Canon Kabushiki Kaisha | Decoder of variable length codes |
EP1158807A2 (en) * | 2000-05-18 | 2001-11-28 | Sony Corporation | Data stream conversion apparatus and method, variable length coded data stream generation apparatus and method, and camera system |
US20020056037A1 (en) * | 2000-08-31 | 2002-05-09 | Gilbert Wolrich | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US6480125B2 (en) * | 2000-06-09 | 2002-11-12 | Seagate Technology Llc | Method and apparatus for efficient encoding of large data words at high code rates |
US6501398B2 (en) * | 2000-03-24 | 2002-12-31 | Matsushita Electric Industrial Co., Ltd. | Variable-length code decoder using barrel shifters and a look-up table |
EP1278308A2 (en) * | 2001-07-19 | 2003-01-22 | Vistar Telecommunications Inc. | Forward link text compression in satellite messaging |
US20030105899A1 (en) * | 2001-08-27 | 2003-06-05 | Rosenbluth Mark B. | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
US20030145155A1 (en) * | 2002-01-25 | 2003-07-31 | Gilbert Wolrich | Data transfer mechanism |
US20040034743A1 (en) * | 2002-08-13 | 2004-02-19 | Gilbert Wolrich | Free list and ring data structure management |
US6707397B1 (en) * | 2002-10-24 | 2004-03-16 | Apple Computer, Inc. | Methods and apparatus for variable length codeword concatenation |
US6707398B1 (en) * | 2002-10-24 | 2004-03-16 | Apple Computer, Inc. | Methods and apparatuses for packing bitstreams |
US20040205747A1 (en) * | 2000-12-21 | 2004-10-14 | Debra Bernstein | Breakpoint for parallel hardware threads in multithreaded processor |
US20050018773A1 (en) * | 2001-11-21 | 2005-01-27 | Van Der Vleuten Renatus Josephus | Bit plane compression method |
DE19958962B4 (en) * | 1998-12-30 | 2007-03-01 | Lg-Nortel Co. Ltd. | Variable length coder, coding method and bit packing method |
US7191309B1 (en) * | 1999-09-01 | 2007-03-13 | Intel Corporation | Double shift instruction for micro engine used in multithreaded parallel processor architecture |
US7216204B2 (en) | 2001-08-27 | 2007-05-08 | Intel Corporation | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
US7246197B2 (en) | 2001-08-27 | 2007-07-17 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
US7418571B2 (en) | 2003-01-10 | 2008-08-26 | Intel Corporation | Memory interleaving |
US7437724B2 (en) | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
US7487505B2 (en) | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
US7991983B2 (en) | 1999-09-01 | 2011-08-02 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
US11456755B1 (en) * | 2021-05-10 | 2022-09-27 | Neuchips Corporation | Look-up table compression method and look-up table reading method for computation equipment and its host and device |
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KR100975062B1 (en) * | 2003-12-27 | 2010-08-11 | 삼성전자주식회사 | A Variable Length Coding apparatus and a Variable Length Coding method |
CN101534125B (en) * | 2009-04-24 | 2012-07-18 | 北京空间机电研究所 | Ultra-long data variable length encoding synthetic system |
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- 1995-11-13 US US08/556,530 patent/US5652583A/en not_active Expired - Lifetime
- 1995-11-16 JP JP7298358A patent/JPH0916373A/en active Pending
- 1995-11-21 CN CNB951175211A patent/CN1144371C/en not_active Expired - Lifetime
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US5913229A (en) * | 1995-12-13 | 1999-06-15 | Samsung Electronics Co., Ltd. | Buffer memory controller storing and extracting data of varying bit lengths |
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EP1158807A2 (en) * | 2000-05-18 | 2001-11-28 | Sony Corporation | Data stream conversion apparatus and method, variable length coded data stream generation apparatus and method, and camera system |
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EP1278308A2 (en) * | 2001-07-19 | 2003-01-22 | Vistar Telecommunications Inc. | Forward link text compression in satellite messaging |
US20030164781A1 (en) * | 2001-07-19 | 2003-09-04 | Hans Haugli | Forward link text compression in satellite messaging |
EP1278308A3 (en) * | 2001-07-19 | 2003-03-26 | Vistar Telecommunications Inc. | Forward link text compression in satellite messaging |
US7230735B2 (en) | 2001-07-19 | 2007-06-12 | Transcore Link Logistics Corp. | Forward link text compression in satellite messaging |
US7246197B2 (en) | 2001-08-27 | 2007-07-17 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
US7216204B2 (en) | 2001-08-27 | 2007-05-08 | Intel Corporation | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
US7225281B2 (en) | 2001-08-27 | 2007-05-29 | Intel Corporation | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
US20030105899A1 (en) * | 2001-08-27 | 2003-06-05 | Rosenbluth Mark B. | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
US7487505B2 (en) | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
US20050018773A1 (en) * | 2001-11-21 | 2005-01-27 | Van Der Vleuten Renatus Josephus | Bit plane compression method |
US20030145155A1 (en) * | 2002-01-25 | 2003-07-31 | Gilbert Wolrich | Data transfer mechanism |
US7610451B2 (en) | 2002-01-25 | 2009-10-27 | Intel Corporation | Data transfer mechanism using unidirectional pull bus and push bus |
US7437724B2 (en) | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
US20040034743A1 (en) * | 2002-08-13 | 2004-02-19 | Gilbert Wolrich | Free list and ring data structure management |
US7337275B2 (en) | 2002-08-13 | 2008-02-26 | Intel Corporation | Free list and ring data structure management |
US6707397B1 (en) * | 2002-10-24 | 2004-03-16 | Apple Computer, Inc. | Methods and apparatus for variable length codeword concatenation |
US6707398B1 (en) * | 2002-10-24 | 2004-03-16 | Apple Computer, Inc. | Methods and apparatuses for packing bitstreams |
US7418571B2 (en) | 2003-01-10 | 2008-08-26 | Intel Corporation | Memory interleaving |
US11456755B1 (en) * | 2021-05-10 | 2022-09-27 | Neuchips Corporation | Look-up table compression method and look-up table reading method for computation equipment and its host and device |
Also Published As
Publication number | Publication date |
---|---|
KR0180169B1 (en) | 1999-05-01 |
JPH0916373A (en) | 1997-01-17 |
KR970004873A (en) | 1997-01-29 |
CN1144371C (en) | 2004-03-31 |
CN1139861A (en) | 1997-01-08 |
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