US5402358A - Method and structure for the automated design of analog integrated circuits - Google Patents
Method and structure for the automated design of analog integrated circuits Download PDFInfo
- Publication number
- US5402358A US5402358A US08/147,465 US14746593A US5402358A US 5402358 A US5402358 A US 5402358A US 14746593 A US14746593 A US 14746593A US 5402358 A US5402358 A US 5402358A
- Authority
- US
- United States
- Prior art keywords
- circuit
- specifications
- device module
- script
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/147,465 US5402358A (en) | 1990-05-14 | 1993-10-29 | Method and structure for the automated design of analog integrated circuits |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US52345390A | 1990-05-14 | 1990-05-14 | |
US93359292A | 1992-08-20 | 1992-08-20 | |
US08/147,465 US5402358A (en) | 1990-05-14 | 1993-10-29 | Method and structure for the automated design of analog integrated circuits |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US93359292A Continuation | 1990-05-14 | 1992-08-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
US5402358A true US5402358A (en) | 1995-03-28 |
Family
ID=27061152
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/147,465 Expired - Lifetime US5402358A (en) | 1990-05-14 | 1993-10-29 | Method and structure for the automated design of analog integrated circuits |
Country Status (1)
Country | Link |
---|---|
US (1) | US5402358A (en) |
Cited By (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5633807A (en) * | 1995-05-01 | 1997-05-27 | Lucent Technologies Inc. | System and method for generating mask layouts |
US5633806A (en) * | 1992-10-12 | 1997-05-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit and method of designing same |
US5673199A (en) * | 1995-05-01 | 1997-09-30 | Hughes Electronics | Computer aided reuse tool |
WO1998015976A1 (en) * | 1996-10-10 | 1998-04-16 | Semiconductores Investigación Y Diseno, S.A. - (Sidsa) | Process for the prototyping of mixed signal applications and field programmable system on a chip for applying said process |
US5828580A (en) * | 1994-11-08 | 1998-10-27 | Epic Design Technology, Inc. | Connectivity-based approach for extracting parasitic layout in an integrated circuit |
US5835378A (en) * | 1995-11-20 | 1998-11-10 | Lsi Logic Corporation | Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip |
US5896301A (en) * | 1996-10-25 | 1999-04-20 | Advanced Micro Devices, Inc. | Method for performing floorplan timing analysis using multi-dimensional feedback in a histogram and integrated circuit made using same |
US5903472A (en) * | 1996-10-25 | 1999-05-11 | Advanced Micro Devices, Inc. | Method for performing floorplan timing analysis by selectively displaying signal paths based on slack time calculations and integrated circuit made using same |
US5903469A (en) * | 1994-11-08 | 1999-05-11 | Synopsys, Inc. | Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach |
US5910899A (en) * | 1996-10-25 | 1999-06-08 | Advanced Micro Devices, Inc. | Method for performing floorplan timing analysis using multi-dimensional feedback in a spreadsheet with computed hyperlinks to physical layout graphics and integrated circuit made using same |
US5946210A (en) * | 1996-04-19 | 1999-08-31 | Vlt Corporation | Configuring power converters |
US6110213A (en) * | 1997-11-06 | 2000-08-29 | Vlt Coporation | Fabrication rules based automated design and manufacturing system and method |
US6177942B1 (en) * | 1996-04-30 | 2001-01-23 | Mentor Graphics Corporation | Part development system |
US6321367B1 (en) * | 1996-08-30 | 2001-11-20 | Altera Corporation | Apparatus and method for automatically generating circuit layouts |
US6349402B1 (en) * | 1998-07-09 | 2002-02-19 | Kuoching Lin | Method and apparatus for optimizing differential pairs based on timing constraints |
US6405356B1 (en) * | 1998-11-20 | 2002-06-11 | Via Technologies, Inc. | Method of automatic placement for an arrayed-element device |
US6453276B1 (en) * | 1998-12-22 | 2002-09-17 | Unisys Corporation | Method and apparatus for efficiently generating test input for a logic simulator |
US6467072B1 (en) * | 1998-11-20 | 2002-10-15 | Via Technologies, Inc. | Method of placement and routing for an array device |
US6606732B2 (en) | 2000-12-11 | 2003-08-12 | International Business Machines Corporation | Method for specifying, identifying, selecting or verifying differential signal pairs on IC packages |
WO2003088099A2 (en) * | 2002-04-07 | 2003-10-23 | Barcelona Design, Inc. | Efficient layout strategy for automated design layout tools |
US20040015787A1 (en) * | 2002-04-10 | 2004-01-22 | Thomas Heydler | Method and apparatus for efficient semiconductor process evaluation |
US20040025136A1 (en) * | 2002-07-30 | 2004-02-05 | Carelli John A. | Method for designing a custom ASIC library |
US6708144B1 (en) * | 1997-01-27 | 2004-03-16 | Unisys Corporation | Spreadsheet driven I/O buffer synthesis process |
US20040268284A1 (en) * | 2003-06-24 | 2004-12-30 | International Business Machines Corporation | Method of forming guard ring parameterized cell structure in a hierarchical parameterized cell design, checking and verification system |
US6848089B2 (en) * | 2002-07-31 | 2005-01-25 | International Business Machines Corporation | Method and apparatus for detecting devices that can latchup |
US20060117284A1 (en) * | 2004-11-30 | 2006-06-01 | Alexandre Andreev | RRAM memory timing learning tool |
US20060274681A1 (en) * | 2005-06-02 | 2006-12-07 | International Business Machines Corporation | Apparatus and method for reduced loading of signal transmission elements |
US7277825B1 (en) * | 2003-04-25 | 2007-10-02 | Unisys Corporation | Apparatus and method for analyzing performance of a data processing system |
US7299459B1 (en) | 2000-01-19 | 2007-11-20 | Sabio Labs, Inc. | Parser for signomial and geometric programs |
US7353188B2 (en) * | 2000-06-30 | 2008-04-01 | Lg Electronics | Product selling system and method for operating the same |
US7401310B1 (en) | 2006-04-04 | 2008-07-15 | Advanced Micro Devices, Inc. | Integrated circuit design with cell-based macros |
US20090146692A1 (en) * | 2007-12-06 | 2009-06-11 | Hsu Louis L | Structure for apparatus for reduced loading of signal transmission elements |
US20090161722A1 (en) * | 2007-12-21 | 2009-06-25 | International Business Machines Corporation | Automatic shutdown or throttling of a bist state machine using thermal feedback |
US10216890B2 (en) | 2004-04-21 | 2019-02-26 | Iym Technologies Llc | Integrated circuits having in-situ constraints |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
UST940013I4 (en) * | 1974-09-17 | 1975-11-04 | Network design process using multiple performance functions | |
US4933860A (en) * | 1988-05-20 | 1990-06-12 | Trw Inc. | Method for fabricating a radio frequency integrated circuit and product formed thereby |
US4967367A (en) * | 1988-11-21 | 1990-10-30 | Vlsi Technology, Inc. | Synthetic netlist system and method |
-
1993
- 1993-10-29 US US08/147,465 patent/US5402358A/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
UST940013I4 (en) * | 1974-09-17 | 1975-11-04 | Network design process using multiple performance functions | |
US4933860A (en) * | 1988-05-20 | 1990-06-12 | Trw Inc. | Method for fabricating a radio frequency integrated circuit and product formed thereby |
US4967367A (en) * | 1988-11-21 | 1990-10-30 | Vlsi Technology, Inc. | Synthetic netlist system and method |
Non-Patent Citations (37)
Title |
---|
A. Domic et al, CLEO: a CMOS layout generator, Nov. 1989, pp. 340 343. * |
A. Domic et al, CLEO: a CMOS layout generator, Nov. 1989, pp. 340-343. |
A. R. Newton, Symbolic Layout and Procedural Design, 1987, pp. 65 113. * |
A. R. Newton, Symbolic Layout and Procedural Design, 1987, pp. 65-113. |
C. Hwant, Y. Hateh, et al, An Optimal Transistor Chaining Algorithm for CMOS Cell Layout, 1989, pp. 344, 347. * |
C. Hwant, Y. Hateh, et al, An Optimal Transistor-Chaining Algorithm for CMOS Cell Layout, 1989, pp. 344, 347. |
D. Hill, Sc2:A Hybrid Automatic Layout System, Nov. 1985, pp. 172 174. * |
D. Hill, Sc2:A Hybrid Automatic Layout System, Nov. 1985, pp. 172-174. |
Design Methodologies for VLSI Systems, Analog Digital ASIC Design, pp. 60 61. * |
Design Methodologies for VLSI Systems, Analog Digital ASIC Design, pp. 60-61. |
G. Thuau, G. Saucier, Optimized Layout of MOS Cells, 1988, pp. 79 87. * |
G. Thuau, G. Saucier, Optimized Layout of MOS Cells, 1988, pp. 79-87. |
H. Cai, S. Note et al, A Data Path Layout Assembler for High Performance DSP Circuits, 1990, pp. 306 311. * |
H. Cai, S. Note et al, A Data Path Layout Assembler for High Performance DSP Circuits, 1990, pp. 306-311. |
H. Heeb and W. Fichtner, GRAPES: A Module Generator Based on Graph Planarity, Nov. 1987, pp. 428 431. * |
H. Heeb and W. Fichtner, GRAPES: A Module Generator Based on Graph Planarity, Nov. 1987, pp. 428-431. |
IEEE Journal of Solid State Circuits, vol. 24, No. 5, Oct. 1989 Cell Libraries and Assembly Tools for Analog/Digital CMOS and BiCMOS Application Specific Integrated Circuit Design by M. Smith et al. * |
IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989 Cell Libraries and Assembly Tools for Analog/Digital CMOS and BiCMOS Application-Specific Integrated Circuit Design by M. Smith et al. |
N. Matsumoto, Y. Watanabe et al, Datapath Generator Based on Gate Level Symbolic Layout, 1990, pp. 388 393. * |
N. Matsumoto, Y. Watanabe et al, Datapath Generator Based on Gate-Level Symbolic Layout, 1990, pp. 388-393. |
R. J. Duffin, Toplogy of series parallel networks, 1965, pp. 308 318. * |
R. J. Duffin, Toplogy of series-parallel networks, 1965, pp. 308-318. |
R. L. Maziasz et al, Layout Optimization of Static CMOS Functional Cells, Jul. 1990, pp. 708 719. * |
R. L. Maziasz et al, Layout Optimization of Static CMOS Functional Cells, Jul. 1990, pp. 708-719. |
S. Chakravarty et al, On Optimizing nMos and Dynamic CMOS Functional Cells, 1990, pp. 1701 1704. * |
S. Chakravarty et al, On Optimizing nMos and Dynamic CMOS Functional Cells, 1990, pp. 1701-1704. |
S. Wimer, R. Pinter, Optimal Chaining of CMOS Transistors in a Functional Cell, 1987, pp. 795 801. * |
S. Wimer, R. Pinter, Optimal Chaining of CMOS Transistors in a Functional Cell, 1987, pp. 795-801. |
Successful ASIC Design the First Time Through, Van Nostrand Reinhold, 1991, p. 18. * |
T. Lager IV, Release 3.1, Lager IV Tools Users Manual, On Line Documentation, Nov. 1991, pp. 1 10. * |
T. Lager IV, Release 3.1, Lager IV Tools Users Manual, On-Line Documentation, Nov. 1991, pp. 1-10. |
T. Lager, Lager IV Tools Users Manual, On Line Documentation for Public Domain UC Berkeley CAD Tools, Jun. 1990, pp. 1 3, Rev. 2.0. * |
T. Lager, Lager IV Tools Users Manual, On-Line Documentation for Public Domain UC Berkeley CAD Tools, Jun. 1990, pp. 1-3, Rev. 2.0. |
VLSI Technology, Inc. VLSIslice Silicon Compiler Language and Development Tool, 14 Mar. 1991, pp. 1 89. * |
VLSI Technology, Inc. VLSIslice Silicon Compiler Language and Development Tool, 14 Mar. 1991, pp. 1-89. |
Y. M. Hunag and M. Sarrafzadeh, Parallel Algorithmy for Mimimum dual cover with applications to CMOS layout, Aug. 1988, pp. 26 33. * |
Y. M. Hunag and M. Sarrafzadeh, Parallel Algorithmy for Mimimum dual-cover with applications to CMOS layout, Aug. 1988, pp. 26-33. |
Cited By (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5633806A (en) * | 1992-10-12 | 1997-05-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit and method of designing same |
US6421814B1 (en) | 1994-11-08 | 2002-07-16 | Synopsys, Inc. | Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach |
US5999726A (en) * | 1994-11-08 | 1999-12-07 | Synopsys, Inc. | Connectivity-based approach for extracting layout parasitics |
US6128768A (en) * | 1994-11-08 | 2000-10-03 | Synopsys, Inc. | Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach |
US5828580A (en) * | 1994-11-08 | 1998-10-27 | Epic Design Technology, Inc. | Connectivity-based approach for extracting parasitic layout in an integrated circuit |
US5903469A (en) * | 1994-11-08 | 1999-05-11 | Synopsys, Inc. | Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach |
US6438729B1 (en) | 1994-11-08 | 2002-08-20 | Synopsys, Inc. | Connectivity-based approach for extracting layout parasitics |
US5633807A (en) * | 1995-05-01 | 1997-05-27 | Lucent Technologies Inc. | System and method for generating mask layouts |
US5673199A (en) * | 1995-05-01 | 1997-09-30 | Hughes Electronics | Computer aided reuse tool |
US5835378A (en) * | 1995-11-20 | 1998-11-10 | Lsi Logic Corporation | Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip |
US5946210A (en) * | 1996-04-19 | 1999-08-31 | Vlt Corporation | Configuring power converters |
US6177942B1 (en) * | 1996-04-30 | 2001-01-23 | Mentor Graphics Corporation | Part development system |
US6321367B1 (en) * | 1996-08-30 | 2001-11-20 | Altera Corporation | Apparatus and method for automatically generating circuit layouts |
US6460172B1 (en) | 1996-10-10 | 2002-10-01 | Semiconductors Investigacion Diseno, S.A. (Sidsa) | Microprocessor based mixed signal field programmable integrated device and prototyping methodology |
WO1998015976A1 (en) * | 1996-10-10 | 1998-04-16 | Semiconductores Investigación Y Diseno, S.A. - (Sidsa) | Process for the prototyping of mixed signal applications and field programmable system on a chip for applying said process |
US5910899A (en) * | 1996-10-25 | 1999-06-08 | Advanced Micro Devices, Inc. | Method for performing floorplan timing analysis using multi-dimensional feedback in a spreadsheet with computed hyperlinks to physical layout graphics and integrated circuit made using same |
US5903472A (en) * | 1996-10-25 | 1999-05-11 | Advanced Micro Devices, Inc. | Method for performing floorplan timing analysis by selectively displaying signal paths based on slack time calculations and integrated circuit made using same |
US5896301A (en) * | 1996-10-25 | 1999-04-20 | Advanced Micro Devices, Inc. | Method for performing floorplan timing analysis using multi-dimensional feedback in a histogram and integrated circuit made using same |
US6708144B1 (en) * | 1997-01-27 | 2004-03-16 | Unisys Corporation | Spreadsheet driven I/O buffer synthesis process |
US6110213A (en) * | 1997-11-06 | 2000-08-29 | Vlt Coporation | Fabrication rules based automated design and manufacturing system and method |
US6847853B1 (en) | 1997-11-06 | 2005-01-25 | Vlt, Inc. | Fabrication rules based automated design and manufacturing system and method |
US6349402B1 (en) * | 1998-07-09 | 2002-02-19 | Kuoching Lin | Method and apparatus for optimizing differential pairs based on timing constraints |
US6405356B1 (en) * | 1998-11-20 | 2002-06-11 | Via Technologies, Inc. | Method of automatic placement for an arrayed-element device |
US6467072B1 (en) * | 1998-11-20 | 2002-10-15 | Via Technologies, Inc. | Method of placement and routing for an array device |
US6453276B1 (en) * | 1998-12-22 | 2002-09-17 | Unisys Corporation | Method and apparatus for efficiently generating test input for a logic simulator |
US7299459B1 (en) | 2000-01-19 | 2007-11-20 | Sabio Labs, Inc. | Parser for signomial and geometric programs |
US7353188B2 (en) * | 2000-06-30 | 2008-04-01 | Lg Electronics | Product selling system and method for operating the same |
US6606732B2 (en) | 2000-12-11 | 2003-08-12 | International Business Machines Corporation | Method for specifying, identifying, selecting or verifying differential signal pairs on IC packages |
WO2003088099A2 (en) * | 2002-04-07 | 2003-10-23 | Barcelona Design, Inc. | Efficient layout strategy for automated design layout tools |
WO2003088099A3 (en) * | 2002-04-07 | 2004-11-18 | Barcelona Design Inc | Efficient layout strategy for automated design layout tools |
US7093205B2 (en) | 2002-04-10 | 2006-08-15 | Barcelona Design, Inc. | Method and apparatus for efficient semiconductor process evaluation |
US20040015787A1 (en) * | 2002-04-10 | 2004-01-22 | Thomas Heydler | Method and apparatus for efficient semiconductor process evaluation |
US20040025136A1 (en) * | 2002-07-30 | 2004-02-05 | Carelli John A. | Method for designing a custom ASIC library |
US6848089B2 (en) * | 2002-07-31 | 2005-01-25 | International Business Machines Corporation | Method and apparatus for detecting devices that can latchup |
US7277825B1 (en) * | 2003-04-25 | 2007-10-02 | Unisys Corporation | Apparatus and method for analyzing performance of a data processing system |
US20040268284A1 (en) * | 2003-06-24 | 2004-12-30 | International Business Machines Corporation | Method of forming guard ring parameterized cell structure in a hierarchical parameterized cell design, checking and verification system |
US7350160B2 (en) * | 2003-06-24 | 2008-03-25 | International Business Machines Corporation | Method of displaying a guard ring within an integrated circuit |
US20080098337A1 (en) * | 2003-06-24 | 2008-04-24 | International Business Machines Corporation | Method of forming guard ring parameterized cell structure in a hierarchical parameterized cell design, checking and verification system |
US10860773B2 (en) | 2004-04-21 | 2020-12-08 | Iym Technologies Llc | Integrated circuits having in-situ constraints |
US10216890B2 (en) | 2004-04-21 | 2019-02-26 | Iym Technologies Llc | Integrated circuits having in-situ constraints |
US10846454B2 (en) | 2004-04-21 | 2020-11-24 | Iym Technologies Llc | Integrated circuits having in-situ constraints |
US20060117284A1 (en) * | 2004-11-30 | 2006-06-01 | Alexandre Andreev | RRAM memory timing learning tool |
US7200826B2 (en) * | 2004-11-30 | 2007-04-03 | Lsi Logic Corporation | RRAM memory timing learning tool |
US20060274681A1 (en) * | 2005-06-02 | 2006-12-07 | International Business Machines Corporation | Apparatus and method for reduced loading of signal transmission elements |
US8040813B2 (en) | 2005-06-02 | 2011-10-18 | International Business Machines Corporation | Apparatus and method for reduced loading of signal transmission elements |
US7401310B1 (en) | 2006-04-04 | 2008-07-15 | Advanced Micro Devices, Inc. | Integrated circuit design with cell-based macros |
US8024679B2 (en) | 2007-12-06 | 2011-09-20 | International Business Machines Corporation | Structure for apparatus for reduced loading of signal transmission elements |
US20090146692A1 (en) * | 2007-12-06 | 2009-06-11 | Hsu Louis L | Structure for apparatus for reduced loading of signal transmission elements |
US7689887B2 (en) * | 2007-12-21 | 2010-03-30 | International Business Machines Corporation | Automatic shutdown or throttling of a BIST state machine using thermal feedback |
US20090161722A1 (en) * | 2007-12-21 | 2009-06-25 | International Business Machines Corporation | Automatic shutdown or throttling of a bist state machine using thermal feedback |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5402358A (en) | Method and structure for the automated design of analog integrated circuits | |
Wolf | Modern VLSI design: system-on-chip design | |
Van Der Meijs et al. | VLSI circuit reconstruction from mask topology | |
Toumazou et al. | Analog IC design automation. I. Automated circuit generation: new concepts and methods | |
CN113950686A (en) | Automatic circuit generation | |
US6291322B1 (en) | Method for modeling noises in an integrated circuit | |
US6560753B2 (en) | Integrated circuit having tap cells and a method for positioning tap cells in an integrated circuit | |
US4607339A (en) | Differential cascode current switch (DCCS) master slice for high efficiency/custom density physical design | |
US8042080B2 (en) | Electro-migration verifying apparatus, electro-migration verifying method, data structure and netlist used in the same | |
Naiknaware et al. | Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations | |
US7065727B2 (en) | Optimal simultaneous design and floorplanning of integrated circuit | |
Wolf | Modern VLSI Design: IP-Based Design (paperback) | |
US7200825B2 (en) | Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip | |
US6678869B2 (en) | Delay calculation method and design method of a semiconductor integrated circuit | |
US4608649A (en) | Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design | |
US7587305B2 (en) | Transistor level verilog | |
Cherkauer et al. | Channel width tapering of serially connected MOSFET's with emphasis on power dissipation | |
Daseking et al. | Vista: a VLSI CAD system | |
Schroter et al. | Compact layout and bias-dependent base-resistance modeling for advanced SiGe HBTs | |
US6839887B1 (en) | Method and system for predictive multi-component circuit layout generation with reduced design cycle | |
Lan et al. | Matching performance of current mirrors with arbitrary parameter gradients through the active devices | |
Naiknaware et al. | Schematic driven module generation for analog circuits with performance optimization and matching considerations | |
Strang | CAD Tools and Design Kits | |
McElwee | An Automated Analog Layout Generation Flow | |
Lomelí-Illescas et al. | A tool for the automatic generation and analysis of regular analog layout modules |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: PHILIPS SEMICONDUCTORS VLSI INC., NEW YORK Free format text: CHANGE OF NAME;ASSIGNOR:VLSI TECHNOLOGY, INC.;REEL/FRAME:018635/0570 Effective date: 19990702 Owner name: NXP B.V., NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PHILIPS SEMICONDUCTORS INC.;REEL/FRAME:018645/0779 Effective date: 20061130 |
|
AS | Assignment |
Owner name: PHILIPS SEMICONDUCTORS INC., NEW YORK Free format text: CHANGE OF NAME;ASSIGNOR:PHILIPS SEMICONDUCTORS VLSI INC.;REEL/FRAME:018668/0255 Effective date: 19991220 |