US5285408A - Method and apparatus for providing a faster ones voltage level restore operation in a dram - Google Patents
Method and apparatus for providing a faster ones voltage level restore operation in a dram Download PDFInfo
- Publication number
- US5285408A US5285408A US07/945,206 US94520692A US5285408A US 5285408 A US5285408 A US 5285408A US 94520692 A US94520692 A US 94520692A US 5285408 A US5285408 A US 5285408A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
Definitions
- the present invention relates to DRAMs. Particularly, a DRAM that provides a faster ones voltage level restore operation. Uniquely, the DRAM does not turn off, but current limits, the active pull-up circuitry during a memory cell write cycle.
- FIG. 1 is a general illustration of a typical 5 volt DRAM 10, including the following elements: Column decoding circuitry 12, a first half of a memory array 14, an N-channel sense amplifier (NSA) 16, a second half of a memory array 18, and a P-channel sense amplifier (PSA) 20.
- Column decoding circuitry 12 a first half of a memory array 14, an N-channel sense amplifier (NSA) 16, a second half of a memory array 18, and a P-channel sense amplifier (PSA) 20.
- NSA N-channel sense amplifier
- PSA P-channel sense amplifier
- the column decode 12 routs signals going to and from the memory arrays.
- the word line (row line) is turned on, thus selecting the cell to be read and thereby dumping the stored charge of the cell onto the associated digit line.
- the small charge from the cell will cause a small voltage change on the digit line; either up or down depending whether a one or zero is stored.
- FIG. 2 illustrates when a ones charge is accessed from the cell. NSA will pull the lower voltage digit line towards ground, this is followed by PSA pulling the corresponding higher voltage digit line up, towards supply voltage (Vcc). The PSA and NSA amplify the voltage differences between the two digit lines associated with a particular memory cell being accessed.
- the PSA is turned off during a write back to allow the high digit line to be pulled towards ground and the low voltage digit line to be pulled up towards a ones voltage level. Thereafter attaining a write back, PSA is turned back on to continue recharging the new digit line towards the ones voltage level. Whereby, the respective voltages on the digit lines are clamped, trapping the appropriate charges in the memory cells, and the high and low voltages are equilibrated together to provide for an intermediate pre-charged voltage level in preparation for the next cycle.
- a problem occurs during the write operation. Specifically, beginning with the read operation, after the accessed memory cell's row is turned on, the whole row (or word line) is turned on. The word line opens all of the gates of the associated memory cells, thereby dumping the stored charges onto the appropriate digit lines. During the write back operation, all of the non-accessed memory cells on the word line are restored to the former charges. This restoration process is accomplished by the NSA and PSA circuits separating and amplifying the voltages on the digit lines before the word line shuts all the memory cell gates, thereby trapping the restored and refreshed charges in the non-accessed or addressed memory cells.
- the problem occurs, during a write back operation to the accessed memory cell.
- the global PSA shut down during the write operation has the effect of increasing the overall operation time for each read-write cycle, and more importantly, slowing down the overall DRAM device.
- the present invention provides for a DRAM non-accessed memory cell refresh or restore process/operation that reaches a digit line's ones voltage level faster. Specifically, the invention does not shut down any PSAs during the write operation. By leaving on the PSAs, the ones digit lines will continue to be pulled-up towards a ones voltage level even during the write operation. Thus, the digit line being pulled high (being restored to a ones voltage level) will reach the final ones voltage level sooner and obviously shortening the restore operation and ultimately the overall cycle time.
- FIG. 1 is a illustration of a particular DRAM architecture.
- FIG. 2 is a typical voltage vs. timing graph illustrating the cycle of a read, write, recharge, and equilibrate operation for the two addressed digit lines.
- FIG. 4 is a circuitry of a PSA and associated signal controls.
- U.S. Pat. No. 5,042,011 is a sense amplifier pull-down device with tailored edge input.
- U.S. Pat. No. 4,748,349 is a high performance dynamic sense amplifier with voltage boost for row address lines.
- U.S. Pat. No. 4,636,987 is a semiconductor dynamic memory device with multiplexed sense amplifier and write activated active loads.
- U.S. Pat. No. 4,543,500 is a high performance dynamic sense amplifier voltage boost for row address lines.
- U.S Pat. No. 4,533,843 is a high performance dynamic sense amplifier with voltage boost for row address lines.
- U.S. Pat. No. 4,370,575 is a high performance dynamic sense amplifier with active loads.
- U.S. Pat. No. 4,366,559 is a memory device.
- U.S. Pat. No. 4,239,993 is a high performance dynamic sense amplifier with active loads.
- U.S. Pat. No. 4,233,675 is a X sense amp memory.
- the terminology of "the digit line being pulled high” has the same meaning as a “ones digit line” or a “digit line being restored to a ones voltage level.” All describe that one of the digit lines in a pair has its voltage being pulled towards a ones voltage level.
- FIG. 3 A general embodiment of the improved timing cycle for the non-accessed memory cells located on the activated word line is illustrated in FIG. 3.
- FIG. 3 One skilled in the art will understand the general operation of the voltage versus time diagram of a typical non-accessed pair of digit lines as in FIG. 3 in reference to the simultaneous timing with the accessed pair of digit lines of FIG. 2.
- the word line is activated, in this case, a ones charge is dumped onto the digit line.
- the NSA fires, pulling the other digit line low, towards the zeros voltage level.
- the PSA fires, pulling the higher voltage digit line towards the ones voltage level.
- the difference between the new and prior art (old) embodiments develops at the beginning of the write operation.
- the old method shuts off the PSA, during which time there is no more recharging of the associated digit lines towards the ones voltage level.
- PSA is reactivated, thus continuing the digit line's voltage pull-up.
- the new method (illustrated by the dotted lines), will not turn off the PSA, but merely limit the current to PSA 20.
- the voltage on the digit line keeps increasing; although, perhaps, at a somewhat slower rate of increase.
- PSA 20 is fully activated (having no current limiting), and resumes the final recharge operation, at the prior faster rate of voltage pull-up towards the ones voltage level.
- delta t the new approach will 1) reach ones voltage level sooner than the old method, 2) allow for sooner equilibrate and precharge operation in preparation for the next cycle, and 3) shorten the overall cycle time.
- PSA 20 is a cross coupled P-channel device, connected to a pair of digit lines 30.
- P-channel transistor 34 receives either a PSAr (PSA read) signal 32 or a PSAw (PSA write) signal 38.
- P-channel transistor 36 with the gate connected to ground is always on. Both transistors 34 and 36 connect PSA 20 to ACT line (active pull-up line) 40. Supply voltage Vcc is connected to ACT line 40 via transistor 42.
- the size and other parameters of transistor 36 are chosen so that it will not allow as much current to flow to PSA 20 as will transistor 34.
- PSA 20 is activated (receives current from ACT 40) when PSAr 32 signal is pulsed high, thereby opening transistor 34 and therefore supplying PSA 20 with a full current from ACT 40.
- PSAw 38 signal is pulsed low, turning off transistor 34; thereby, transistor 36 is the only connection between ACT 40 and PSA 20.
- transistor 36 has a higher impedance than transistor 34, PSA 20 receives less current during the write operation. Therefore, PSA 20 is never turned off, but does operate at a lower current during the write operation.
- Transistor 36 will limit the current from ACT 40 to PSA 20; thereby 1) allowing switching of the voltages on the accessed digit lines, and 2) continuously allowing active voltage pull-up, during the entire write operation, of the non-addressed digit lines; thereby shortening the overall time to reach the ones voltage level and thereby completing the full cycle of operation.
- FIG. 2 and 3 take place simultaneously; one being the accessed digit lines, the other the non-accessed digit lines. All references to the sequence of events in the non-accessed digit lines are related to the operation occurring during a writing back of an opposite charge to the addressed memory cell.
- transistor 42 limits the current from Vcc to ACT 40. Notedly, if Vcc were directly applied to ACT 40, the PSA 20 would be damaged. Consequently, when transistor 42 is turned on, it takes about 30 to 40 nsec to pull ACT 42 from ground or Vcc/2 up to Vcc.
Abstract
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US07/945,206 US5285408A (en) | 1992-09-15 | 1992-09-15 | Method and apparatus for providing a faster ones voltage level restore operation in a dram |
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US07/945,206 US5285408A (en) | 1992-09-15 | 1992-09-15 | Method and apparatus for providing a faster ones voltage level restore operation in a dram |
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US5285408A true US5285408A (en) | 1994-02-08 |
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US07/945,206 Expired - Lifetime US5285408A (en) | 1992-09-15 | 1992-09-15 | Method and apparatus for providing a faster ones voltage level restore operation in a dram |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5615158A (en) * | 1995-11-13 | 1997-03-25 | Micron Technology, Inc. | Sense amplifier circuit for detecting degradation of digit lines and method thereof |
US5677878A (en) * | 1996-01-17 | 1997-10-14 | Micron Technology, Inc. | Method and apparatus for quickly restoring digit I/O lines |
US5783948A (en) * | 1995-06-23 | 1998-07-21 | Micron Technology, Inc. | Method and apparatus for enhanced booting and DC conditions |
US5959933A (en) * | 1996-01-25 | 1999-09-28 | Micron Technology, Inc. | System for improved memory cell access |
Citations (11)
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US4233675A (en) * | 1979-06-08 | 1980-11-11 | National Semiconductor Corporation | X Sense AMP memory |
US4239993A (en) * | 1978-09-22 | 1980-12-16 | Texas Instruments Incorporated | High performance dynamic sense amplifier with active loads |
US4366559A (en) * | 1978-05-12 | 1982-12-28 | Nippon Electric Co., Ltd. | Memory device |
US4370575A (en) * | 1978-09-22 | 1983-01-25 | Texas Instruments Incorporated | High performance dynamic sense amplifier with active loads |
US4567389A (en) * | 1984-07-05 | 1986-01-28 | Mostek Corporation | CMOS Differential amplifier |
US4627033A (en) * | 1984-08-02 | 1986-12-02 | Texas Instruments Incorporated | Sense amplifier with reduced instantaneous power |
US4636987A (en) * | 1984-08-29 | 1987-01-13 | Texas Instruments | Semiconductor dynamic memory device with multiplexed sense amplifier and write-activated active loads |
US4766333A (en) * | 1987-03-09 | 1988-08-23 | Inmos Corporation | Current sensing differential amplifier |
US4951252A (en) * | 1988-10-25 | 1990-08-21 | Texas Instruments Incorporated | Digital memory system |
US5042011A (en) * | 1989-05-22 | 1991-08-20 | Micron Technology, Inc. | Sense amplifier pulldown device with tailored edge input |
US5113372A (en) * | 1990-06-06 | 1992-05-12 | Micron Technology, Inc. | Actively controlled transient reducing current supply and regulation circuits for random access memory integrated circuits |
-
1992
- 1992-09-15 US US07/945,206 patent/US5285408A/en not_active Expired - Lifetime
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4366559A (en) * | 1978-05-12 | 1982-12-28 | Nippon Electric Co., Ltd. | Memory device |
US4239993A (en) * | 1978-09-22 | 1980-12-16 | Texas Instruments Incorporated | High performance dynamic sense amplifier with active loads |
US4370575A (en) * | 1978-09-22 | 1983-01-25 | Texas Instruments Incorporated | High performance dynamic sense amplifier with active loads |
US4233675A (en) * | 1979-06-08 | 1980-11-11 | National Semiconductor Corporation | X Sense AMP memory |
US4567389A (en) * | 1984-07-05 | 1986-01-28 | Mostek Corporation | CMOS Differential amplifier |
US4627033A (en) * | 1984-08-02 | 1986-12-02 | Texas Instruments Incorporated | Sense amplifier with reduced instantaneous power |
US4636987A (en) * | 1984-08-29 | 1987-01-13 | Texas Instruments | Semiconductor dynamic memory device with multiplexed sense amplifier and write-activated active loads |
US4766333A (en) * | 1987-03-09 | 1988-08-23 | Inmos Corporation | Current sensing differential amplifier |
US4951252A (en) * | 1988-10-25 | 1990-08-21 | Texas Instruments Incorporated | Digital memory system |
US5042011A (en) * | 1989-05-22 | 1991-08-20 | Micron Technology, Inc. | Sense amplifier pulldown device with tailored edge input |
US5113372A (en) * | 1990-06-06 | 1992-05-12 | Micron Technology, Inc. | Actively controlled transient reducing current supply and regulation circuits for random access memory integrated circuits |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5783948A (en) * | 1995-06-23 | 1998-07-21 | Micron Technology, Inc. | Method and apparatus for enhanced booting and DC conditions |
US5945845A (en) * | 1995-06-23 | 1999-08-31 | Micron Technology, Inc. | Method and apparatus for enhanced booting and DC conditions |
US5615158A (en) * | 1995-11-13 | 1997-03-25 | Micron Technology, Inc. | Sense amplifier circuit for detecting degradation of digit lines and method thereof |
US5742549A (en) * | 1995-11-13 | 1998-04-21 | Micron Technology, Inc. | Sense amplifier circuit for detecting degradation of digit lines and method thereof |
US5677878A (en) * | 1996-01-17 | 1997-10-14 | Micron Technology, Inc. | Method and apparatus for quickly restoring digit I/O lines |
US5959933A (en) * | 1996-01-25 | 1999-09-28 | Micron Technology, Inc. | System for improved memory cell access |
US6094378A (en) * | 1996-01-25 | 2000-07-25 | Micron Technology, Inc. | System for improved memory cell access |
US6288952B1 (en) | 1996-01-25 | 2001-09-11 | Micron Technology, Inc. | System for improved memory cell access |
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