|Publication number||US5218704 A|
|Application number||US 07/429,270|
|Publication date||8 Jun 1993|
|Filing date||30 Oct 1989|
|Priority date||30 Oct 1989|
|Also published as||CN1024226C, CN1054496A, DE69027510D1, DE69027510T2, EP0426410A2, EP0426410A3, EP0426410B1, US5930516, US6006336, US6173409, US6397340, US6633988, US6732283, US6732284, US7028198, US7284139, US7392416, US7549071, US9021283, US20010005892, US20020104033, US20030131272, US20030131273, US20040225906, US20040225908, US20050198543, US20050204177, US20050204178, US20050204179|
|Publication number||07429270, 429270, US 5218704 A, US 5218704A, US-A-5218704, US5218704 A, US5218704A|
|Inventors||LaVaughn F. Watts, Jr., Steven J. Wallace|
|Original Assignee||Texas Instruments|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Referenced by (362), Classifications (13), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to real-time computer power conservation, and more particularly to an apparatus and method for reduction of central processing unit (CPU) clock time based on the real-time activity level within the CPU of a portable computer.
2. Description of the Related Art
During the development stages of personal computers, the transportable or portable computer has become very popular. Such portable computer uses a large power supply and really represents a small desktop personal computer. Portable computers are smaller and lighter than a desktop personal computer and allow a user to employ the same software that can be used on a desktop computer.
The first generation "portable" computers only operated from an A/C wall power. As personal computer development continued, battery-powered computers were designed. Furthermore, real portability became possible with the development of new display technology, better disk storage, and lighter components.
However, the software developed was desiged to run on desk top personal computers, with all the features of desk top computers, without regard to battery-powered portable computers that only had limited amounts of power available for short periods of time. No special considerations were made by the software, operating system (MS-DOS), Basic Input/Output System (BIOS), or the third party application software to conserve power usage for these portable computers.
As more and more highly functional software packages were developed, desk top computer users experienced increased performance from the introductions of higher computational CPUs, increased memory, and faster high performance disk drives.
Unfortunately, portable computers continued to run only on A/C power or with large and heavy batteries. In trying to keep up with the performance requirements of the desk top computers, and the new software, expensive components were used to cut the power requirements. Even so, the heavy batteries still did not run very long. This meant users of portable computers had to settle for A/C operation or very short battery operation to have the performance that was expected from the third party software.
Portable computer designers stepped the performance down to 8088- and 8086-type processors to reduce the power consumption. The supporting circuits and CPU took less power to run and therefore, lighter batteries could be used. Unfortunately, the new software requiring 80286-type instructions, that did not exist in the older slower 8088/8086 CPUs, did not run.
In an attempt to design a portable computer that could conserve power, thereby yielding longer battery operation, smaller units, and less weight, some portable computer designers proceeded to reduce power consumption of a portable computer while a user is not using the computer. For example, designers obtain a reduction in power usage by slowing or stopping the disk drive after some predetermined period of inactivity; if the disk drive is not being used, the disk drive is turned off, or simply placed into a standby mode. When the user is ready to use the disk, the operator must wait until the disk drive spins up and the computer system is ready again for full performance before the operator may proceed with the operation.
Other portable computer designers conserve power by turning the computer display off when the keyboard is not being used. However, in normal operation the computer is using full power. In other words, power conservation by this method is practical only when the user is not using the components of the system. It is very likely, however, that the user will turn the computer off when not in use.
Nevertheless, substantial power conservation while the operator is using the computer for meaningful work is needed. When the operator uses the computer, full operation of all components is required. During the intervals while the operator is not using the computer, however, the computer could be turned off or slowed down to conserve power consumption. It is critical to maintaining performance to determine when to slow the computer down or turn it off without disrupting the user's work, upsetting the third party software, or confusing the operating system, until operation is needed.
Furthermore, although an user can wait for the disk to spin up as described above, application software packages cannot wait for the CPU to "spin up" and get ready. The CPU must be ready when the application program needs to compute. Switching to full operation must be completed quickly and without the application program being affected. This immediate transition must be transparent to the user as well as to the application currently active. Delays cause user operational problems in response time and software compatability, as well as general failure by the computer to accurately execute a required program.
Other attempts at power conservation for portable computers include providing a "Shut Down" or "Standby Mode" of operation. The problem, again, is that the computer is not usable by the operator during this period The operator could just as well turned off the power switch of the unit to save power. This type of power conservation only allows the portable computer to "shut down" and thereby save power if the operator forgets to turn off the power switch, or walks away from the computer for the programmed length of time. The advantage of this type of power conservation over just turning the power switch off/on is a much quicker return to full operation. However, this method of power conservation is still not real-time, intelligent power conservation while the computer is on and processing data which does not disturb the operating system, BIOS, and any third party application programs currently running on the computer.
Some attempt to meet this need was made by VLSI vendors in providing circuits that either turned off the clocks to the CPU when the user was not typing on the keyboard or woke up the computer on demand when a keystroke occurred. Either of these approaches reduce power but the computer is dead (unusable) during this period Background operations such as updating the system clock, communications, print spooling, and other like operations cannnot be performed. Some existing portable computers employ these circuits. After a programmed period of no activity, the computer turns itself off. The operator must turn the machine on again but does not have to reboot the operating system and application program. The advantage of this circuity is, like the existing "shut down" operations, a quick return to full operation without restarting the computer. Nevertheless, this method only reduces power consumption when the user walks away from the machine and does not actually extend the operational life of the battery charge.
In view of the above problems associated with the related art, it is an object of the present invention to provide an apparatus and method for real-time conservation of power for computer systems without any real-time performance degradation, such conservation of power remaining transparent to the user.
Another object of the present invention is to provide an apparatus and method for predicting the activity level within a computer system and using the prediction for automatic power conservation.
Yet another object of the present invention is to provide an apparatus and method which allows user modification of automatic activity level predictions and using the modified predictions for automatic power conservation.
A further object of the present invention is to provide an apparatus and method for real-time reduction and restoration of clock speeds thereby returning the CPU to full processing rate from a period of inactivity which is transparent to software programs.
These objects are accomplished in a preferred embodiment of the present invention by an apparatus and method which determine whether a CPU may rest based upon the CPU activity level and activates a hardware selector based upon that determination. If the CPU may rest, or sleep, the hardware selector applies oscillations at a sleep clock level; if the CPU is to be active, the hardware selector applies oscillations at a high speed clock level.
The present invention examines the state of CPU activity, as well as the activity of both the operator and any application software program currently active. This sampling of activity is performed real-time, adjusting the performance level of the computer to manage power conservation and computer power. These adjustments are accomplished within the CPU cycles and do not affect the user's perception of performance.
Thus, when the operator for the third party software of the operating system/BIOS is not using the computer, the present invention will effect a quick turn off or slow down of the CPU until needed, thereby reducing the power consumption, and will promptly restore full CPU operation when needed without affecting perceived performance. This switching back into full operation from the "slow down" mode occurs without the user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a "ready" state.
These and other features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of a preferred embodiment, taken together with the accompanying drawings, in which:
FIG. 1 is a flowchart depicting the self-tuning aspect of a preferred embodiment of the present invention;
FIGS. 2a-2d are flowcharts depicting the active power conservation monitor employed by the present invention;
FIG. 3 is a simplified schematic diagram representing the active power conservation associated hardware employed by the present invention;
FIG. 4 is a schematic of the sleep hardware for one embodiment of the present invention; and
FIG. 5 is a schematic of the sleep hardware for another embodiment of the present invention.
If the period of computer activity in any given system is examined, the CPU and associated components have a utilization percentage. If the user is inputing data from the keyboard, the time between keystrokes is very long in terms of CPU cycles. Many things can be accomplished by the computer during this time, such as printing a report. Even during the printing of a report, time is still available for additional operations such as background updating of a clock/calendar display. Even so, there is almost always spare time when the CPU is not being used. If the computer is turned off or slowed down during this spare time, then power consumption is obtained real-time. Such real-time power conservation extends battery operation life.
According to the preferred embodiment of the present invention, to conserve power under MS-DOS, as well as other operating systems such as OS/2, XENIX, and those for Apple computers, requires a combination of hardware and software. It should be noted that because the present invention will work in any system, while the implementation may vary slightly on a system-by-system basis, the scope of the present invention should therefore not be limited to computer systems operating under MS/DOS.
Slowing down or stopping the computer system components according to the preferred embodiment of the present invention, reduces power consumption, although the amount of power saved may vary. Therefore, according to the present invention, stopping the clock (where possible as some CPUs cannot have their clocks stopped) reduces the power consumption more than just slowing the clock.
In general, the number of operations (or instructions) per second may be considered to be roughly proportional to the processor clock:
Assuming for simplicity that the same instruction is repeatedly executed so that instructions/second is constant, the relationship can be expressed as follows:
where Fq is instructions/second, K1 is constant equal to the instructions/cycle, and Clk equals cycles/second. Thus, roughly speaking, the rate of execution increases with the frequency of the CPU clock.
The amount of power being used at any given moment is also related to the frequency of the CPU clock and therefore to the rate of execution. In general this relationship can be expressed as follows:
P=K2 +(K3 *Clk)
where P is power in watts, K2 is a constant in watts, K3 is a constant and expresses the number of watt-seconds/cycle, and Clk equals the cycles/second of the CPU clock. Thus it can also be said that the amount of power being consumed at any given time increases as the CPU clock frequency increases.
Assume that a given time period T is divded into N intervals such that the power P is constant during each interval. Then the amount of energy E expended during T is given by:
E=P(1)deltaT1 +P(2)deltaT2. . . +P(N)deltaTN
Further assume that the CPU clock "Clk" has only two states, either "ON" or "OFF". For the purposes of this discussion, the "ON" state represents the CPU clock at its maximum frequency, while the "OFF" state represents the minimum clock rate at which the CPU can operate (this may be zero for CPUs that can have their clocks stopped). For the condition in which the CPU clock is always "ON", each P(i) in the previous equation is equal and the total energy is: ##EQU1##
This represents the maximum power consumption of the computer in which no power conservation measures are being used. If the CPU clock is "off" during a portion of the intervals, then there are two power levels possible for each interval. The P(on) represents the power being consumed when the clock in in its "ON" state, while P(off) represents the power being used when the clock is "OFF". If all of the time intervals in which the clock is "ON"is summed into the quantity "T(on)" and the "OFF" intervals are summed into "T(off)", then it follows:
Now the energy being used during period T can be written:
Under these conditions, the total energy consumed may be reduced by increasing the time intervals T(off). Thus, by controlling the periods of time the clock is in its "OFF" state, the amount of energy being used may be reduced. If the T(off) period is divided into a large number of intervals during the period T, then as the width of each interval goes to zero, energy consumption is at a maximum. Conversely, as the width of the T(off) intervals increase, the energy consumed decreases.
If the "OFF" intervals are arranged to coincide with periods during which the CPU is normally inactive, then the user cannnot perceive any reduction in performance and overall energy consumption is reduced from the E(max) state. In order to align the T(off) intervals with periods of CPU inactivity, the CPU activity level is used to determine the width of the T(off) intervals in a closed loop. FIG. 1 depicts such a closed loop. The activity level of the CPU is determined at Step 10. If this level is an increase over an immediately previous determination, the present invention decreases the T(off) interval (Step 20) and returns to determine the activity level of the CPU again. If, on the other hand, this activity level is a decrease over an immediately previous determination, the present invention increases the T(off) interval (Step 30) and proceeds to again determine the activity level of the CPU. Thus the T(off) intervals are constantly being adjusted to match the system activity level.
In any operating system, two key logic points exist: an IDLE, or "do nothing", loop within the operating system and an operating system request channel, usually available for services needed by the application software. By placing logic inline with these logic points, the type of activity request made by an application software can be evaluated, power conservation can be activated and slice periods determined. A slice period is the number of T(on) vs. T(off) intervals over time, computed by the activity level. An assumption may be made to determine CPU activity level: Software programs that need service usually need additional services and the period of time between service requests can be used to determine the activity level of any application software running on the computer and to provide slice counts for power conservation according to the present invention.
Once the CPU is interrupted during a power conservation slice (T(off)), the CPU will save the interrupted routine's state prior to vectoring to the interrupt software. Of course, since the power conservation software was operating during this slice, control will be returned to the active power conservation loop (monitor 40) which simply monitors the CPU's clock to determine an exit condition for the power conservation mode, thereby exiting from T(off) to T(on) state. The interval of the next power conservation state is adjusted by the activity level monitored, as discussed above in connection with FIG. 1. Some implementations can create an automatic exit from T(off) by the hardware logic, thereby forcing the power conservation loop to be exited automatically and executing an interval T(on).
More specifically, looking now at FIGS. 2a-2d, which depict the active power conservation monitor 40 of the present invention. The CPU installs monitor 40 either via a program stored in the CPU ROM or loads it from an external device storing the program in RAM. Once the CPU has loaded monitor 40, it continues to INIT 50 for system interrupt initialization, user configurational setup, and system/application specific initialization. IDLE branch 60 (more specifically set out in FIG. 2b) is executed by a hardware or software interrupt for an IDLE or "do nothing" function. This type of interrupt is caused by the CPU entering either an IDLE or a "do nothing" loop (i.e., planned inactivity). The ACTIVITY branch 70 of the flowchart, more fully described below in relation to FIG. 2d, is executed by a software or hardware interrupt due to an operating system or I/O service request, by an application program or internal operating system function. An I/O service request made by a program may, for example, be a disk I/O, read, print, load, etc. Regardless of the branch selected, control is eventually returned to the CPU operating system at RETURN 80. The INIT branch 50 of this flowchart, shown in FIG. 2a, is executed only once if it is loaded via program into ROM or is executed every time during power up if it is loaded from an external device and stored in the RAM. Once this branch of active power monitor 40 has been fully executed, whenever control is yielded from the operating system to the power conservation mode, either IDLE 60 or ACTIVITY 70 branches are selected depending on the type of CPU activity: IDLE branch 60 for power conservation during planned inactivity and ACTIVITY branch 70 for power conservation during CPU activity.
Looking more closely at INIT branch 50 , after all system interrupt and variables are initialized, the routine continues at Step 90 to set the Power-- level equal to DEFAULT-- LEVEL. In operating systems where the user has input control for the Power-- level, the program at Step 100 checks to see if a User-- level has been selected. If the User-- level is less than zero or greater than the MAXIMUM-- LEVEL, the system uses the DEFAULT-- LEVEL. Otherwise, it continues onto Step 110 where it modifies the Power-- level to equal the User-- level.
According to the preferred embodiment of the present invention, the system at Step 120 sets the variable Idle-- tick to zero and the variable Activity-- tick to zero. Under an MS/DOS implementation, Idle-- tick refers to the number of interrupts found in a "do nothing" loop. Activity-- tick refers to the number of interrupts caused by an activity interrupt which in turn determines the CPU activity level. Tick count represents a delta time for the next interrupt. Idle-- tick is a constant delta time from one tick to another (interrupt) unless overwritten by a software interrupt. A software interrupt may reprogram delta time between interrupts.
After setting the variables to zero, the routine continues on to Setup 130 at which time any application specific configuration fine-tuning is handled in terms of system-specific details and the system is initialized. Next the routine arms the interrupt I/O (Step 140) with instructions to the hardware indicating the hardware can take control at the next interrupt. INIT branch 50 then exits to the operating system, or whatever called the active power monitor originally, at RETURN 80.
Consider now IDLE branch 60 of active power monitor 40, more fully described at FIG. 2b. In response to a planned inactivity of the CPU, monitor 40 (not specifically shown in this Figure) checks to see if entry into IDLE branch 60 is permitted by first determining whether the activity interrupt is currently busy. If Busy-- A equals BUSY-- FLAG (Step 150), which is a reentry flag, the CPU is busy and cannot now be put to sleep. Therefore, monitor 40 immediately proceeds to RETURN I 160 and exits the routine. RETURN I 160 is an indirect vector to the previous operating system IDLE vector interrupt for normal processing stored before entering monitor 40. (I.e., this causes an interrupt return to the last chained vector.)
If the Busy-- A interrupt flag is not busy, then monitor 40 checks to see if the Busy-- Idle interrupt flag, Busy-- I, equals BUSY-- FLAG (Step 170). If so, this indicates the system is already in IDLE branch 60 of monitor 40 and therefore the system should not interrupt itself. If Busy-- I =BUSY-- FLAG, the system exits the routine at RETURN-- I indirect vector 160.
If, however, neither the Busy-- A reentry flag or the Busy-- I reentry flag have been set, the routine sets the Busy-- I flag at Step 180 for reentry protection (Busy-- I=BUSY-- FLAG). At Step 190 Idle-- tick is incremented by one. Idle13 tick is the number of T(on) before a T(off) interval and is determined from IDLE interrupts, setup interrupts and from CPU activity level. Idle-- tick increments by one to allow for smoothing of events, thereby letting a critical I/O activity control smoothing.
At Step 200 monitor 40 checks to see if Idle-- tick equals IDLE-- MAXTICKS. IDLE13 MAXTICKS is one of the constants initialized in Setup 130 of INIT branch 50, remains constant for a system, and is responsible for self-tuning of the activity level. If Idle-- tick does not equal IDLE-- MAXTICKS, the Busy-- I flag is cleared at Step 210 and exits the loop proceeding to the RETURN I indirect vector 160. If, however, Idle-- tick equals IDLE-- MAXTCKS, Idle-- tick is set equal to IDLE-- START-- TICKS (Step 220). IDLE-- START-- TICKS is a constant which may or may not be zero (depending on whether the particular CPU can have its clock stopped). This step determines the self-tuning of how often the rest of the sleep functions may be performed. By setting IDLE-- START-- TICKS equal to IDLE-- MAXTICKS minus one, a continuous T(off) interval is achieved. At Step 230, the Power-- level is checked. If it is equal to zero, the monitor clears the Busy-- I flag (Step 210), exits the routine at RETURN I 160, and returns control to the operating system so it may continue what it was originally doing before it entered active power monitor 40.
If, however, the Power-- level does not equal zero at Step 240, the routine determines whether an interrupt mask is in place. An interrupt mask is set by the system/application software, and determines whether interrupts are available to monitor 40. If interrupts are NOT-- AVAILABLE, the Busy-- I reentry flag is cleared and control is returned to the operating system to continue what it was doing before it entered monitor 40. Operating systems, as well as application software, can set T(on) interval to yield a continuous T(on) state by setting the interrupt mask equal to NOT-- AVAILABLE.
Assuming an interrupt is AVAILABLE, monitor 40 proceeds to the SAVE POWER subroutine 250 which is fully executed during one T(off) period established by the hardware state. (For example, in the preferred embodiment of the present invention, the longest possible interval could be 18 ms, which is the longest time between two ticks or interrupts from the real-time clock.) During the SAVE POWER subroutine 250, the CPU clock is stepped down to a sleep clock level.
Once a critical I/O operation forces the T(on) intervals, the IDLE branch 60 interrupt tends to remain ready for additional critical I/O requests. As the CPU becomes busy with critical I/O, less T(off) intervals are available. Conversely, as critical I/O requests decrease, and the time intervals between them increase, more T(off) intervals are available. IDLE branch 60 is a self-tuning system based on feedback from activity interrupts and tends to provide more T(off) intervals as the activity level slows. As soon as monitor 40 has completed SAVE POWER subroutine 250, shown in FIG. 2c and more fully described below, the Busy-- I reentry flag is cleared (Step 210) and control is returned at RETURN I 160 to whatever operating system originally requested monitor 40.
Consider now FIG. 2c, which is a flowchart depicting the SAVE POWER subroutine 250. Monitor 40 determines what the I/O hardware high speed clock is at Step 260. It sets the CURRENT-- CLOCK-- RATE equal to the relevant high speed clock and saves this value to be used for CPUs with multiple level high speed clocks. Thus, if a particular CPU has 12 MHz and 6 MHz high speed clocks, monitor 40 must determine which high speed clock the CPU is at before monitor 40 reduces power so it may reestablish the CPU at the proper high speed clock when the CPU awakens. At Step 270, the Save-- clock-- rate is set equal to the CURRENT-- CLOCK-- RATE determined. Save-- clock-- rate 270 is not used when there is only one high speed clock for the CPU. Monitor 40 now continues to SLEEPCLOCK 280, where a pulse is sent to the hardware selector (shown in FIG. 3) to put the CPU clock to sleep (i.e., lower or stop its clock frequency). The I/O port hardware sleep clock is at much lower oscillations than the CPU clock normally employed.
At this point either of two events can happen. A system/application interrupt may occur or a real-time clock interrupt may occur. If a system/application interrupt 290 occurs, monitor 40 proceeds to interrupt routine 300, processing the interrupt as soon as possible, arming interrupt I/O at Step 310, and returning to determine whether there has been an interrupt (Step 320). Since in this case there has been an interrupt, the Save-- clock-- rate is used (Step 330) to determine which high speed clock to return the CPU to and SAVE POWER subroutine 250 is exited at RETURN 340. If, however, a system/application interrupt is not received, the SAVE POWER subroutine 250 will continue to wait until a real-time clock interrupt has occurred (Step 320). Once such an interrupt has occurred, SAVE POWER subroutine 250 reestablishes the CPU at the stored Save-clock-rate. If the sleep clock rate was not stopped, in other words, the sleep clock rate was not zero, control is passed at a slow clock and SAVE POWER subroutine 250 will execute interrupt loop 320 several times. If however, control is passed when the sleep clock rate was zero, in other words, there was no clock, the SAVE POWER subroutine 250 will execute interrupt loop 320 once before returning the CPU clock to the Save-- clock-- rate 330 and exiting (Step (340).
Consider now FIG. 2d which is a flowchart showing ACTIVITY branch 70 triggered by an application/system activity request via an operating system service request interrupt. ACTIVITY branch 70 begins with reentry protection. Monitor 40 determines at Step 350 whether Busy-- I has been set to BUSY-- FLAG. If it has, this means the system is already in IDLE branch 60 and cannot be interrupted. If Busy-- I=BUSY-- FLAG, monitor 40 exits to RETURN I 160, which is an indirect vector to an old activity vector interrupt for normal processing, via an interrupt vector after the operating system performs the requested service.
If however, the Busy-- I flag does not equal BUSY-- FLAG, which means IDLE branch 60 is not being accessed, monitor 40 determines at Step 360 if the BUSY-- A flag has been set equal to BUSY-- FLAG. If so, control will be returned to the system at this point because ACTIVITY branch 70 is already being used and cannot be interrupted. If the Busy-- A flag has not been set, in other words, Busy-- A does not equal BUSY-- FLAG, monitor 40 sets Busy-- A equal to BUSY-- FLAG at Step 370 so as not to be interrupted during execution of ACTIVITY branch 70. At Step 380 the Power-- level is determined. If Power-- level equals zero, monitor 40 exits ACTIVITY branch 70 after clearing the Busy-- A reentry flag (Step 390). If however, the Power-- level does not equal zero, the CURRENT-- CLOCK-- RATE of the I/O hardware is next determined. As was true with Step 270 of FIG. 2C, Step 400 of FIG. 2d uses the CURRENT-- CLOCK-- RATE if there are multiple level high speed clocks for a given CPU. Otherwise, CURRENT-- CLOCK-- RATE always equals the CPU high speed clock. After the CURRENT-- CLOCK-- RATE is determined (Step 400), at Step 410 Idle-- tick is set equal to the constant START-- TICKS established for the previously determined CURRENT-- CLOCK-- RATE. T(off) intervals are established based on the current high speed clock that is active.
Monitor 40 next determines that a request has been made. A request is an input by the application software running on the computer, for a particular type of service needed. At Step 420, monitor 40 determines whether the request is a CRITICAL I/O. If the request is a CRITICAL I/O, it will continuously force T(on) to lengthen until the T(on) is greater than the T(off), and monitor 40 will exit ACTIVITY branch 70 after clearing the Busy-- A reentry flag (Step 390). If, on the other hand, the request is not a CRITICAL I/O, then the Activity-- tick is incremented by one at Step 430. It is then determined at Step 440 whether the Activity-- tick now equals ACTIVITY-- MAXTICKS. Step 440 allows a smoothing from a CRITICAL I/O, and makes the system ready from another CRITICAL I/O during Activity-- tick T(on) intervals. Assuming Activity-- tick does not equal ACTIVITY-- MAXTICKS, ACTIVITY branch 70 is exited after clearing the Busy-- A reentry flag (Step 390). If, on the other hand, the Activity-- tick equals constant ACTIVITY-- MAXTICKS, at Step 450 Activity-- tick is set to the constant LEVEL-- MAXTICKS established for the particular Power-- level determined at Step 380.
Now monitor 40 determines whether an interrupt mask exists (Step 460). An interrupt mask is set by system/application software. Setting it to NOT-- AVAILABLE creates a continuous T(on) state. If the interrupt mask equals NOT-- AVAILABLE, there are no interrupts available at this time and monitor 40 exits ACTIVITY branch 70 after clearing the Busy-- A reentry flag (Step 390). If, however, an interrupt is AVAILABLE, monitor 40 determines at Step 470 whether the request identified at Step 420 was for a SLOW I/O-- INTERRUPT. SLOW I/O requests may have a delay until the I/O device becomes "ready". During the "make ready" operation, a continuous T(off) interval may be set up and executed to conserve power. Thus, if the request is not a SLOW I/O-- INTERRUPT, ACTIVITY branch 70 is exited after clearing the Busy-- A reentry flag (Step 390). If, however, the request is a SLOW I/O-- INTERRUPT, and time yet exists before the I/O device becomes "ready", monitor 40 then determines at Step 480 whether the I/O request is COMPLETE (i.e., is I/O device ready?). If the I/O device is not ready, monitor 40 forces T(off) to lengthen, thereby forcing the CPU to wait, or sleep, until the SLOW I/O device is ready. At this point it has time to save power and ACTIVITY branch 70 enters SAVE POWER subroutine 250 previously described in connection with to FIG. 2C. If, however, the I/O request is COMPLETE, control is returned to the operating system subsequently to monitor 40 exiting ACTIVITY branch 70 after clearing Busy-- A reentry flag (Step 390).
Self-tuning is inherent within the control system of continuous feedback loops. The software of the present invention can detect when CPU activity is low and therefore when the power conservation aspect of the present invention may be activated. Once the power conservation monitor is activated, a prompt return to full speed CPU clock operation within the interval is achieved so as to not degrade the performance of the computer. To achieve this prompt return to full speed CPU clock operation, the preferred embodiment of the present invention employs some associated hardware.
Looking now at FIG. 3 which shows a simplified schematic diagram representing the associated hardware employed by the present invention for active power conservation. When monitor 40 (not shown) determines the CPU is ready to sleep, it writes to an I/O port (not shown) which causes a pulse on the SLEEP line. The rising edge of this pulse on the SLEEP line causes flip flop 500 to clock a high to Q and a low to Q-. This causes the AND/OR logic (AND gates 510, 520; OR gate 530) to select the pulses travelling the SLEEP CLOCK line from SLEEP CLOCK oscillator 540 to be sent to and used by the CPU CLOCK. SLEEP CLOCK oscillator 540 is a slower clock than the CPU clock used during normal CPU activity. The high coming from the Q of flip flop 500 ANDed (510) with the pulses coming from SLEEP CLOCK oscillator 540 is ORed (530) with the result of the low on the Q- of flip flop 500 ANDed (520) with the pulse generated along the HIGH SPEED CLOCK line by the HIGH SPEED CLOCK oscillator 550 to yield the CPU CLOCK. When the I/O port designates SLEEP CLOCK, the CPU CLOCK is then equal to the SLEEP CLOCK oscillator 540 value. If, on the other hand, an interrupt occurs, an interrupt- value clears flip flop 500, thereby forcing the AND/OR selector (comprising 510, 520 and 530) to choose the HIGH SPEED CLOCK value, and returns the CPU CLOCK value to the value coming from HIGH SPEED CLOCK oscillator 550. Therefore, during any power conservation operation on the CPU, the detection of any interrupt within the system will restore the CPU operation at full clock rate prior to vectoring and processing the interrupt.
It should be noted that the associated hardware needed, external to each of the CPUs for any given system, may be different based on the operating system used, whether the CPU can be stopped, etc. Nevertheless, the scope of the present invention should not be limited by possible system specific modifications needed to permit the present invention to actively conserve power in the numerous available portable computer systems. For example two actual implementations are shown in FIGS. 4 and 5, discussed below.
Many VSLI designs today allow for clock switching of the CPU speed. The logic to switch from a null clock or slow clock to a fast clock logic is the same as that which allows the user to change speeds by a keyboard command. The added logic of monitor 40 working with such switching logic, causes an immediate return to a fast clock upon detection of any interrupt. This simple logic is the key to the necessary hardware support to interrupt the CPU and thereby allow the processing of the interrupt at full speed.
The method to reduce power consumption under MS-DOS employs the MS-DOS IDLE loop trap to gain access to the "do nothing" loop. The IDLE loop provides special access to application software and operating system operations that are in a state of IDLE or low activity Careful examination is required to determine the activity level at any given point within the system. Feedback loops are used from the interrupt 21H service request to determine the activity level. The prediction of activity level is determined by interrupt 21H requests, from which the present invention thereby sets the slice periods for "sleeping" (slowing down or stopping) the CPU. An additional feature allows the user to modify the slice depending on the activity level of interrupt 21H.
Looking now at FIG. 4, which depicts a schematic of an actual sleep hardware implementation for a system such as the Intel 80386 (CPU cannot have its clock stopped). Address enable bus 600 and address bus 610 provide CPU input to demultiplexer 620. The output of demultiplexer 620 is sent along SLEEPCS- and provided as input to OR gates 630,640. The other inputs to OR gates 630,640 are the I/O write control line and the I/O read control line, respectively. The outputs of these gates, in addition to NOR gate 650, are applied to D flip flop 660 to decode the port. "INTR" is the interrupt input from the I/O port (peripherals) into NOR gate 650, which causes the logic hardware to switch back to the high speed clock. The output of flip flop 660 is then fed, along with the output from OR gate 630, to tristate buffer 670 to enable it to read back what is on the port. All of the above-identified hardware is used by the read/write I/O port (peripherals) to select the power saving "Sleep" operation. The output "SLOW-" is equivalent to "SLEEP" in FIG. 2, and is inputted to flip flop 680, discussed later.
The output of SLEEP CLOCK oscillator 690 is divided into two slower clocks by D flip flops 700,710. In the particular implementation shown in FIG. 4, 16 MHz sleep clock oscillator 690 is divided into 4 MHz and 8 MHz clocks. Jumper Jl selects which clock is to be the "SLEEP CLOCK".
In this particular implementation, high speed clock oscillator 720 is a 32 MHz oscillator, although this particular speed is not a requirement of the present invention. The 32 MHz oscillator is put in series with a resistor (for the implementation shown, 33 ohms), which is in series with two parallel capacitors (10 pF). The result of such oscillations is tied to the clocks of D flip flops 730,740.
D flip flops 680,730,740 are synchronizing flip flops; 680,730 were not shown in the simplified sleep hardware of FIG. 2. These flip flops are used to ensure the clock switch occurs only on clock edge. As can be seen in FIG. 4, as with flip flop 500 of FIG. 2, the output of flip flop 740 either activates OR gate 750 or OR gate 760, depending upon whether the CPU is to sleep ("FASTEN-") or awaken ("SLOWEN-").
OR gates 750,760 and AND gate 770 are the functional equivalents to the AND/OR selector of FIG. 2. They are responsible for selecting either the "slowclk" (slow clock, also known as SLEEP CLOCK) or high speed clock (designated as 32 MHz on the incoming line). In this implementation, the Slow clock is either 4 MHz or 8 MHz, depending upon jumper Jl, and the high speed clock is 32 MHz. The output of AND gate 770 (ATUCLK) establishes the rate of the CPU clock, and is the equivalent of CPU CLOCK of FIG. 2.
Consider now FIG. 5, which depicts a schematic of another actual sleep hardware implementation for a system such as the Intel 80286 (CPU can have its clock stopped). The Western Digital FE3600 VLSI is used for the speed switching with a special external PAL 780 to control the interrupt gating which wakes up the CPU on any interrupt. The software power conservation according to the present invention monitors the interrupt acceptance, activating the next P(i)deltaTi interval after the interrupt.
Any interrupt request to the CPU will return the system to normal operation. An interrupt request ("INTRQ") to the CPU will cause the PAL to issue a Wake Up signal on the RESCPU line to the FE3001 (not shown) which in turn enables the CPU and the DMA clocks to bring the system back to its normal state. This is the equivalent of the "INTERRUPT-" of FIG. 2. Interrupt Request is synchronized to avoid confusing the state machine so that Interrupt (INTDET) will only be detected while the cycle is active. The rising edge of RESCPU will wake up the FE 3001 which in turn releases the whole system from the Sleep Mode.
Implementation for the 386SX is different only in the external hardware and software power conservation loop. The software loop will set external hardware to switch to the high speed clock on interrupt prior to vectoring the interrupt. Once return is made to the power conservation software, the high speed clock cycle will be detected and the hardware will be reset for full clock operation.
Implementation for OS/2 uses the "do nothing" loop programmed as a THREAD running in background operation with low priority. Once the THREAD is activated, the CPU sleep, or low speed clock, operation will be activated until an interrupt occurs thereby placing the CPU back to the original clock rate.
Although interrupts have been employed to wake up the CPU in the preferred embodiment of the present invention, it should be realized that any periodic activity within the system, or applied to the system, could also be used for the same function.
While several implementations of the preferred embodiment of the invention has been shown and described, various modifications and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3453601 *||18 Oct 1966||1 Jul 1969||Philco Ford Corp||Two speed arithmetic calculator|
|US3941989 *||13 Dec 1974||2 Mar 1976||Mos Technology, Inc.||Reducing power consumption in calculators|
|US4267577 *||26 Apr 1979||12 May 1981||Sharp Kabushiki Kaisha||Low power consumption integrated circuit for a combined timepiece and calculator|
|US4279020 *||18 Aug 1978||14 Jul 1981||Bell Telephone Laboratories, Incorporated||Power supply circuit for a data processor|
|US4293927 *||12 Dec 1979||6 Oct 1981||Casio Computer Co., Ltd.||Power consumption control system for electronic digital data processing devices|
|US4381552 *||18 Nov 1980||26 Apr 1983||Motorola Inc.||Stanby mode controller utilizing microprocessor|
|US4409665 *||26 Dec 1979||11 Oct 1983||Texas Instruments Incorporated||Turn-off-processor between keystrokes|
|US4670837 *||25 Jun 1984||2 Jun 1987||American Telephone And Telegraph Company||Electrical system having variable-frequency clock|
|US4686386 *||18 Mar 1985||11 Aug 1987||Oki Electric Industry Co., Ltd.||Power-down circuits for dynamic MOS integrated circuits|
|US4698748 *||7 Oct 1983||6 Oct 1987||Essex Group, Inc.||Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system inactivity|
|US4851987 *||17 Jan 1986||25 Jul 1989||International Business Machines Corporation||System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur|
|US4980836 *||14 Oct 1988||25 Dec 1990||Compaq Computer Corporation||Apparatus for reducing computer system power consumption|
|US5025387 *||1 Jun 1990||18 Jun 1991||Motorola, Inc.||Power saving arrangement for a clocked digital circuit|
|EP0472081A1 *||12 Aug 1991||26 Feb 1992||Hoechst Aktiengesellschaft||Carbonic acid groups containing copolymers, their preparation and their use as a thickener|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5339445 *||16 Nov 1992||16 Aug 1994||Harris Corporation||Method of autonomously reducing power consumption in a computer sytem by compiling a history of power consumption|
|US5355501 *||9 Mar 1990||11 Oct 1994||Novell, Inc.||Idle detection system|
|US5355503 *||13 Oct 1993||11 Oct 1994||National Semiconductor Corporation||Event driven scanning of data input equipment using multi-input wake-up techniques|
|US5394527 *||26 Oct 1993||28 Feb 1995||Zenith Data Systems Corporation||Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability|
|US5396635 *||12 Feb 1993||7 Mar 1995||Vadem Corporation||Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system|
|US5404459 *||21 Jul 1992||4 Apr 1995||Advanced Micro Devices||Serial interface module and method in which the clock is only activated to send a predetermined number of data bits|
|US5414861 *||11 Sep 1991||9 May 1995||Fujitsu Limited||Data protection system using different levels of reserve power to maintain data in volatile memories for any period of time|
|US5416726 *||6 Oct 1992||16 May 1995||Microsoft Corporation||Method and system for placing a computer in a reduced power state|
|US5418969 *||20 Jul 1994||23 May 1995||Matsushita Electric Industrial Co., Ltd.||Low power consumption microprocessor|
|US5430881 *||20 May 1992||4 Jul 1995||Dia Semicon Systems Incorporated||Supervisory control method and power saving control unit for computer system|
|US5432946 *||11 Apr 1991||11 Jul 1995||International Business Machines Corp.||LAN server personal computer with unattended activation capability|
|US5446904 *||4 Jun 1992||29 Aug 1995||Zenith Data Systems Corporation||Suspend/resume capability for a protected mode microprocessor|
|US5446906 *||30 Jun 1993||29 Aug 1995||Intel Corporation||Method and apparatus for suspending and resuming a keyboard controller|
|US5467042 *||8 Nov 1993||14 Nov 1995||Cirrus Logic, Inc.||Low power clocking apparatus and method|
|US5469553 *||16 Dec 1994||21 Nov 1995||Quantum Corporation||Event driven power reducing software state machine|
|US5471608 *||9 Dec 1993||28 Nov 1995||Pitney Bowes Inc.||Dynamically programmable timer-counter having enable mode for timer data load and monitoring circuit to allow enable mode only upon time-out|
|US5475848 *||5 Apr 1995||12 Dec 1995||Dia Semicon Systems, Incorporated||Supervisory control method and power saving control unit for computer system|
|US5485623 *||3 Mar 1994||16 Jan 1996||Hitachi, Ltd.||Information processor having high speed and safety resume system|
|US5504907 *||4 Mar 1993||2 Apr 1996||Dell Usa, L.P.||Power management system with adaptive control parameters for portable computer|
|US5504910 *||2 Feb 1994||2 Apr 1996||Advanced Micro Devices, Inc.||Power management unit including software configurable state register and time-out counters for protecting against misbehaved software|
|US5511201 *||25 Mar 1992||23 Apr 1996||Hitachi, Ltd.||Data processing apparatus, power supply controller and display unit|
|US5511203 *||2 Feb 1994||23 Apr 1996||Advanced Micro Devices||Power management system distinguishing between primary and secondary system activity|
|US5511204 *||7 Sep 1994||23 Apr 1996||International Business Machines Corporation||Performing system tasks at power-off using system management interrupt|
|US5515539 *||8 Jun 1994||7 May 1996||Mitsubishi Denki Kabushiki Kaisha||Apparatus and method for reducing power consumption by peripheral devices after downloading a program therefrom|
|US5537660 *||17 Nov 1994||16 Jul 1996||Intel Corporation||Microcontroller having selectable bus timing modes based on primary and secondary clocks for controlling the exchange of data with memory|
|US5542035 *||27 Oct 1993||30 Jul 1996||Elonex Technologies||Timer-controlled computer system shutdown and startup|
|US5544082 *||15 Feb 1995||6 Aug 1996||Microsoft Corporation||Method and system for placing a computer in a reduced power state|
|US5551033 *||4 Jun 1992||27 Aug 1996||Zenith Data Systems Corporation||Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program|
|US5560017 *||29 Apr 1994||24 Sep 1996||Wang Laboratories, Inc.||System with clock frequency controller responsive to interrupt independent of software routine and software loop repeatedly executing instruction to slow down system clock|
|US5560024 *||1 Feb 1995||24 Sep 1996||Fujitsu Personal Systems, Inc.||Computer power management system|
|US5566340 *||22 Jun 1994||15 Oct 1996||Dell Usa L.P.||Portable computer system with adaptive power control parameters|
|US5581297 *||24 Jul 1992||3 Dec 1996||Intelligent Instruments Corporation||Low power video security monitoring system|
|US5589923 *||24 Apr 1995||31 Dec 1996||Samsung Electronics Co., Ltd.||Power saving method of an image forming apparatus|
|US5603038 *||7 Sep 1994||11 Feb 1997||International Business Machines Corporation||Automatic restoration of user options after power loss|
|US5630008 *||28 Dec 1994||13 May 1997||Mitsumi Electric Co., Ltd.||Control circuit for driving motor with reduced power consumption and disk unit having the control circuit|
|US5652890 *||23 Dec 1993||29 Jul 1997||Vantus Technologies, Inc.||Interrupt for a protected mode microprocessor which facilitates transparent entry to and exit from suspend mode|
|US5659763 *||18 Nov 1996||19 Aug 1997||Mitsubishi Denki Kabushiki Kaisha||Apparatus and method for reducing power consumption by peripheral devices by controlling the interconnection of power supplies|
|US5666541 *||15 Oct 1996||9 Sep 1997||Compaq Computer Corporation||Reducing power usage in a personal computer|
|US5669004 *||2 Apr 1996||16 Sep 1997||Compaq Computer Corporation||Reducing power usage in a personal computer|
|US5691920 *||2 Oct 1995||25 Nov 1997||International Business Machines Corporation||Method and system for performance monitoring of dispatch unit efficiency in a processing system|
|US5710929 *||2 Jun 1995||20 Jan 1998||Vadem Corporation||Multi-state power management for computer systems|
|US5710933 *||31 Mar 1995||20 Jan 1998||International Business Machines Corporation||System resource enable apparatus|
|US5721936 *||24 Jul 1996||24 Feb 1998||Elonex I.P. Holdings||Timer-controlled computer system power management|
|US5727208 *||3 Jul 1995||10 Mar 1998||Dell U.S.A. L.P.||Method and apparatus for configuration of processor operating parameters|
|US5729726 *||2 Oct 1995||17 Mar 1998||International Business Machines Corporation||Method and system for performance monitoring efficiency of branch unit operation in a processing system|
|US5748855 *||2 Oct 1995||5 May 1998||Iinternational Business Machines Corporation||Method and system for performance monitoring of misaligned memory accesses in a processing system|
|US5751945 *||2 Oct 1995||12 May 1998||International Business Machines Corporation||Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system|
|US5752011 *||20 Jun 1994||12 May 1998||Thomas; C. Douglas||Method and system for controlling a processor's clock frequency in accordance with the processor's temperature|
|US5752044 *||7 Jun 1995||12 May 1998||International Business Machines Corporation||Computer system having multi-level suspend timers to suspend from operation in attended and unattended modes|
|US5752062 *||2 Oct 1995||12 May 1998||International Business Machines Corporation||Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system|
|US5754436 *||6 Nov 1996||19 May 1998||Texas Instruments Incorporated||Adaptive power management processes, circuits and systems|
|US5754867 *||20 Mar 1996||19 May 1998||Vlsi Technology, Inc.||Method for optimizing performance versus power consumption using external/internal clock frequency ratios|
|US5758133 *||28 Dec 1995||26 May 1998||Vlsi Technology, Inc.||System and method for altering bus speed based on bus utilization|
|US5758175 *||17 Dec 1996||26 May 1998||Vadem||Multi-mode power switching for computer systems|
|US5765004 *||1 Jun 1995||9 Jun 1998||Vantus Technologies, Inc.||Suspend/resume capability for a protected mode microprocessor|
|US5771390 *||23 Aug 1996||23 Jun 1998||Dell Usa, L.P.||System and method for cascading from a power managed suspend state to a suspend-to-disk state in a computer system|
|US5784598 *||7 Jun 1995||21 Jul 1998||Texas Instruments Incorporated||Method and apparatus for changing processor clock rate|
|US5790609 *||4 Nov 1996||4 Aug 1998||Texas Instruments Incorporated||Apparatus for cleanly switching between various clock sources in a data processing system|
|US5797019 *||2 Oct 1995||18 Aug 1998||International Business Machines Corporation||Method and system for performance monitoring time lengths of disabled interrupts in a processing system|
|US5799198 *||2 Jun 1995||25 Aug 1998||Vadem Corporation||Activity monitor for computer system power management|
|US5828568 *||18 Sep 1997||27 Oct 1998||Canon Kabushiki Kaisha||Information processing apparatus, processing method thereof, and power supply control method therefor|
|US5867718 *||29 Nov 1995||2 Feb 1999||National Semiconductor Corporation||Method and apparatus for waking up a computer system via a parallel port|
|US5884085 *||27 Nov 1996||16 Mar 1999||Kabushiki Kaisha Toshiba||Portable computer having dedicated register group and peripheral controller bus between system bus and peripheral controller|
|US5886689 *||10 Jun 1997||23 Mar 1999||Seiko Epson Corporation||Computer system with video display controller having power saving modes|
|US5887179 *||11 Jun 1996||23 Mar 1999||Motorola, Inc.||System power saving means and method|
|US5892959 *||17 Dec 1996||6 Apr 1999||Vadem||Computer activity monitor providing idle thread and other event sensitive clock and power control|
|US5901322 *||8 Aug 1997||4 May 1999||National Semiconductor Corporation||Method and apparatus for dynamic control of clocks in a multiple clock processor, particularly for a data cache|
|US5903746 *||4 Nov 1996||11 May 1999||Texas Instruments Incorporated||Apparatus and method for automatically sequencing clocks in a data processing system when entering or leaving a low power state|
|US5903766 *||13 Jan 1997||11 May 1999||Packard Bell Nec, Inc.||Suspend/resume capability for a protected mode microprocessor|
|US5926404 *||12 Nov 1997||20 Jul 1999||Dell Usa, L.P.||Computer system with unattended operation power-saving suspend mode|
|US5930516 *||30 Apr 1997||27 Jul 1999||Texas Instruments Incorporated||Real time power conservation for computers|
|US5949971 *||2 Oct 1995||7 Sep 1999||International Business Machines Corporation||Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system|
|US5974261 *||9 May 1995||26 Oct 1999||Vantus Technology||Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability|
|US5974551 *||10 Oct 1996||26 Oct 1999||Samsung Electronics Co., Ltd.||Power supply device and a power supply method for a computer system|
|US5974557 *||18 Aug 1997||26 Oct 1999||Thomas; C. Douglass||Method and system for performing thermal and power management for a computer|
|US5983339 *||21 Aug 1995||9 Nov 1999||International Business Machines Corporation||Power down system and method for pipelined logic functions|
|US5983355 *||20 May 1996||9 Nov 1999||National Semiconductor Corporation||Power conservation method and apparatus activated by detecting specific fixed interrupt signals indicative of system inactivity and excluding prefetched signals|
|US5987614 *||17 Jun 1997||16 Nov 1999||Vadem||Distributed power management system and method for computer|
|US5995454 *||9 Jul 1997||30 Nov 1999||Kabushiki Kaisha Toshiba||Computer system with alarm power-on function and automatic starting method thereof|
|US5996084 *||17 Jan 1997||30 Nov 1999||Texas Instruments Incorporated||Method and apparatus for real-time CPU thermal management and power conservation by adjusting CPU clock frequency in accordance with CPU activity|
|US6006336 *||12 Apr 1993||21 Dec 1999||Texas Instruments Incorporated||Real-time power conservation for computers|
|US6016548 *||15 Jul 1997||18 Jan 2000||Kabushiki Kaisha Toshiba||Apparatus for controlling duty ratio of power saving of CPU|
|US6061803 *||15 Nov 1993||9 May 2000||International Microcircuits, Inc.||Variable frequency clock for an electronic system and method therefor|
|US6065138 *||7 Jan 1997||16 May 2000||Magnitude Llc||Computer activity monitoring system|
|US6079025 *||23 Jul 1998||20 Jun 2000||Vadem||System and method of computer operating mode control for power consumption reduction|
|US6088806 *||20 Oct 1998||11 Jul 2000||Seiko Epson Corporation||Apparatus and method with improved power-down mode|
|US6115823 *||18 Aug 1999||5 Sep 2000||Amphus, Inc.||System and method for task performance based dynamic distributed power management in a computer system and design method therefor|
|US6173409||8 Sep 1999||9 Jan 2001||Texas Instruments Incorporated||Real-time power conservation for electronic device having a processor|
|US6188830||14 Jul 1997||13 Feb 2001||Sony Corporation||Audiovisual effects processing method and apparatus for instantaneous storage-based playback of audio data in synchronization with video data|
|US6192479||19 Jan 1995||20 Feb 2001||Texas Instruments Incorporated||Data processing with progressive, adaptive, CPU-driven power management|
|US6193422 *||22 Jun 1994||27 Feb 2001||Nec Corporation||Implementation of idle mode in a suspend/resume microprocessor system|
|US6216235||10 Jul 1999||10 Apr 2001||C. Douglass Thomas||Thermal and power management for computer systems|
|US6223293||16 Feb 1995||24 Apr 2001||Nec Corporation||Suspend/resume capability for a protected mode microprocessor|
|US6256743 *||29 Apr 1998||3 Jul 2001||Seiko Epson Corporation||Selective power-down for high performance CPU/system|
|US6282662 *||4 Aug 1995||28 Aug 2001||Dell Usa, L.P.||Power management override for portable computers|
|US6298448||21 Dec 1998||2 Oct 2001||Siemens Information And Communication Networks, Inc.||Apparatus and method for automatic CPU speed control based on application-specific criteria|
|US6300946 *||29 May 1998||9 Oct 2001||Palm, Inc.||Method and apparatus for interacting with a portable computer|
|US6301673||23 Jan 1997||9 Oct 2001||Nec Corporation||Suspend/resume capability for a protected mode microprocessor|
|US6324651||12 Nov 1998||27 Nov 2001||International Business Machines Corporation||Method and apparatus for saving device state while a computer system is in sleep mode|
|US6345363||23 Jun 1998||5 Feb 2002||National Semiconductor Corporation||Microprocessor core power reduction by not reloading existing operands|
|US6378068||1 Jun 1995||23 Apr 2002||Nec Corporation||Suspend/resume capability for a protected mode microprocesser|
|US6397340||9 Jan 2001||28 May 2002||Texas Instruments Incorporated||Real-time power conservation for electronic device having a processor|
|US6438697||27 Mar 2001||20 Aug 2002||Compaq Information Technologies Group, L.P.||Demand-based processor clock frequency switching|
|US6448988||19 Mar 1999||10 Sep 2002||Palm, Inc.||Method and apparatus for interacting with a portable computer system|
|US6484041||6 Oct 1999||19 Nov 2002||Nokia Mobile Phones, Ltd.||Method for adjusting power consumption|
|US6487668||12 Feb 2001||26 Nov 2002||C. Douglass Thomas||Thermal and power management to computer systems|
|US6574739 *||14 Apr 2000||3 Jun 2003||Compal Electronics, Inc.||Dynamic power saving by monitoring CPU utilization|
|US6584571||25 Apr 2000||24 Jun 2003||St. Clair Intellectual Property Consultants, Inc.||System and method of computer operating mode clock control for power consumption reduction|
|US6609211||20 Aug 2002||19 Aug 2003||Hewlett-Packard Development Company, L.P.||Utilization-based power management of a clocked device|
|US6611921||26 Nov 2001||26 Aug 2003||Microsoft Corporation||Input device with two input signal generating means having a power state where one input means is powered down and the other input means is cycled between a powered up state and a powered down state|
|US6622253||2 Aug 2001||16 Sep 2003||Scientific-Atlanta, Inc.||Controlling processor clock rate based on thread priority|
|US6633988||11 Feb 2002||14 Oct 2003||Texas Instruments Incorporated||Processor having real-time power conservation|
|US6661410||7 Sep 2001||9 Dec 2003||Microsoft Corporation||Capacitive sensing and data input device power management|
|US6665802||29 Feb 2000||16 Dec 2003||Infineon Technologies North America Corp.||Power management and control for a microcontroller|
|US6694442 *||18 Dec 2000||17 Feb 2004||Asustek Computer Inc.||Method for saving power in a computer by idling system controller and reducing frequency of host clock signal used by system controller|
|US6694443||8 Feb 2001||17 Feb 2004||National Semiconductor Corporation||System for controlling power of a microprocessor by asserting and de-asserting a control signal in response to condition associated with the microprocessor entering and exiting low power state respectively|
|US6694451||7 Dec 2000||17 Feb 2004||Hewlett-Packard Development Company, L.P.||Method for redundant suspend to RAM|
|US6703599||30 Jan 2002||9 Mar 2004||Microsoft Corporation||Proximity sensor with adaptive threshold|
|US6720673 *||11 Apr 2001||13 Apr 2004||International Business Machines Corporation||Voltage island fencing|
|US6721894||9 Aug 2002||13 Apr 2004||National Semiconductor Corporation||Method for controlling power of a microprocessor by asserting and de-asserting a control signal in response conditions associated with the microprocessor entering and exiting low power state respectively|
|US6732283||28 Feb 2003||4 May 2004||Texas Instruments Incorporated||Processor having real-time power conservation|
|US6732284||28 Feb 2003||4 May 2004||Texas Instruments Incorporated||Processor having real-time power conservation|
|US6813674||12 May 2000||2 Nov 2004||St. Clair Intellectual Property Consultants, Inc.||Dual-edge fifo interface|
|US6816150||26 Nov 2001||9 Nov 2004||Microsoft Corporation||Data input device power management including beacon state|
|US6848054 *||13 Dec 1995||25 Jan 2005||Texas Instruments Incorporated||Real-time computer thermal management and power conservation|
|US6850229||26 Nov 2001||1 Feb 2005||Microsoft Corporation||Capacitive sensing and data input device power management|
|US6859882 *||18 May 2001||22 Feb 2005||Amphus, Inc.||System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment|
|US6865684||7 Jul 2003||8 Mar 2005||Hewlett-Packard Development Company, L.P.||Utilization-based power management of a clocked device|
|US6895448||29 May 2001||17 May 2005||O2 Micro, Inc.||Low-power audio CD player for portable computers|
|US6901524 *||26 Mar 2002||31 May 2005||Texas Instruments Incorporated||Processor having real-time power conservation and thermal management|
|US6910139||7 Feb 2001||21 Jun 2005||Fujitsu Limited||Software processing apparatus with a switching processing unit for displaying animation images in an environment operating base on type of power supply|
|US6910141||23 Feb 2004||21 Jun 2005||National Semiconductor Corporation||Pipelined data processor with signal-initiated power management control|
|US6924667||19 Jul 2002||2 Aug 2005||O2Micro International Limited||Level shifting and level-shifting amplifier circuits|
|US6930515||2 Sep 2004||16 Aug 2005||O2 Micro International Limited||Level shifting and level shifting amplifier circuits|
|US6933922||9 Jan 2004||23 Aug 2005||Microsoft Corporation||Proximity sensor with adaptive threshold|
|US6954804||28 Mar 2003||11 Oct 2005||Micro, Inc.||Controller for portable electronic devices|
|US6954867||26 Jul 2002||11 Oct 2005||Microsoft Corporation||Capacitive sensing employing a repeatable offset charge|
|US6978390||23 Feb 2004||20 Dec 2005||National Semiconductor Corporation||Pipelined data processor with instruction-initiated power management control|
|US6995747||5 Nov 2004||7 Feb 2006||Microsoft Corporation||Capacitive sensing and data input device power management|
|US6996784||10 May 2002||7 Feb 2006||Palmsource, Inc.||Method and apparatus for interacting with a portable computer system|
|US7000132||23 Feb 2004||14 Feb 2006||National Semiconductor Corporation||Signal-initiated power management method for a pipelined data processor|
|US7002550||11 Feb 2005||21 Feb 2006||Microsoft Corporation||Proximity sensor with adaptive threshold|
|US7023425||5 Nov 2004||4 Apr 2006||Microsoft Corporation||Data input device power management including beacon state|
|US7028198||30 Apr 2004||11 Apr 2006||Texas Instruments Incorporated||Processor having real-time power conservation|
|US7032119||18 May 2001||18 Apr 2006||Amphus, Inc.||Dynamic power and workload management for multi-server system|
|US7038506 *||23 Mar 2004||2 May 2006||Stmicroelectronics Pvt. Ltd.||Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system|
|US7058826||4 Oct 2004||6 Jun 2006||Amphus, Inc.||System, architecture, and method for logical server and other network devices in a dynamically configurable multi-server network environment|
|US7062666||23 Feb 2004||13 Jun 2006||National Semiconductor Corporation||Signal-initiated method for suspending operation of a pipelined data processor|
|US7100061||18 Jan 2000||29 Aug 2006||Transmeta Corporation||Adaptive power control|
|US7111179||11 Oct 2002||19 Sep 2006||In-Hand Electronics, Inc.||Method and apparatus for optimizing performance and battery life of electronic devices based on system and application parameters|
|US7112978||30 Sep 2004||26 Sep 2006||Transmeta Corporation||Frequency specific closed loop feedback control of integrated circuits|
|US7114086||27 Feb 2002||26 Sep 2006||Ati Technologies, Inc.||System for reduced power consumption by monitoring instruction buffer and method thereof|
|US7120810||23 Feb 2004||10 Oct 2006||National Semiconductor Corporation||Instruction-initiated power management method for a pipelined data processor|
|US7124312||30 Jun 2005||17 Oct 2006||Microsoft Corporation||Capacitive sensing employing a repeatable offset charge|
|US7134011||18 May 2001||7 Nov 2006||Huron Ip Llc||Apparatus, architecture, and method for integrated modular server system providing dynamically power-managed and work-load managed network devices|
|US7167993||22 Oct 2002||23 Jan 2007||Thomas C Douglass||Thermal and power management for computer systems|
|US7180322||30 Sep 2004||20 Feb 2007||Transmeta Corporation||Closed loop feedback control of integrated circuits|
|US7194646 *||7 Dec 1995||20 Mar 2007||Texas Instruments Incorporated||Real-time thermal management for computers|
|US7228242||31 Dec 2002||5 Jun 2007||Transmeta Corporation||Adaptive power control based on pre package characterization of integrated circuits|
|US7228441||18 May 2001||5 Jun 2007||Huron Ip Llc||Multi-server and multi-CPU power management system and method|
|US7254721 *||7 Jun 2001||7 Aug 2007||Advanced Micro Devices, Inc.||System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit|
|US7260731||23 Oct 2000||21 Aug 2007||Transmeta Corporation||Saving power when in or transitioning to a static mode of a processor|
|US7272735||28 Feb 2006||18 Sep 2007||Huron Ip Llc||Dynamic power and workload management for multi-server system|
|US7284139||3 May 2005||16 Oct 2007||Texas Instruments Incorporated||Processor having real-time power conservation|
|US7290246 *||19 Dec 2002||30 Oct 2007||Texas Instruments Incorporated||Power profiling system and method for correlating runtime information|
|US7293186||17 Jan 2007||6 Nov 2007||Thomas C Douglass||Thermal and power management for computer systems|
|US7336090 *||29 Aug 2006||26 Feb 2008||Transmeta Corporation||Frequency specific closed loop feedback control of integrated circuits|
|US7336092 *||19 Jul 2006||26 Feb 2008||Transmeta Corporation||Closed loop feedback control of integrated circuits|
|US7363408 *||30 Nov 2004||22 Apr 2008||Via Technologies, Inc.||Interruption control system and method|
|US7386647 *||14 Oct 2005||10 Jun 2008||Dell Products L.P.||System and method for processing an interrupt in a processor supporting multithread execution|
|US7386858||18 Jul 2003||10 Jun 2008||Access Systems Americas, Inc.||Method and apparatus for unified external and interprocess communication|
|US7389438||25 May 2005||17 Jun 2008||Texas Instruments Incorporated||Method for detecting temperature and activity associated with a processor and using the results for controlling power dissipation associated with a processor|
|US7392416||6 May 2005||24 Jun 2008||Texas Instruments Incorporated||Method for controlling power consumption associated with a processor|
|US7418611||20 Sep 2006||26 Aug 2008||Thomas C Douglass||Thermal and power management for computer systems|
|US7421600 *||29 Jul 2005||2 Sep 2008||Silicon Integrated Systems Corp.||Power saving method|
|US7444439||9 Sep 2003||28 Oct 2008||02 Micro International Limited||Audio controller for portable electronic devices|
|US7469387||5 Apr 2005||23 Dec 2008||Access Systems Americas, Inc.||Method and apparatus for interacting with a portable computer system|
|US7479944||11 Feb 2005||20 Jan 2009||Microsoft Corporation||Proximity sensor with adaptive threshold|
|US7484111||28 Feb 2006||27 Jan 2009||Huron Ip Llc||Power on demand and workload management system and method|
|US7487470||12 Sep 2005||3 Feb 2009||Access Systems Americas, Inc.||Method and apparatus for interacting with a portable computer system|
|US7489177 *||5 Jun 2006||10 Feb 2009||Research In Motion Limited||Clock circuit for a microprocessor|
|US7506190||22 Jun 2007||17 Mar 2009||Thomas C Douglass||Thermal and power management for computer systems|
|US7509512||23 Feb 2004||24 Mar 2009||National Semiconductor Corporation||Instruction-initiated method for suspending operation of a pipelined data processor|
|US7512822||28 Feb 2006||31 Mar 2009||Huron Ip Llc||System and method for activity or event based dynamic energy conserving server reconfiguration|
|US7522964||2 Oct 2001||21 Apr 2009||O2Micro International Limited||Low power digital audio decoding/playing system for computing devices|
|US7522965||30 Jul 2002||21 Apr 2009||O2Micro International Limited||Low power digital audio decoding/playing system for computing devices|
|US7522966||17 Oct 2002||21 Apr 2009||O2Micro International Limited||Low power digital audio decoding/playing system for computing devices|
|US7526349||2 Aug 2001||28 Apr 2009||O2Micro International Limited||Low power digital audio decoding/playing system for computing devices|
|US7533283||28 Feb 2006||12 May 2009||Huron Ip Llc||Apparatus and method for modular dynamically power managed power supply and cooling system for computer systems, server applications, and other electronic devices|
|US7549071||3 May 2005||16 Jun 2009||Texas Instruments Incorporated||Method for providing real-time power conservation in a processor|
|US7552350||24 Apr 2007||23 Jun 2009||Huron Ip Llc||System and method for activity or event base dynamic energy conserving server reconfiguration|
|US7558976||28 Feb 2006||7 Jul 2009||Huron Ip Llc||System, method, architecture, and computer program product for dynamic power management in a computer system|
|US7562233||22 Jun 2004||14 Jul 2009||Transmeta Corporation||Adaptive control of operating and body bias voltages|
|US7562239||28 Feb 2006||14 Jul 2009||Huron Ip Llc||System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment|
|US7587262||7 Nov 2000||8 Sep 2009||Intel Corporation||Temperature averaging thermal sensor apparatus and method|
|US7596708||25 Apr 2006||29 Sep 2009||Sameer Halepete||Adaptive power control|
|US7598731||17 Apr 2007||6 Oct 2009||Robert Paul Masleid||Systems and methods for adjusting threshold voltage|
|US7626409||26 Sep 2006||1 Dec 2009||Koniaris Kleanthes G||Frequency specific closed loop feedback control of integrated circuits|
|US7642835||12 Nov 2003||5 Jan 2010||Robert Fu||System for substrate potential regulation during power-up in integrated circuits|
|US7647513||3 Jul 2007||12 Jan 2010||Advanced Micro Devices, Inc.||Method and apparatus for improving responsiveness of a power management system in a computing device|
|US7649402||23 Dec 2003||19 Jan 2010||Tien-Min Chen||Feedback-controlled body-bias voltage source|
|US7692477||23 Dec 2003||6 Apr 2010||Tien-Min Chen||Precise control component for a substrate potential regulation circuit|
|US7719344||21 Feb 2006||18 May 2010||Tien-Min Chen||Stabilization component for a substrate potential regulation circuit|
|US7721125||7 Feb 2006||18 May 2010||Huron Ip, Llc||System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment|
|US7730330||10 Aug 2005||1 Jun 2010||Marc Fleischmann||System and method for saving and restoring a processor state without executing any instructions from a first instruction set|
|US7739531||4 Mar 2005||15 Jun 2010||Nvidia Corporation||Dynamic voltage scaling|
|US7761274||7 Nov 2000||20 Jul 2010||Intel Corporation||Temperature-based clock frequency controller apparatus and method|
|US7774625||22 Jun 2004||10 Aug 2010||Eric Chien-Li Sheng||Adaptive voltage control by accessing information stored within and specific to a microprocessor|
|US7782110||19 Jul 2007||24 Aug 2010||Koniaris Kleanthes G||Systems and methods for integrated circuits comprising multiple body bias domains|
|US7786756||30 Sep 2005||31 Aug 2010||Vjekoslav Svilan||Method and system for latchup suppression|
|US7808292||12 Jan 2009||5 Oct 2010||Research In Motion Limited||Clock circuit for a microprocessor|
|US7816742||6 Apr 2006||19 Oct 2010||Koniaris Kleanthes G||Systems and methods for integrated circuits comprising multiple body biasing domains|
|US7821489 *||30 Apr 2003||26 Oct 2010||Panasonic Corporation||Data processing apparatus|
|US7822967||24 Oct 2006||26 Oct 2010||Huron Ip Llc||Apparatus, architecture, and method for integrated modular server system providing dynamically power-managed and work-load managed network devices|
|US7822996||19 Mar 2007||26 Oct 2010||Texas Instruments Incorporated||Method for implementing thermal management in a processor and/or apparatus and/or system employing the same|
|US7847619||22 Apr 2008||7 Dec 2010||Tien-Min Chen||Servo loop for well bias voltage source|
|US7849332||30 May 2003||7 Dec 2010||Nvidia Corporation||Processor voltage adjustment system and method|
|US7859062||30 Sep 2004||28 Dec 2010||Koniaris Kleanthes G||Systems and methods for integrated circuits comprising multiple body biasing domains|
|US7870404||21 Aug 2007||11 Jan 2011||Andrew Read||Transitioning to and from a sleep state of a processor|
|US7882369||14 Nov 2002||1 Feb 2011||Nvidia Corporation||Processor performance adjustment system and method|
|US7886164||30 May 2003||8 Feb 2011||Nvidia Corporation||Processor temperature adjustment system and method|
|US7890741||3 Apr 2003||15 Feb 2011||O2Micro International Limited||Low power digital audio decoding/playing system for computing devices|
|US7900075||31 Oct 2007||1 Mar 2011||National Semiconductor Corporation||Pipelined computer system with power management control|
|US7900076||31 Oct 2007||1 Mar 2011||National Semiconductor Corporation||Power management method for a pipelined computer system|
|US7937599||25 Aug 2008||3 May 2011||Ipventure, Inc.||Thermal and power management for computer systems|
|US7941675||31 Dec 2002||10 May 2011||Burr James B||Adaptive power control|
|US7949864||28 Sep 2005||24 May 2011||Vjekoslav Svilan||Balanced adaptive body bias control|
|US7953990||31 Dec 2002||31 May 2011||Stewart Thomas E||Adaptive power control based on post package characterization of integrated circuits|
|US8022747||30 Nov 2009||20 Sep 2011||Robert Fu||System for substrate potential regulation during power-up in integrated circuits|
|US8040149||1 Sep 2009||18 Oct 2011||Koniaris Kleanthes G||Frequency specific closed loop feedback control of integrated circuits|
|US8074092||27 May 2009||6 Dec 2011||Huron Ip Llc||System, architecture, and method for logical server and other network devices in a dynamically configurable multi-server network environment|
|US8085084||30 Nov 2009||27 Dec 2011||Robert Fu||System for substrate potential regulation during power-up in integrated circuits|
|US8140872||10 Jun 2008||20 Mar 2012||Marc Fleischmann||Restoring processor context in response to processor power-up|
|US8193852||19 Feb 2010||5 Jun 2012||Tien-Min Chen||Precise control component for a substrate potential regulation circuit|
|US8222914||25 Aug 2009||17 Jul 2012||Robert Paul Masleid||Systems and methods for adjusting threshold voltage|
|US8319515||25 Aug 2009||27 Nov 2012||Robert Paul Masleid||Systems and methods for adjusting threshold voltage|
|US8354868||30 Aug 2010||15 Jan 2013||Research In Motion Limited||Clock circuit for a microprocessor|
|US8370658||14 Jul 2009||5 Feb 2013||Eric Chen-Li Sheng||Adaptive control of operating and body bias voltages|
|US8370663||11 Feb 2008||5 Feb 2013||Nvidia Corporation||Power management with dynamic frequency adjustments|
|US8420472||31 Aug 2010||16 Apr 2013||Kleanthes G. Koniaris||Systems and methods for integrated circuits comprising multiple body biasing domains|
|US8436675||11 Jan 2010||7 May 2013||Tien-Min Chen||Feedback-controlled body-bias voltage source|
|US8442784||5 Jun 2007||14 May 2013||Andrew Read||Adaptive power control based on pre package characterization of integrated circuits|
|US8566621||22 Oct 2010||22 Oct 2013||Texas Instruments Incorporated||Method for implementing thermal management in a processor and/or apparatus and/or system employing the same|
|US8566627||14 Jul 2009||22 Oct 2013||Sameer Halepete||Adaptive power control|
|US8593169||16 Sep 2011||26 Nov 2013||Kleanthes G. Koniaris||Frequency specific closed loop feedback control of integrated circuits|
|US8629711||1 May 2012||14 Jan 2014||Tien-Min Chen||Precise control component for a substarate potential regulation circuit|
|US8697512||14 Dec 2010||15 Apr 2014||Kleanthes G. Koniaris||Systems and methods for integrated circuits comprising multiple body biasing domains|
|US8700923||3 Feb 2009||15 Apr 2014||Huron Ip Llc||Apparatus and method for modular dynamically power managed power supply and cooling system for computer systems, server applications, and other electronic devices|
|US8725488||26 Jul 2007||13 May 2014||Qualcomm Incorporated||Method and apparatus for adaptive voltage scaling based on instruction usage|
|US8749290||12 Dec 2012||10 Jun 2014||Blackberry Limited||Clock circuit for a microprocessor|
|US8775843||4 Feb 2013||8 Jul 2014||Nvidia Corporation||Power management with dynamic frequency adjustments|
|US8806247||21 Dec 2012||12 Aug 2014||Intellectual Venture Funding Llc||Adaptive power control|
|US8839006||28 May 2010||16 Sep 2014||Nvidia Corporation||Power consumption reduction systems and methods|
|US8862924||15 Nov 2011||14 Oct 2014||Advanced Micro Devices, Inc.||Processor with power control via instruction issuance|
|US9021283||30 Apr 2004||28 Apr 2015||Texas Instruments Incorporated||Processor having real-time power conservation|
|US9026810||31 Dec 2012||5 May 2015||Intellectual Venture Funding Llc||Adaptive control of operating and body bias voltages|
|US9100003||16 Jul 2012||4 Aug 2015||Robert Paul Masleid||Systems and methods for adjusting threshold voltage|
|US9134782||7 May 2007||15 Sep 2015||Nvidia Corporation||Maintaining optimum voltage supply to match performance of an integrated circuit|
|US9256265||30 Dec 2009||9 Feb 2016||Nvidia Corporation||Method and system for artificially and dynamically limiting the framerate of a graphics processing unit|
|US9395784 *||25 Apr 2013||19 Jul 2016||Intel Corporation||Independently controlling frequency of plurality of power domains in a processor system|
|US9407241||16 Aug 2012||2 Aug 2016||Kleanthes G. Koniaris||Closed loop feedback control of integrated circuits|
|US9436264||10 Jan 2011||6 Sep 2016||Intellectual Ventures Holding 81 Llc||Saving power when in or transitioning to a static mode of a processor|
|US9548725||26 Nov 2013||17 Jan 2017||Intellectual Ventures Holding 81 Llc||Frequency specific closed loop feedback control of integrated circuits|
|US9571070||7 May 2014||14 Feb 2017||Blackberry Limited||Clock circuit for a microprocessor|
|US9575554||15 Dec 2015||21 Feb 2017||International Business Machines Corporation||Dynamic time sliced sensor sampling for reduced power consumption|
|US9612653||3 Sep 2015||4 Apr 2017||Freescale Semiconductor, Inc.||Integrated circuit with selectable power-on reset mode|
|US20010016917 *||14 Feb 2001||23 Aug 2001||Soren Haubold||Method and configuration for supplying a clock signal to processor-controlled apparatuses|
|US20020004912 *||18 May 2001||10 Jan 2002||Amphus, Inc.||System, architecture, and method for logical server and other network devices in a dynamically configurable multi-server network environment|
|US20020004913 *||18 May 2001||10 Jan 2002||Amphus, Inc.||Apparatus, architecture, and method for integrated modular server system providing dynamically power-managed and work-load managed network devices|
|US20020007463 *||18 May 2001||17 Jan 2002||Amphus, Inc.||Power on demand and workload management system and method|
|US20020040442 *||7 Feb 2001||4 Apr 2002||Nobutaka Ishidera||Software processing apparatus and recording medium on which program is recorded|
|US20020062454 *||18 May 2001||23 May 2002||Amphus, Inc.||Dynamic power and workload management for multi-server system|
|US20020068988 *||2 Aug 2001||6 Jun 2002||Reginia Chan||Low power digital audio decoding/playing system for computing devices|
|US20020078391 *||18 Dec 2000||20 Jun 2002||Shih-Ping Yeh||Power saving method and system for a computer|
|US20020099514 *||26 Mar 2002||25 Jul 2002||Watts La Vaughn F.||Processor having real-time power conservation and thermal management|
|US20020138778 *||22 Mar 2001||26 Sep 2002||Cole James R.||Controlling CPU core voltage to reduce power consumption|
|US20030001909 *||10 May 2002||2 Jan 2003||Haitani Robert Yuji||Method and apparatus for interacting with a portable computer system|
|US20030036350 *||18 Dec 2000||20 Feb 2003||Annika Jonsson||Method and apparatus for selective service access|
|US20030046528 *||26 Jun 2002||6 Mar 2003||Haitani Robert Yuji||Method and apparatus for interacting with a portable computer system|
|US20030088326 *||17 Oct 2002||8 May 2003||Sterling Du||Low power digital audio decoding/playing system for computing devices|
|US20030131269 *||27 Feb 2002||10 Jul 2003||Carl Mizyuabu||System for reduced power consumption by monitoring instruction buffer and method thereof|
|US20030188208 *||18 May 2001||2 Oct 2003||Amphus, Inc.|
|US20030191976 *||19 Dec 2002||9 Oct 2003||Cyran Robert J.||Power profiling system and method for correlating runtime information|
|US20030193466 *||30 Apr 2003||16 Oct 2003||Mitsuaki Oshima||Data processing apparatus|
|US20030196126 *||11 Apr 2002||16 Oct 2003||Fung Henry T.|
|US20030200473 *||18 May 2001||23 Oct 2003||Amphus, Inc.||System and method for activity or event based dynamic energy conserving server reconfiguration|
|US20030212474 *||19 Jun 2003||13 Nov 2003||Intel Corporation||Method and apparatus for programmable thermal sensor for an integrated circuit|
|US20040006690 *||3 Apr 2003||8 Jan 2004||Sterling Du||Low power digital audio decoding/playing system for computing devices|
|US20040006720 *||7 Jul 2003||8 Jan 2004||Compaq Information Technologies Group, L.P., A Delaware Corporation||Utilization-based power management of a clocked device|
|US20040024931 *||28 Mar 2003||5 Feb 2004||James Lam||Controller for portable electronic devices|
|US20040128090 *||31 Dec 2002||1 Jul 2004||Andrew Read||Adaptive power control based on pre package characterization of integrated circuits|
|US20040142705 *||9 Jan 2004||22 Jul 2004||Microsoft Corporation||Proximity sensor with adaptive threshold|
|US20040172567 *||23 Feb 2004||2 Sep 2004||Robert Maher||Signal-initiated power management method for a pipelined data processor|
|US20040172568 *||23 Feb 2004||2 Sep 2004||Robert Maher||Signal-initiated method for suspending operation of a pipelined data processor|
|US20040172572 *||23 Feb 2004||2 Sep 2004||Robert Maher||Pipelined data processor with signal-initiated power management control|
|US20040225906 *||30 Apr 2004||11 Nov 2004||Watts Lavaughn F.||Real-time power conservation for portable computers|
|US20040225908 *||30 Apr 2004||11 Nov 2004||Watts Lavaughn F.||Processor having real-time power conservation|
|US20040230852 *||23 Feb 2004||18 Nov 2004||Robert Maher||Pipelined data processor with instruction-initiated power management control|
|US20050024087 *||2 Sep 2004||3 Feb 2005||Liusheng Liu||Level shifting and level-shifting amplifier circuits|
|US20050024802 *||23 Feb 2004||3 Feb 2005||Robert Maher||Instruction-initiated power management method for a pipelined data processor|
|US20050036261 *||23 Feb 2004||17 Feb 2005||Robert Maher||Instruction-initiated method for suspending operation of a pipelined data pocessor|
|US20050078085 *||5 Nov 2004||14 Apr 2005||Microsoft Corporation||Data input device power management including beacon state|
|US20050120154 *||30 Nov 2004||2 Jun 2005||Via Technologies, Inc.||Interruption control system and method|
|US20050146499 *||11 Feb 2005||7 Jul 2005||Microsoft Corporation||Proximity sensor with adaptive threshold|
|US20050168438 *||5 Nov 2004||4 Aug 2005||Microsoft Corporation||Capacitive sensing and data input device power management|
|US20050198543 *||3 May 2005||8 Sep 2005||Watts Lavaughn F.Jr.||Processor having real-time power conservation|
|US20050200603 *||11 Feb 2005||15 Sep 2005||Microsoft Corporation||Proximity sensor with adaptive threshold|
|US20050204177 *||3 May 2005||15 Sep 2005||Watts Lavaughn F.Jr.||Method for providing real-time power conservation in a processor|
|US20050204178 *||6 May 2005||15 Sep 2005||Watts Lavaughn F.Jr.||Method for controlling power consumption associated with a processor|
|US20050204179 *||6 May 2005||15 Sep 2005||Watts Lavauchn F.Jr.||Method for controlling power consumption associated with a processor|
|US20050212571 *||23 Mar 2004||29 Sep 2005||Stmicroelectronics Pvt. Ltd.||Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system|
|US20050223254 *||25 May 2005||6 Oct 2005||Watts La Vaughn F Jr||Method for implementing thermal and power management in a processor and/or apparatus and/or system employing the same|
|US20050223255 *||25 May 2005||6 Oct 2005||Watts La Vaughn F Jr||Method for implementing thermal and power management in a processor and/or apparatus and/or system employing the same|
|US20050223256 *||25 May 2005||6 Oct 2005||Watts La Vaughn F Jr||Method for implementing thermal and power management in a processor and/or apparatus and/or system employing the same|
|US20050223257 *||25 May 2005||6 Oct 2005||Watts La Vaughn F Jr||Processor employing implementing real-time power conservation and thermal management|
|US20050223258 *||27 May 2005||6 Oct 2005||Watts La V F Jr||Apparatus employing real-time power conservation and thermal management|
|US20050240785 *||30 Jun 2005||27 Oct 2005||Microsoft Corporation||Capacitive sensing employing a repeatable offset charge|
|US20060080475 *||8 Jun 2005||13 Apr 2006||O2Micro Inc||Controller for portable electronic devices|
|US20060101175 *||9 Sep 2003||11 May 2006||Du Sterling S||Audio controller for portable electronic devices|
|US20060163633 *||27 Mar 2006||27 Jul 2006||Cem Basceri||Dielectric relaxation memory|
|US20060229033 *||5 Jun 2006||12 Oct 2006||Carragher Mark A J||Clock circuit for a microprocessor|
|US20060248325 *||28 Feb 2006||2 Nov 2006||Fung Henry T||Apparatus and method for modular dynamically power managed power supply and cooling system for computer systems, server applications, and other electronic devices|
|US20060248359 *||28 Feb 2006||2 Nov 2006||Fung Henry T||Power on demand and workload management system and method|
|US20060248360 *||28 Feb 2006||2 Nov 2006||Fung Henry T||Multi-server and multi-CPU power management system and method|
|US20060248361 *||28 Feb 2006||2 Nov 2006||Fung Henry T||Dynamic power and workload management for multi-server system|
|US20060253717 *||28 Feb 2006||9 Nov 2006||Fung Henry T||System and method for activity or event based dynamic energy conserving server reconfiguration|
|US20060259796 *||7 Feb 2006||16 Nov 2006||Fung Henry T|
|US20060259797 *||28 Feb 2006||16 Nov 2006||Fung Henry T||System, method, architecture, and computer program product for dynamic power management in a computer system|
|US20060265608 *||28 Feb 2006||23 Nov 2006||Fung Henry T|
|US20060282601 *||31 May 2006||14 Dec 2006||Kabushiki Kaisha Toshiba||Information processing apparatus and power-saving controlling method|
|US20070028128 *||29 Jul 2005||1 Feb 2007||Silicon Integrated Systems Corp.||Power saving method|
|US20070088887 *||14 Oct 2005||19 Apr 2007||Dell Products L.P.||System and method for processing an interrupt in a processor supporting multithread execution|
|US20070101173 *||24 Oct 2006||3 May 2007||Fung Henry T|
|US20070118774 *||17 Jan 2007||24 May 2007||Thomas C D||Thermal and power management for computer systems|
|US20070240003 *||19 Mar 2007||11 Oct 2007||Watts Lavaughn F Jr||Method For Implementing Thermal Management In A Processor And/Or Apparatus And/Or System Employing The Same|
|US20070245165 *||24 Apr 2007||18 Oct 2007||Amphus, Inc.||System and method for activity or event based dynamic energy conserving server reconfiguration|
|US20070283176 *||3 Jul 2007||6 Dec 2007||Advanced Micro Devices, Inc.||Method and apparatus for improving responsiveness of a power management system in a computing device|
|US20070294555 *||21 Aug 2007||20 Dec 2007||Andrew Read||Saving power when in or transitioning to a static mode of a processor|
|US20080098248 *||31 Oct 2007||24 Apr 2008||National Semiconductor Corporation||Pipelined computer system with power management control|
|US20090031155 *||26 Jul 2007||29 Jan 2009||Qualcomm Incorporated||Method and Apparatus for Adaptive Voltage Scaling Based on Instruction Usage|
|US20090174454 *||12 Jan 2009||9 Jul 2009||Carragher Mark A J||Clock circuit for a microprocessor|
|US20090204830 *||11 Feb 2008||13 Aug 2009||Nvidia Corporation||Power management with dynamic frequency dajustments|
|US20090235104 *||27 May 2009||17 Sep 2009||Fung Henry T|
|US20100011233 *||14 Jul 2009||14 Jan 2010||Sameer Halepete||Adaptive power control|
|US20100073075 *||30 Nov 2009||25 Mar 2010||Robert Fu||System for substrate potential regulation during power-up in integrated circuits|
|US20100073076 *||30 Nov 2009||25 Mar 2010||Robert Fu||System for substrate potential regulation during power-up in integrated circuits|
|US20100109758 *||11 Jan 2010||6 May 2010||Tien-Min Chen||Feedback-controlled body-bias voltage source|
|US20100201434 *||19 Feb 2010||12 Aug 2010||Tien-Min Chen||Precise control component for a substrate potential regulation circuit|
|US20100257389 *||14 Jul 2009||7 Oct 2010||Eric Chen-Li Sheng||Adaptive control of operating and body bias voltages|
|US20100321081 *||30 Aug 2010||23 Dec 2010||Research In Motion Limited||Clock circuit for a microprocessor|
|US20110072282 *||22 Oct 2010||24 Mar 2011||Watts Jr Lavaughn F||Method for implementing thermal management in a processor and/or apparatus and/or system employing the same|
|US20110086478 *||14 Dec 2010||14 Apr 2011||Koniaris Kleanthes G||Systems and methods for integrated circuits comprising multiple body biasing domains|
|US20110107131 *||10 Jan 2011||5 May 2011||Andrew Read||Saving power when in or transitioning to a static mode of a processor|
|US20110208916 *||28 Nov 2008||25 Aug 2011||Masahiko Saito||Shared cache controller, shared cache control method and integrated circuit|
|US20110219245 *||9 May 2011||8 Sep 2011||Burr James B||Adaptive power control|
|US20110221029 *||23 May 2011||15 Sep 2011||Vjekoslav Svilan||Balanced adaptive body bias control|
|US20110231678 *||31 May 2011||22 Sep 2011||Stewart Thomas E||Adaptive power control based on post package characterization of integrated circuits|
|US20140325247 *||25 Apr 2013||30 Oct 2014||Inder Sodhi||Controlling power and performance in a system agent of a processor|
|USRE38108||22 Mar 2001||6 May 2003||Seiko Epson Corporation||Computer system with video display controller having power saving modes|
|USRE40866||22 Feb 2007||4 Aug 2009||Huron Ip Llc||System, method, and architecture for dynamic server power management and dynamic workload management for multiserver environment|
|WO1995012158A1 *||27 Oct 1994||4 May 1995||Elonex Technologies, Inc.||Timer-controlled computer system shutdown and startup|
|WO2003012610A1 *||25 Jul 2002||13 Feb 2003||Scientific-Atlanta, Inc.||Controlling processor clock rate based on thread priority|
|U.S. Classification||713/322, 713/321|
|International Classification||G06F1/20, G06F1/32, G06F1/08|
|Cooperative Classification||G06F1/3203, Y02B60/1275, Y02B60/1217, G06F1/206, G06F1/324|
|European Classification||G06F1/20T, G06F1/32P5F, G06F1/32P|
|30 Oct 1989||AS||Assignment|
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WALLACE, STEVEN J.;REEL/FRAME:005207/0050
Effective date: 19891027
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WATTS, LAVAUGHN F. JR.;REEL/FRAME:005207/0049
Effective date: 19891027
|5 Jul 1994||CC||Certificate of correction|
|25 Sep 1996||FPAY||Fee payment|
Year of fee payment: 4
|29 Sep 2000||FPAY||Fee payment|
Year of fee payment: 8
|29 Sep 2004||FPAY||Fee payment|
Year of fee payment: 12