US4930097A - Architecture for an improved performance of a programmable logic device - Google Patents
Architecture for an improved performance of a programmable logic device Download PDFInfo
- Publication number
- US4930097A US4930097A US07/292,464 US29246488A US4930097A US 4930097 A US4930097 A US 4930097A US 29246488 A US29246488 A US 29246488A US 4930097 A US4930097 A US 4930097A
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- US
- United States
- Prior art keywords
- coupled
- pld
- inputs
- buffer
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
Abstract
Description
Claims (18)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/292,464 US4930097A (en) | 1988-12-30 | 1988-12-30 | Architecture for an improved performance of a programmable logic device |
JP32978989A JP2818803B2 (en) | 1988-12-30 | 1989-12-21 | Programmable logic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/292,464 US4930097A (en) | 1988-12-30 | 1988-12-30 | Architecture for an improved performance of a programmable logic device |
Publications (1)
Publication Number | Publication Date |
---|---|
US4930097A true US4930097A (en) | 1990-05-29 |
Family
ID=23124793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/292,464 Expired - Lifetime US4930097A (en) | 1988-12-30 | 1988-12-30 | Architecture for an improved performance of a programmable logic device |
Country Status (2)
Country | Link |
---|---|
US (1) | US4930097A (en) |
JP (1) | JP2818803B2 (en) |
Cited By (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247195A (en) * | 1991-07-26 | 1993-09-21 | Advanced Micro Devices, Inc. | PLDs with high drive capability |
US5379442A (en) * | 1993-03-31 | 1995-01-03 | Intel Corporation | Fast primary and feedback path in a programmable logic circuit |
US5384732A (en) * | 1992-07-03 | 1995-01-24 | Seiko Epson Corporation | Semiconductor device comprising a function change over switching circuit having a non-volatile storage device |
US5432388A (en) * | 1992-08-27 | 1995-07-11 | At&T Global Information Solutions Company | Repeatedly programmable logic array using dynamic access memory |
US5596743A (en) * | 1993-05-28 | 1997-01-21 | Regents Of The University Of California | Field programmable logic device with dynamic interconnections to a dynamic logic core |
US6005806A (en) * | 1996-03-14 | 1999-12-21 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6018476A (en) * | 1996-09-16 | 2000-01-25 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6038627A (en) * | 1998-03-16 | 2000-03-14 | Actel Corporation | SRAM bus architecture and interconnect to an FPGA |
US6049487A (en) * | 1998-03-16 | 2000-04-11 | Actel Corporation | Embedded static random access memory for field programmable gate array |
US6150837A (en) * | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US6486701B1 (en) * | 2000-06-12 | 2002-11-26 | Cypress Semiconductor Corp. | CPLD high speed path |
US6549035B1 (en) | 1998-09-15 | 2003-04-15 | Actel Corporation | High density antifuse based partitioned FPGA architecture |
US6727726B1 (en) | 2002-11-12 | 2004-04-27 | Actel Corporation | Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array |
US6750674B1 (en) | 2002-10-02 | 2004-06-15 | Actel Corporation | Carry chain for use between logic modules in a field programmable gate array |
US6765427B1 (en) | 2002-08-08 | 2004-07-20 | Actel Corporation | Method and apparatus for bootstrapping a programmable antifuse circuit |
US6772387B1 (en) | 1998-03-16 | 2004-08-03 | Actel Corporation | Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture |
US6774667B1 (en) | 2002-05-09 | 2004-08-10 | Actel Corporation | Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays |
US6799240B1 (en) | 1998-03-16 | 2004-09-28 | Actel Corporation | SRAM bus architecture and interconnect to an FPGA |
US6825690B1 (en) | 2003-05-28 | 2004-11-30 | Actel Corporation | Clock tree network in a field programmable gate array |
US6838902B1 (en) | 2003-05-28 | 2005-01-04 | Actel Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US6867615B1 (en) | 2003-05-30 | 2005-03-15 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US6885218B1 (en) | 2002-10-08 | 2005-04-26 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US6891396B1 (en) | 2002-12-27 | 2005-05-10 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
US6891394B1 (en) | 2002-06-04 | 2005-05-10 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US20050146354A1 (en) * | 2002-12-18 | 2005-07-07 | Actel Corporation | Multi-level routing architecture in a field programmable gate array having transmitters and receivers |
US7378867B1 (en) | 2002-06-04 | 2008-05-27 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US7385419B1 (en) | 2003-05-30 | 2008-06-10 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
US7434080B1 (en) | 2002-09-03 | 2008-10-07 | Actel Corporation | Apparatus for interfacing and testing a phase locked loop in a field programmable gate array |
US7543216B1 (en) * | 1998-03-16 | 2009-06-02 | Actel Corporation | Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture |
US7545168B2 (en) | 2003-05-28 | 2009-06-09 | Actel Corporation | Clock tree network in a field programmable gate array |
US7549138B2 (en) | 2002-10-08 | 2009-06-16 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US7579869B2 (en) | 2002-12-27 | 2009-08-25 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4124899A (en) * | 1977-05-23 | 1978-11-07 | Monolithic Memories, Inc. | Programmable array logic circuit |
US4609986A (en) * | 1984-06-14 | 1986-09-02 | Altera Corporation | Programmable logic array device using EPROM technology |
US4617479A (en) * | 1984-05-03 | 1986-10-14 | Altera Corporation | Programmable logic array device using EPROM technology |
-
1988
- 1988-12-30 US US07/292,464 patent/US4930097A/en not_active Expired - Lifetime
-
1989
- 1989-12-21 JP JP32978989A patent/JP2818803B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4124899A (en) * | 1977-05-23 | 1978-11-07 | Monolithic Memories, Inc. | Programmable array logic circuit |
US4124899B1 (en) * | 1977-05-23 | 1987-04-28 | ||
US4617479A (en) * | 1984-05-03 | 1986-10-14 | Altera Corporation | Programmable logic array device using EPROM technology |
US4617479B1 (en) * | 1984-05-03 | 1993-09-21 | Altera Semiconductor Corp. | Programmable logic array device using eprom technology |
US4609986A (en) * | 1984-06-14 | 1986-09-02 | Altera Corporation | Programmable logic array device using EPROM technology |
Cited By (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247195A (en) * | 1991-07-26 | 1993-09-21 | Advanced Micro Devices, Inc. | PLDs with high drive capability |
US5384732A (en) * | 1992-07-03 | 1995-01-24 | Seiko Epson Corporation | Semiconductor device comprising a function change over switching circuit having a non-volatile storage device |
US5432388A (en) * | 1992-08-27 | 1995-07-11 | At&T Global Information Solutions Company | Repeatedly programmable logic array using dynamic access memory |
US5379442A (en) * | 1993-03-31 | 1995-01-03 | Intel Corporation | Fast primary and feedback path in a programmable logic circuit |
US5596743A (en) * | 1993-05-28 | 1997-01-21 | Regents Of The University Of California | Field programmable logic device with dynamic interconnections to a dynamic logic core |
US6005806A (en) * | 1996-03-14 | 1999-12-21 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6532170B1 (en) | 1996-03-14 | 2003-03-11 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6052309A (en) * | 1996-03-14 | 2000-04-18 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6226201B1 (en) | 1996-03-14 | 2001-05-01 | Altera Corporation | Techniques to configure nonvolatile cells and cell arrays |
US6295230B1 (en) | 1996-03-14 | 2001-09-25 | Altera Coporation | Nonvolatile configuration cells and cell arrays |
US6366498B1 (en) | 1996-03-14 | 2002-04-02 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6018476A (en) * | 1996-09-16 | 2000-01-25 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6078521A (en) * | 1996-09-16 | 2000-06-20 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US20050081177A1 (en) * | 1997-02-28 | 2005-04-14 | Actel Corporation | Enhanced field programmable gate array |
US6150837A (en) * | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US7382155B2 (en) | 1997-02-28 | 2008-06-03 | Actel Corporation | Enhanced field programmable gate array |
US6038627A (en) * | 1998-03-16 | 2000-03-14 | Actel Corporation | SRAM bus architecture and interconnect to an FPGA |
US20040237021A1 (en) * | 1998-03-16 | 2004-11-25 | Actel Corporation, A California Corporation | Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture |
US7124347B2 (en) | 1998-03-16 | 2006-10-17 | Actel Corporation | Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture |
US7543216B1 (en) * | 1998-03-16 | 2009-06-02 | Actel Corporation | Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture |
US7054967B2 (en) | 1998-03-16 | 2006-05-30 | Actel Corporation | SRAM bus architecture and interconnect to an FPGA |
US6772387B1 (en) | 1998-03-16 | 2004-08-03 | Actel Corporation | Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture |
US6049487A (en) * | 1998-03-16 | 2000-04-11 | Actel Corporation | Embedded static random access memory for field programmable gate array |
US6799240B1 (en) | 1998-03-16 | 2004-09-28 | Actel Corporation | SRAM bus architecture and interconnect to an FPGA |
US20040199689A1 (en) * | 1998-03-16 | 2004-10-07 | Actel Corporation, A California Corporation | SRAM bus architecture and interconnect to an FPGA |
US20080204074A1 (en) * | 1998-04-28 | 2008-08-28 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
US8990757B2 (en) | 1998-04-28 | 2015-03-24 | Microsemi SoC Corporation | Dedicated interface architecture for a hybrid integrated circuit |
US6549035B1 (en) | 1998-09-15 | 2003-04-15 | Actel Corporation | High density antifuse based partitioned FPGA architecture |
US6486701B1 (en) * | 2000-06-12 | 2002-11-26 | Cypress Semiconductor Corp. | CPLD high speed path |
US6774667B1 (en) | 2002-05-09 | 2004-08-10 | Actel Corporation | Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays |
US7378867B1 (en) | 2002-06-04 | 2008-05-27 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US7119573B2 (en) | 2002-06-04 | 2006-10-10 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US6891394B1 (en) | 2002-06-04 | 2005-05-10 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US7545166B2 (en) | 2002-06-04 | 2009-06-09 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US20050206407A1 (en) * | 2002-06-04 | 2005-09-22 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US6765427B1 (en) | 2002-08-08 | 2004-07-20 | Actel Corporation | Method and apparatus for bootstrapping a programmable antifuse circuit |
US7774665B2 (en) | 2002-09-03 | 2010-08-10 | Actel Corporation | Apparatus for testing a phrase-locked loop in a boundary scan enabled device |
US20090045855A1 (en) * | 2002-09-03 | 2009-02-19 | Actel Corporation | Apparatus for interfacing and testing a phase locked loop in a field programmable gate array |
US7434080B1 (en) | 2002-09-03 | 2008-10-07 | Actel Corporation | Apparatus for interfacing and testing a phase locked loop in a field programmable gate array |
US6750674B1 (en) | 2002-10-02 | 2004-06-15 | Actel Corporation | Carry chain for use between logic modules in a field programmable gate array |
US7549138B2 (en) | 2002-10-08 | 2009-06-16 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US7111272B1 (en) | 2002-10-08 | 2006-09-19 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US6885218B1 (en) | 2002-10-08 | 2005-04-26 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US6727726B1 (en) | 2002-11-12 | 2004-04-27 | Actel Corporation | Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array |
US6946871B1 (en) | 2002-12-18 | 2005-09-20 | Actel Corporation | Multi-level routing architecture in a field programmable gate array having transmitters and receivers |
US20050146354A1 (en) * | 2002-12-18 | 2005-07-07 | Actel Corporation | Multi-level routing architecture in a field programmable gate array having transmitters and receivers |
US7126374B2 (en) | 2002-12-18 | 2006-10-24 | Actel Corporation | Multi-level routing architecture in a field programmable gate array having transmitters and receivers |
US6891396B1 (en) | 2002-12-27 | 2005-05-10 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
US7579869B2 (en) | 2002-12-27 | 2009-08-25 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
US7075334B1 (en) | 2002-12-27 | 2006-07-11 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
US7049846B1 (en) | 2003-05-28 | 2006-05-23 | Actel Corporation | Clock tree network in a field programmable gate array |
US20060082385A1 (en) * | 2003-05-28 | 2006-04-20 | Actel Corporation, A California Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US6825690B1 (en) | 2003-05-28 | 2004-11-30 | Actel Corporation | Clock tree network in a field programmable gate array |
US7394289B2 (en) | 2003-05-28 | 2008-07-01 | Actel Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US20080218207A1 (en) * | 2003-05-28 | 2008-09-11 | Actel Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US7545168B2 (en) | 2003-05-28 | 2009-06-09 | Actel Corporation | Clock tree network in a field programmable gate array |
US7227380B2 (en) | 2003-05-28 | 2007-06-05 | Actel Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US6838902B1 (en) | 2003-05-28 | 2005-01-04 | Actel Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US7102385B2 (en) | 2003-05-30 | 2006-09-05 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US20080231319A1 (en) * | 2003-05-30 | 2008-09-25 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US20060087341A1 (en) * | 2003-05-30 | 2006-04-27 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US6867615B1 (en) | 2003-05-30 | 2005-03-15 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US7385419B1 (en) | 2003-05-30 | 2008-06-10 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US6980028B1 (en) | 2003-05-30 | 2005-12-27 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
Also Published As
Publication number | Publication date |
---|---|
JPH02226811A (en) | 1990-09-10 |
JP2818803B2 (en) | 1998-10-30 |
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Owner name: INTEL CORPORATION, 3065 BOWERS AVENUE, SANTA CLARA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:LEDENBACH, GREGORY W.;ALLEN, MICHAEL J.;REEL/FRAME:004999/0704 Effective date: 19881222 Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEDENBACH, GREGORY W.;ALLEN, MICHAEL J.;REEL/FRAME:004999/0704 Effective date: 19881222 |
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