US4195354A - Semiconductor matrix for integrated read-only storage - Google Patents

Semiconductor matrix for integrated read-only storage Download PDF

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US4195354A
US4195354A US05/931,422 US93142278A US4195354A US 4195354 A US4195354 A US 4195354A US 93142278 A US93142278 A US 93142278A US 4195354 A US4195354 A US 4195354A
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semiconductor
type conductivity
buses
components
metallic
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US05/931,422
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Jury V. Kruzhanov
Viktor P. Dubinin
Viktor S. Ovchinnikov
Vladimir E. Safronov
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/055—Fuse

Definitions

  • the invention relates to static storage devices, and more particularly to a semiconductor matrix for an integrated read-only storage suitable for use with accounting and controlling computers, with data acquisition and processing systems, and with various test and control apparatus.
  • a semiconductor matrix for an integrated read-only storage (cf. U.S. Pat. No. 3,721,964, cl. G11c, 7/00), comprising a plurality of components each of which is provided with a semiconductor region of a first type conductivity and a semiconductor region of a second type conductivity located in the latter.
  • the components are formed at the locations where semiconductor buses of said first type conductivity intersect metallic buses disposed in a dielectric layer which is adapted to isolate the semiconductor buses from the metallic buses.
  • the semiconductor buses are made in the upper layer of a two-layer semiconductor substrate, the upper layer of the substrate having said second type conductivity, and the lower layer of the substrate having said first type conductivity.
  • the known matrix has each of its components provided with a second type conductivity semiconductor region and a window located above the latter, but some of these regions are void of openings made above them in the first dielectric layer. Since the openings are made in certain windows only, there is a gap between the boundaries of a window and an opening, which does not allow for a decrease in the size of the window so as to obtain that size equal to that of the opening.
  • the size of a second type conductivity semiconductor region is determined by the size of an opening above it; therefore, the area of the p-n junction between the second type conductivity semiconductor region and the first type conductivity semiconductor region, and the capacitance of that p-n junction, are also determined by the window size which cannot be reduced to the opening size due to the availability of the above-mentioned gap. This tends to limit the extent of integration and speed of operation of the associated integrated read-only storage.
  • An object of the invention is to provide for a greater extent of integration of an integrated read-only storage.
  • Another object of the invention is to provide for a greater speed of operation of an integrated read-only storage.
  • a semiconductor matrix for an integrated read-only storage comprising a plurality of components each of which is provided with a semiconductor region of a first type conductivity, at least some components of said components each having a semiconductor region of a second type conductivity disposed in said first type conductivity semiconductor region, said components being formed at the locations where semiconductor buses of said first type conductivity, made in a substrate, intersect metallic buses disposed on a dielectric layer which is adapted to isolate the semiconductor buses from the metallic buses, windows being made in the dielectric layer above the second type conductivity semiconductor regions, some of the windows having openings to provide for electric contact between the second type conductivity semiconductor regions and the metallic buses, which matrix being characterized in that only those components of said components, above which the openings registering with the windows are located, are provided with the second type conductivity semiconductor regions.
  • the second type conductivity semiconductor regions with the windows disposed above them are incorporated only in those components which have the openings. It is therefore possible to combine the windows and the openings made in the dielectric layer. As a result, the area of the p-n junction between the second type conductivity semiconductor region and the first type conductivity semiconductor region as well as the capacitance of that p-n junction are reduced, which results in a greater extent of integration and speed of operation of the integrated read-only storage.
  • a semiconductor substrate 1 comprises semiconductor buses 2 of a first type conductivity opposite to that of the semiconductor substrate 1.
  • the components of the matrix of the invention are formed at the locations where the semiconductor buses 2 intersect metallic buses 3 disposed on a dielectric layer 4 which is used to isolate the semiconductor buses 2 from the metallic buses 3. At least some components of said components each have a semiconductor region 5 of a second type conductivity, disposed in the semiconductor bus 2.
  • openings 6 there are windows above the semiconductor regions 5 with which openings 6 are registered, said openings 6 being made in the dielectric layer 4 and being disposed above those components which comprise the semiconductor regions 5.
  • the prior art and disclosed matrices for an integrated read-only storage have a specification as follows: identical openings in the dielectric layer 4 each having an area of 3 ⁇ 3 ⁇ m 2 ; identical depth of the regions 5 equal to 1 ⁇ m; and the value of the gap between the boundaries of the window and the opening, in the prior art matrix, equal to 2 ⁇ m.
  • the disclosed matrix has the area of the above p-n junction decreased by a factor of 2 (and therefore a greater extent of integration) and has the capacitance of the above p-n junction decreased by a factor of 2.5 (and therefore a greater speed of operation), as compared to the prior art matrix.
  • the capacity of the latter is increased to a superhigh level and such a storage can be implemented as part of a single-chip computer.
  • the substrate 1 is made of p-type silicon to which boron is added to obtain a concentration level of 5.10 16 cm -3 .
  • the buses 2 are made of n-type silicon to which phosphorus is added to obtain a concentration level of 5.10 17 cm -3 .
  • the regions 5 are made of p-type silicon to which boron is added to obtain a concentration level of 5.10 18 cm -3 .
  • the dielectric layer 4 is made of silicon dioxide.
  • the metallic buses 3 are made of molybdenum.
  • the fabrication of the matrix of the invention in accordance with the above requirements includes the steps as follows: the oxide is grown; windows are opened in the latter to allow for the introduction of phosphorus; phosphorus is used for ion doping; phosphorus is subject to diffusion and simultaneous oxidation is effected; windows are opened in the oxide to introduce boron and ion doping with boron is then performed.
  • molybdenum connections are formed and heating is effected to activate the impurity.
  • the substrate 1 is made of n-type silicon to which phosphorus is added to obtain a concentration level of 10 16 cm -3 .
  • the buses 2 are made of p-type silicon to which boron is added to obtain a concentration level of 10 17 cm -3 .
  • the regions 5 are made of n-type silicon to which arsenic is added to obtain a concentration level of 10 19 cm -3 .
  • the dielectric layer 4 is a layer of silicon dioxide.
  • the metallic buses 3 are made of aluminum.
  • the fabrication of the matrix of the invention in accordance with the above requirements includes the steps as follows: the oxide is grown; windows are opened in the latter to allow for the introduction of boron; boron is used for ion doping; boron is subject to diffusion and similtaneous oxidation is effected; windows are opened in the oxide to introduce arsenic and ion doping with arsenic is then performed.
  • heating is effected to provide for the activation of the impurity and aluminum connections are formed.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

A semiconductor matrix for an integrated read-only storage is disclosed which comprises a plurality of components each of which is provided with a semiconductor region of a first type conductivity, at least some components of said components each having a semiconductor region of a second type conductivity disposed in said first type conductivity semiconductor region. Said components are formed at the locations where semiconductor buses of said first type conductivity, made in a substrate, intersect metallic buses disposed on a dielectric layer which is adapted to isolate the semiconductor buses from the metallic ones. There are windows comprising openings which register with them and are adapted to provide for electric contact between the second type conductivity semiconductor regions and the metallic buses, said windows are formed in the dielectric layer above said second type conductivity semiconductor regions of respective components.

Description

FIELD OF THE INVENTION
The invention relates to static storage devices, and more particularly to a semiconductor matrix for an integrated read-only storage suitable for use with accounting and controlling computers, with data acquisition and processing systems, and with various test and control apparatus.
DESCRIPTION OF THE PRIOR ART
Known in the art is a semiconductor matrix for an integrated read-only storage (cf. U.S. Pat. No. 3,721,964, cl. G11c, 7/00), comprising a plurality of components each of which is provided with a semiconductor region of a first type conductivity and a semiconductor region of a second type conductivity located in the latter. The components are formed at the locations where semiconductor buses of said first type conductivity intersect metallic buses disposed in a dielectric layer which is adapted to isolate the semiconductor buses from the metallic buses. The semiconductor buses are made in the upper layer of a two-layer semiconductor substrate, the upper layer of the substrate having said second type conductivity, and the lower layer of the substrate having said first type conductivity. There are windows covered with another dielectric layer, located above the second type conductivity semiconductor regions and made in the first dielectric layer, some of the windows having openings to provide for electric contact between the second type conductivity semiconductor regions and the metallic buses.
The known matrix has each of its components provided with a second type conductivity semiconductor region and a window located above the latter, but some of these regions are void of openings made above them in the first dielectric layer. Since the openings are made in certain windows only, there is a gap between the boundaries of a window and an opening, which does not allow for a decrease in the size of the window so as to obtain that size equal to that of the opening. The size of a second type conductivity semiconductor region is determined by the size of an opening above it; therefore, the area of the p-n junction between the second type conductivity semiconductor region and the first type conductivity semiconductor region, and the capacitance of that p-n junction, are also determined by the window size which cannot be reduced to the opening size due to the availability of the above-mentioned gap. This tends to limit the extent of integration and speed of operation of the associated integrated read-only storage.
SUMMARY OF THE INVENTION
An object of the invention is to provide for a greater extent of integration of an integrated read-only storage.
Another object of the invention is to provide for a greater speed of operation of an integrated read-only storage.
There is disclosed a semiconductor matrix for an integrated read-only storage, comprising a plurality of components each of which is provided with a semiconductor region of a first type conductivity, at least some components of said components each having a semiconductor region of a second type conductivity disposed in said first type conductivity semiconductor region, said components being formed at the locations where semiconductor buses of said first type conductivity, made in a substrate, intersect metallic buses disposed on a dielectric layer which is adapted to isolate the semiconductor buses from the metallic buses, windows being made in the dielectric layer above the second type conductivity semiconductor regions, some of the windows having openings to provide for electric contact between the second type conductivity semiconductor regions and the metallic buses, which matrix being characterized in that only those components of said components, above which the openings registering with the windows are located, are provided with the second type conductivity semiconductor regions.
In the disclosed matrix, the second type conductivity semiconductor regions with the windows disposed above them are incorporated only in those components which have the openings. It is therefore possible to combine the windows and the openings made in the dielectric layer. As a result, the area of the p-n junction between the second type conductivity semiconductor region and the first type conductivity semiconductor region as well as the capacitance of that p-n junction are reduced, which results in a greater extent of integration and speed of operation of the integrated read-only storage.
The invention will now be described, by way of example, with reference to the accompanying drawing which shows a lateral section of a portion of a semiconductor matrix for an integrated read-only storage, according to the invention.
DESCRIPTION OF THE INVENTION
A semiconductor substrate 1 comprises semiconductor buses 2 of a first type conductivity opposite to that of the semiconductor substrate 1.
The components of the matrix of the invention are formed at the locations where the semiconductor buses 2 intersect metallic buses 3 disposed on a dielectric layer 4 which is used to isolate the semiconductor buses 2 from the metallic buses 3. At least some components of said components each have a semiconductor region 5 of a second type conductivity, disposed in the semiconductor bus 2.
There are windows above the semiconductor regions 5 with which openings 6 are registered, said openings 6 being made in the dielectric layer 4 and being disposed above those components which comprise the semiconductor regions 5.
Assume that the prior art and disclosed matrices for an integrated read-only storage have a specification as follows: identical openings in the dielectric layer 4 each having an area of 3×3 μm2 ; identical depth of the regions 5 equal to 1 μm; and the value of the gap between the boundaries of the window and the opening, in the prior art matrix, equal to 2 μm. With these parameters, the disclosed matrix has the area of the above p-n junction decreased by a factor of 2 (and therefore a greater extent of integration) and has the capacitance of the above p-n junction decreased by a factor of 2.5 (and therefore a greater speed of operation), as compared to the prior art matrix.
With the disclosed matrix used as an accumulator and/or decoder of an integrated read-only storage, the capacity of the latter is increased to a superhigh level and such a storage can be implemented as part of a single-chip computer.
Embodiments of the invention will now be described by way of the following Examples.
EXAMPLE 1
The substrate 1 is made of p-type silicon to which boron is added to obtain a concentration level of 5.1016 cm-3.
The buses 2 are made of n-type silicon to which phosphorus is added to obtain a concentration level of 5.1017 cm-3.
The regions 5 are made of p-type silicon to which boron is added to obtain a concentration level of 5.1018 cm-3.
The dielectric layer 4 is made of silicon dioxide.
The metallic buses 3 are made of molybdenum.
The fabrication of the matrix of the invention in accordance with the above requirements includes the steps as follows: the oxide is grown; windows are opened in the latter to allow for the introduction of phosphorus; phosphorus is used for ion doping; phosphorus is subject to diffusion and simultaneous oxidation is effected; windows are opened in the oxide to introduce boron and ion doping with boron is then performed.
At the final stage, molybdenum connections are formed and heating is effected to activate the impurity.
EXAMPLE 2
The substrate 1 is made of n-type silicon to which phosphorus is added to obtain a concentration level of 1016 cm-3.
The buses 2 are made of p-type silicon to which boron is added to obtain a concentration level of 1017 cm-3.
The regions 5 are made of n-type silicon to which arsenic is added to obtain a concentration level of 1019 cm-3.
The dielectric layer 4 is a layer of silicon dioxide.
The metallic buses 3 are made of aluminum.
The fabrication of the matrix of the invention in accordance with the above requirements includes the steps as follows: the oxide is grown; windows are opened in the latter to allow for the introduction of boron; boron is used for ion doping; boron is subject to diffusion and similtaneous oxidation is effected; windows are opened in the oxide to introduce arsenic and ion doping with arsenic is then performed.
At the final step, heating is effected to provide for the activation of the impurity and aluminum connections are formed.

Claims (1)

What is claimed is:
1. A semiconductor matrix for an integrated read-only storage, comprising:
a substrate;
semiconductor buses of a first type conductivity, formed in said substrate;
metallic buses arranged in an intersection relationship to said semiconductor buses of said first type conductivity;
a dielectric layer having said metallic buses disposed thereon and adapted to isolate said semiconductor buses from said metallic buses;
a plurality of components of said matrix, formed at the locations where said semiconductor buses of said first type conductivity intersect said metallic buses and implemented on the basis of a semiconductor region of said first type conductivity, only some components of said components therein having a second type conductivity; and
windows formed in said dielectric layer above said second type conductivity semiconductor regions of said some components and comprising openings registered with said windows so that the area of p-n junction between the second type conductivity semiconductor region and the first type conductivity semiconductor region as well as the capacitance of said p-n junction are reduced, thereby providing increased integration and speed of operation of the integrated read-only storage.
US05/931,422 1977-08-16 1978-08-07 Semiconductor matrix for integrated read-only storage Expired - Lifetime US4195354A (en)

Applications Claiming Priority (2)

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SU2517209 1977-08-16
SU2517209[I] 1977-08-16

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US4195354A true US4195354A (en) 1980-03-25

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US (1) US4195354A (en)
JP (1) JPS5448453A (en)
DE (1) DE2835087C2 (en)
FR (1) FR2400747A1 (en)
GB (1) GB2004688B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3717852A (en) * 1971-09-17 1973-02-20 Ibm Electronically rewritable read-only memory using via connections

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3721964A (en) * 1970-02-18 1973-03-20 Hewlett Packard Co Integrated circuit read only memory bit organized in coincident select structure
GB1357515A (en) * 1972-03-10 1974-06-26 Matsushita Electronics Corp Method for manufacturing an mos integrated circuit
JPS5416990A (en) * 1977-07-08 1979-02-07 Hitachi Ltd Matrix form logic circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3717852A (en) * 1971-09-17 1973-02-20 Ibm Electronically rewritable read-only memory using via connections

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Abbas, Electronically Encodable Read-only Store, IBM Technical Disclosure Bulletin, vol. 13, No. 6, 11/70, pp. 1426-1427. *
Gaesslen, Schottky Barrier Read-only Memory, IBM Technical Disclosure Bulletin, vol. 14, No. 1, 6/71, p. 252. *

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JPS5448453A (en) 1979-04-17
FR2400747A1 (en) 1979-03-16
GB2004688A (en) 1979-04-04
GB2004688B (en) 1982-05-06
DE2835087A1 (en) 1979-03-01
DE2835087C2 (en) 1984-10-31
FR2400747B1 (en) 1984-11-23

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