US3256516A

US3256516A - Data display centering and expansion system

Info

Publication number: US3256516A
Application number: US203823A
Authority: US
Inventors: John J Melia; Stephen J Popick; Benjamin E Simpson; Walter L Tuchman
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1962-06-20
Filing date: 1962-06-20
Publication date: 1966-06-14
Anticipated expiration: 1983-06-14

Description

June 14, 1966 J. J. MELIA ETAL. 3,256,516

DATA DISPLAY CENTERING AND EXPANSION SYSTEM Filed June 20, 1962 6 Sheets-Sheet 1 CONSOLE 88 CONSOLE DISPLAY CENTRAL 88 COMMON PROCESSOR 94 82 f 84 CONSOLE 80 106 H0 150 D/A (H4 Mfg-"M 108" 116 D/A 157p x Y x Y REG REG SENS SENS EXP EXP GATES GATES k k k k k 8 8 I 94/ 150 168 x Y 92/ 8] REG REG! J 140 f AREA 160 INVENTORS SEL JOHN J MELIA Y STEPHEN J. POPICK AREA BENJAMIN E. SIMPSON sgz l WALTER L.TUCHMAN 400 q 159 By 24% 8 9.3

ATTORNEY June 14, 1966 J. J. MELIA ETAL 3,256,516

DATA DISPLAY CENTERING AND EXPANSION SYSTEM Filed June 20, 1962 6 Sheets-Sheet 4.

KM 7811' REG 380 9 1 11 aw m f O 582" 1 X32 x4 1 1 R X186 6 8 1-0 1 ,1? 11 0 X2 X4 X8 DEC DEC DEC 1110 o 0 0 0 O 0 o 111 1100 o 0 0 o O 0 0 1100 0 o 0 1010 o O. o 0 o o 0 101 1000 0 o 0 0 o 0 0 1000 o 0 o 0110 o 0 0 0 0 o o 011 0100 0 0 o 0 o O o 0100 0 0 o 0010 o o 0 0 0 0 o 001 R o o 0 o 0 o 0 0 o 0 June 14, 1966 J. J. MELIA ETAL 3,256,516

DATA DISPLAY CENTERING AND EXPANSION SYSTEM Filed June 20, 1962 6 Sheets-Sheet 5 FIG. 7 b

Ill O IO June 14, 1966 J. J. MELIA ETAL 3,256,516

DATA DISPLAY CENTERING AND EXPANSION SYSTEM 6 Sheets-Sheet 6 Filed June 20, 1962 mm mm 5 3 mm 3 R @N @N E Q NN R 2 E E t m: 2 3 E N s mw-wmqmm United States Patent Ofiice 3,256,516 Patented June 14, 1966 3,256,516 DATA DISPLAY CENTERING AND EXPANSION SYSTEM John J. Melia, Woodstock, and Stephen J. Popick, Kingston, N.Y., Benjamin E. Simpson, Waldron, Ark., and Walter L. T uchman, De Witt, N.Y., assignors to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed June 20, 1962, Ser. No. 203,823 6 Claims. (Cl. 340-1725) This invention relates to data processing systems and more particularly to centeriing and expansion means for control of data display equipment of such systems.

Display systems are frequently included in data processing equipments, often for the purpose of displaying data messages which have positional significance. Thus, each of a group of messages may include unique display address information, which constitutes part of the intelligence conveyed by the message, and is determinative of the position at which visual symbol of the message is displayed.

It is often desired that messages be displayed on an expanded address scale, for better observation or handling of a particular message or group of neighboring messages. Accordingly, means may be provided whereby messages having addresses normally falling within a particular portion of the display area can be displayed at relocated and relatively expanded display addresses. By this manipulation of addresses, the portion of the display of interest is enlarged and centered, filling the available display area.

The display equipment in a large data processing system may include a number of display consoles attended by individual operators. One operator may wish to scrutinize one area of the display while another is interested in a different section. Accordingly, it is often desired that centering and expansion means be provided which does not affect operation of the central computer, but, rather, is individual to each console and under the control of the individual operator.

A system having the aforedescribed capabilities is disclosed in Gerhardt US. Patent No. 3,011,164. Push buttons are provided by which the operator can define the display area which is to be central and expanded. Operation of the proper push buttons, for executing optimum centering, is a matter of operator judgment and accuracy.

In accordance with the present invention, means are provided whereby centering of the expanded display is automatic upon identification of a mesasge of interest. The identified message becomes a key message, operative to control the centering system. Accidental expansion of the identified message off of the display screen is impossible, and optimum centering of that key message and its environs, within the capabilities of the centering circuitry, is assured.

Conveniently, the selection of the key message can be by operation of a manipulatable device which is sensitive to the display of the message, such as a so-called light gun or light pencil. Thus, the equipment provides the operator of the console with the desired ability to select the area which is to be centered and expanded, in terms of an exact message of interest.

Accordingly, it is a principal object of the present invention to provide improved means for centering and expanding display information, with reference to a particular message of interest.

It is another object of the invention to provide im-- proved display expansion means whereby optimum centering of a given message is assured, within the limits of the centering circuitry.

Yet another object of the invention is to provide an im proved display system as aforesaid, wherein operator selection of an area for centering and expansion is facilitated.

It is another object of the invention to provide improved centering and expanison means for use in a data processing system as aforesaid, which, by reason of its simplicity, may be incorporated individually and independently in each display console of a multiple console system.

Another object of the invention is to provide improved centering and expansion means as aforesaid which does not affect operation of the central computer or other data source.

Still another object of the invention is to provide for more accurate handling of densely grouped display messages, such as are often encountered in the use of computer operated display devices.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying draw- 1ngs.

FIG. 1 is a block diagram of a data processing system including a multi-console display system which may advantageously embody the invention;

FIG. 2 is a schematic representation of portions of a display console, suitable for use in a multi-console system in accordance with FIG. 1 and illustrative of a preferred embodiment of the invention;

FIGS. 3, 3a and 3b illustrate in simplified form logical circuitry of one preferred embodiment of the invention;

FIG. 4 is a view of the display area of the display tube of FIG. 2, showing the available unexpanded mes sage positions in a version of the system; having three-bit binary encoded display addresses;

FIG. 5 is a view similar to FIG. 4, but showing available message positions after expansion of the display;

FIG. 6 shows a series of diagrams of the display area illustrating unexpanded locations of messages which may be selected and displayed at expanded addresses by operation of circuitry of the invention;

FIG. 7 is a diagram showing the layout relationship of sheets of the drawing bearing FIGS. 7a and 8a and FIGS. 71) and 8b;

FIGS. 7a and 7b together constitute a chart of unexpanded display address group limits, pertinent to various levels of expansion;

FIGS. 8a and 8b together constitute a table of binary encoded display addresses for one display axis, showing significant 'bit definitions of the group limits of the chart of FIGS. 7a and 7b; and

FIG. 9 is a schematic representation of address group selector means for'use in modified systems of the invention providing multiple levels of display expansion.

The present invention provides improvement in display systems of the kinds wherein expansion and centering capability is a desired attribute. One display system of this kind is shown in the aforementioned US. Patent No.

3 3,011,164 to R. H. Gerhardt. In certain aspects, the present invention may be viewed as comprising a combination with teachings of Gerhardt which yields improved capabilities.

It is an important attribute of the present invention that its improvements in centering and expansion means, like the prior teachings of Gerhardt, may be embodied at the console level, that is, duplicated in each console of a plural display console data processing system. Thus, each console operator is given individual, automatic controls which need not in their functioning affect or burden operation of the central processor of the system.

Accordingly, as shown in FIG. 1, a data processing system environment in which aspects of the present invention find advantageous use may take the form of a digital computer or other suitable central processor 80 having an output connection 82 to a display common unit 84. The display common unit 84, whichmay contain suitable buffer and other interface equipment, feeds display message information, including display address information to

consoles

86, 88, 90 in parallel, as indicated at 92, 94, 96, 98, 100.

The centering and expansion facilities of and at each of the

consoles

86, 88, 90 may take the form diagrammed in FIG. 2. The image producing device at the console may be, for example, a shaped beam cathode ray tube 110 of the kind having a cathode 112, and electron beam blanking control grid 114, accelerating and focusing anodes 116, character selection deflection plates 118 and a cooperating character shape forming aperture matrix 120, a convergence coil 122 and compensation plates 124 for realigning the shaped electron beam axially of the tube, X and Y electro-magnetic deflection yoke means 126, a phosphor screen at the face 128 of the tube, and a post acceleration high voltage anode 130.

In a display system of the kind diagrammed in FIGS. 1 and 2, the display signals furnished by the display common unit 84 to the several consoles may take the form of a succession of binary encoded multi-bit words identifying each message as it is displayed, with the message comprising a particular character of the character matrix of the shaped beam cathode ray tube 110 together with the address on the screen 128 of the cathode ray tube at which that character is to be displayed. Other command information may be transmitted from the display common equipment 84 to the consoles, such as a timing signal operative to switch the voltage level on the control grid 114 of the cathode ray tube from its blanking to its unblanking level, so as to gate the electron beam on only after the character selection and message deflection circuitry has settled. Accordingly, the input connections to the console of FIG. 2 may include a line 92 for the blank-unblank signal, and

channels

94, 96 having two lines per hit for each of the several bits constituting the message word portion'representative of the matrix 120 X and Y addresses of the character to be displayed. Another channel 98 includes a number of conductor pairs for transfer of the binary encoded X display screen address at which the character is to be shown, while a fifth multi-conductor channel 100 contains conductor pairs for the Y display address portion of the message word. The message word bits could be transmitted to the console in the form of levels; however, it is frequently more convenient to effect this command and message transfer in the form of pulses and therefore the schematic of FIG. 2 shows registers for local storage of the information during the display of the successive messages.

Accordingly,

channels

94, 96 are connected to character information storage registers 104, 105 which provide levels for operation of the character select plates 118 through suitable decoder or digital to .

analog converter units

106, 108. The X display address or X axis mes sage positioning information supplied in pulse form via the conductor channel 98 is stored in register 132, whence it is supplied in level form through expansion circuitry 134 and decoder 136 to the X axis portion of the deflection yoke 126. In like manner, the Y axis message positioning information from conductor channel or' group is stored in register 140 during the display of the character called for by the message, the level-form, binary encoded Y display address information provided by register 140 being operative through expansion circuitry 144 and Y axis decoder 146 to operate the Y axis portion of the deflection yoke 126.

The expansion circuitry of the illustrated embodiment of the invention operates, as detailed in FIGS. 3, 3a and 312, by altering or shifting the significance of the bit posi tions of the binary encoded display address information. Since this results in the loss of the most significant bit in each of the X and Y display address word portions, superposition or original (unexpanded) display areas would result were not means provided to suppress all but a selected group of messages. .Thus, the area-of-interest control circuitry includes an X axis sensor 150 and a Y axis sensor 152, the outputs-of which, together with the blank-unblank timing signal on line 92 are connected to an AND circuit 154. The output of the AND circuit 154 is communicated via line 157 to the control grid 114 of the display tube, and is at a level to unblank or intensity the electron beam of the display tube only during the simultaneous presence of an unblank-significant level on line 92 and from the outputs of the

sensor circuits

150 and 152.

Moreover, operation of the scheme of FIGS. 3, 3a and 3b in the literal expansion of certain areas of the original display, hereinafter referred to as overlap areas involves complementing a certain address bit. Accordingly, identification of the area of interest is desired for address data manipulation, as Well as spurious message suppression.

In accordance with the present invention, means are provided whereby identification and selection of the address group corresponding to the area of interest is affected automatically upon identification of a particular address of interest. Advantageously, this address may be any address in the display area and may be derived from an operator-selected one of the information messages fed to the console, by means which are operable by and upon the display of that message. Accordingly, once a message has been selected for area of interest identification purposes it becomes a key message and its address is referred hereinafter as the key message address.

The illustrated embodiment of the invention includes area of

interest selection circuitry

158, 159 which is responsive, not only to the key message address but also to expansion level command means such as a manually operable expansion level control switch 160, to provide area of interest control information to the X and

Y sensing circuits

150, 152. This information is also fed to the expansion circuitries 134, 144, for control of address manipulation required in the expanded display of overlap areas, as hereinafter more fully described.

For the purpose of making the key message address available to the area of

interest control circuitry

158, 159, the illustrated embodiment of the invention includes

registers

162, 164 and means responsive to operator identification of a key message to store the address of that message in these key message address registers. These means include

gates

166, 168 which are conditioned as shown by the outputs of the X and Y display address registers 132, 140, and an operator manipulatable sensing device such as a photocell device 170. The photocell device 170 is operable to provide a pulse on its output line 172 to sample the

gates

166, 168 in timed coincidence with the display of a message whose display address is at the moment present in the X and Y display address registers 132, 140. The photocell device 170 may take the form shown in US. Patent No. 2,915,643, issued December 1, 1959 in the name of R. G. Mork. This kind of device is known to the art as a light gun or light pencil and may be provided with a trigger switch 173 for enabling the output of its photocell. Thus, the operator positions the device relative to the screen of the display tube 110 for receipt of and activation by the light of the message in which he is interested. He then closes the trigger switch 173, and the time coincidence of the resulting pulse on line 172 with the address in

registers

132, 140, serves to identify that address as the key message address.

FIGS. 3, 3a and 319 show in simplified form circuitry which is operative to select and manipulate X axis display addresses in the manner aforedescribed. Except for the expansion level select switch 160 and the photocell device 170, which are common to the X and Y axis selection and expansion systems as indicated in-FIG. 2, the circuitry of FIGS. 3, 3a and 3b is duplicated for the Y axis and therefore a detailed showing of the Y axis circuitry is not included. Joint operation of the circuitry of FIGS. 3, 3a and 3b with the substantially identical Y axis selection and ex ansion circuitry effects the desired selection and expansion of a display address groups as indicated in FIGS. 4, 5 and 6.

FIG. 4 shows an array of available message display addresses in the unexpanded display, and FIG. 5 shows certain of those addresses which have been selected to the exclusion of the rest, and reoriented on a doubled scale. FIG. 6 shows areas of the FIG. 4 display which may be selected for expansion by operation of the X axis circuitry of FIGS. 3, 3a and 3b and its companion Y axis circuitry. These areas fall into two major classes,

quadrant areas

180, 182, 184 and 186, and overlap

areas

188, 190, 194, 196 and 198. The address groups of quadrant areas comprise integral divisions of each display axis; In the overlap areas, at least one axis address group is :a non-integral or overlap division of that axis. When considering the X axis alone, these address groups may be termed

left side

180, 182, 188,

right side

184, 186, 190, and overlap 194, 196, 198 address groups.

It will be observed that doubling the display scale of a quadrant area may be accomplished by discarding the most significant bit in each of the X and Y addresses, shifting those addresses so as to multiply the significance of each of the remaining bits by two, and suppressing the display of all messages having original addresses falling outside the quadrant selected. In the expansion of any one of the

overlap squares

188, 190, 194, 196 or 198, however, there is the additional step of complementing the most significant bit in the expanded X address or Y address or both.

In other words, considering for simplicity only the X axis, the second and third most significant bits in the addresses, 000, 001, 010, and'Oll repeat in the same order in the

addresses

100, 101, 110 and 111. Thus, centered and expanded display of either first (left) half or the second (right) half of the original address range can be effected by simply discarding the most significant bit and shifting the remaining bits one position so as to donble their numerical weight. On the other hand, expansion and centering of the message positions having original addresses of 010, 011, 100 and 101 involves not only the foregoing shifting and bit dropping steps but also the step of complementing the most significant bit in the expanded address; thus, the original message address of 010 is re-oriented to location 000, and so on.

In the embodiment shown in FIGS. 3, 3a and 3b, the aforedescribed bit shifting and manipulating steps are performed by expansion circuitry 134 under the control of relays 200, 202, the control inputs or armatures of which constitute part of the address group selection circuitry 158. If the expansion select switch 160 is in its normal, open position, relay 200 is de-energized, whereby its contacts 200-1, 2002 and 200-3 are in their closed position. Thus, the 1 significant

level output lines

206, 208, 210, of flip-

flops

214, 216, 218 in the X display address register 132 are connected in straight-through re- 6 lationship to the

input channels

220, 222, 224 of the X display address decoder 136. As shown, the decoder 136 may be of the kind comprising current gates 226, 228, 230 connected to be conditioned by a l significant level on the corresponding

input channel line

220, 222, 224, and when conditioned, to pass currents from corresponding constant

current sources

232, 234, 236 to a binary weighted attenuation network 238. The decoder 136 is thus a digital to analog converter which receives a binary encoded digital address on

lines

220, 222, and 224 and yields an analog voltage equivalent of that address. The analog output lines 240 of the decoder 136 are connected, as shown in FIG. 1, to the deflectionyoke 126 of the display tube 110.

Accordingly, when the expansion level switch 160 is in its times one (open) position X1, each successive X address stored in the register 132 is operative to energize the X portion of the deflection yoke 126 of the display tube 110 with an analog signal corresponding to the value of that X address. The effect of this analog energization of the yoke 126 is added to the effect of bias means (not shown) which cause the quiescent or rest position of the electron beam of the display tube to be atan X, Y address of 000, 000 identified by the letter R in FIG. 4. Accordingly, utilization of three hits in the X address register 132, as shown in FIG. 3 can cause the electron-beam of the display tube 110 to be deflected to any of the X axis address values shown in FIG. 4.

If the expansion level select switch is moved to its closed or X2 position, for the production of a display having a times two expansion, the solenoid of'relay 200 is energized, by the power of a suitable voltage supply (not shown) connected to supplies terminal 242, 244. This action opens relay contacts 200-1, 200-2, 200-3 and closes normally open contacts 2004 and 2005 of relay 200, thereby connecting outputs of the second and third most significant flip-

flops

216, 218 of the X address register 132 to the first and second most

significant input channels

220, 222 of the decoder 136. This accomplishes the desired multiplication of the weight of the address by a factor of two.

It will be recalled that it was stated that in the cases of expansion. and centering of overlap address groups it is necessary, when using the centering and expansion scheme detailed herein, to complement the bit supplied to the most significant input channel 220 of the decoder 136. In the circuit of FIG. 3b, this is accomplished for the X axis by operation of relay 202. If one of the

overlap portions

194, 196 or 198 of FIG. 5 is selected 7 for display, relay 202 is energized thereby opening its normally closed contact 2021 and closing its normally open contact 2022 so as to disconnect the 1 significant line 208 of flip-flop 216 from the decoder 136, and to connect the 0 output line of that flip-flop in its stead.

Referring again to FIGS. 4 and 6, it will be recalled that all unexpanded X addresses falling in any of the

lefthand areas

180, 182, 188 have a most significant bit of 0, while the X addresses falling in any of the

righthand areas

184, 186, 190 begin with a most significant bit of 1. Accordingly, when a lefthand area is to be displayed on a doubled scale, messages having X axis display addresses in the register 132 which have a most significant bit of 0 are legal and are to be displayed, while those addresses starting in a l are illegal and identify an unwanted message. Conversely, if messages whose X address falls in one of the

squares

184, 186 or 190 are to be displayed on the expanded address scale, then original message addresses in the register 132 beginning in a 1 are legal and those beginning in a 0 are illegal. However, in the case X

axis overlap squares

194, 196 and 198, it is necessary to sense the first two hits since addresses beginning in either 01 or 10 are legal.

The X axis sensing circuit 150 performs the abovedescribed discrimination between legal and illegal addresses. If messages having addresses falling within one of the lefthand squares of the unexpanded display are to be shown on the doubled scale, relay 250 is energized thereby closing its normally open contact 250-1 which connects the side of the most significant flipflop 214 in the register 132 to an AND circuit 260. The other input 262 of AND circuit 260 is energized from a suitable voltage source 264, through normally closed contact 202-3 of relay 202, and

lines

266 and 268.

If all X axis addresses beginning in their unexpanded form in a l are to be legal, relay 252 is energized whereby the 1 side of the flip-flop 214 is connected, via line 270 and contact 252-1 of relay 252 to another AND circuit 272. The other input 274 of AND circuit 272 is energized from-the source 264, through normally closed contact 202-3 and line 226.

If only those X axis addresses beginning in their unexpanded form with the

bits

01 or 10 are to be legal, relay 202 is energized. Energization of relay 202 operates to close its contacts 202-4, 202-5, 202-6 and 202-7, and to open its contact 202-3. Thus, if the contents of the two most significant flip-

flops

214, 216 of the register 132 are 0 and 1 respectively, a level is communicated from the O side of flip-flop 214 via line 280 contact 250-1 and line 258 to one input of AND circuit 260, while the other side of the same AND circuit 260 is energized from the 1 side of the second flip-flop 216, via line 208, line 282, contact 202-6 and line 262. If the address bits stored in flip-

flops

214, 216 are 1 and 0, respectively, AND circuit 272 is energized via

lines

206, 270 and contact 202-4, and by lines 204, 236 contact 202- and line 274.

Relays

202, 250, and 252 are interlocked with the expansion level select relay 200 by means of normally open contacts 200-6, 200-7, 200-8 of that relay, so as to be de-energized whenever the expansion level select switch 160 is in its X1 position and relay 200 is thereby de-energized. Furthermore, relay 200 has a normally closed contact 200-9 which connects voltage supply 264 to line 288 whenever relay 200 is de-energized.

Line 288 and the output lines 290 and 292 are connected via an OR circuit 294 to a line 296 which constitutes the output of the X axis address sensing circuit 150 and is connected as shown in FIG. 2 to the intensification control AND circuit 154 of the display tube 110.

Accordingly, the X display sense circuit 150 of FIG. 3b is operative to supply a significant level on line 296 Whenever the expansion level select switch is in its X1 position, irrespective of the contents of register 132; however, when level select switch 160 is in its X2 position a significant level appears on line 296 only when the address in register 132 is a legal one.

In accordance with the present invention the area or address group select circuitry 158 of FIG. 2 includes means responsive to the detection of the display of a message of interest by the photocell device 170, to energize the appropriate one of

relays

202, 250, 252 for selecting automatically the most appropriate X axis address group for expansion. Since adjacent address groups available for expansion overlap each other, it is desirable that there be selected for expansion that address group which not only includes the address of the message of interest but also will center that message most nearly in the expanded display.

Referring to FIG. 4, it will be seen that a message of interest having an X axis address of O00, 001 or 010! will be most effectively centered in the expanded display if the lefthand X axis address group consisting of 000, 001, 010, and 011 is selected for expansion, that is, if relay 250 of FIG. 3b is energized.

If the message of interest has an original address of 011, however, selection of the lefthand address group would be less appropriate since such a message, when displayed on an expanded address scale, would appear at an address of 110, near the high-hand edge of the display 8 screen. It would be more appropriate that the overlap address group of O10, 011, 100, 101 be selected, since this would put the message of interest nearer to the center of the display screen, at a screen address of 010. In other words, it would be more appropriate that relay 202 be energized.

It will be seen, then, that while two bits are sufiicient to establish the legality of a display address in one axis as abovedescribed, an extra bit is required to identify which of two overlapping available address groups is most appropriate to the display of certain messages of interest. In the production of an expanded display by operation of the circuitry of FIGS. 3, 3a and 312 it is most appropriate that relay 250 be energized if the message of interest has an X axis address of 000, 001, or 010; that relay 202 be energized if the message of interest has an X axis address of 011 or and that relay 252 be energized if the message of interest has an axis address of 101, 100 or 111. Accordingly, selection of the appropriate address group

select relay

202, 250, 252 can be accomplished by decoding the most significant three hits of the key message of interest, the display of which has been detected by the photocell device 170 as described above in connection with FIG. 2.

In FIG. 3a the photocell device 9170 is shown to comprise a photocell 300, an amplifier 302 and the trigger switch 173 of the device. When the display of a message is detected by the device, an output pulse appears on line 172 and is conveyed by connection terminal 304 to the sampling input line 306 of the key message address gates 166 of the X axis circuitry. The pulse on line 172 is supplied also to terminal 308 whence it is conveyed to the Y axis circuitry which, again, is substantially identical to the X axis circuitry and is therefore not shown in FIG. 3a. 5;

In the circuit configurations shown, the X axis key message address gate 166 comprises

individual gate circuits

310, 312, 314, 316, 318, 320 connected via

lines

322, 324, 326, 328, 330, 332 to be conditioned by the outputs of flip-

flops

214, 216, 218 of the X message address register 132. These gate circuits are operative to effect non-destructive, double line transfer of the contents of the register 132 to the key message address register 162 by and uponthe appearance of a sampling pulse on line 306. The sampling pulse on line 306 results from the detection of the display of the message of interest, that is, the key message, by response of the photocell 300 to the light of the display of that message. The X axis address of that message is present in the X axis address register :132 during that display. Therefore, the foregoing operation results in preservation of that address in the register 162. The level outputs of the key message address register 162 flip-

flops

310, 312, 314, 316, 318, 320 are connected as shown to AND

circuits

340, 342, 344, 346, 348 and 350. AND circuit 340 is connected to be conditioned by the presence of a 1 stored in flip-flop 334 concurrently with a l stored in flip-flop 336. This AND circuit 340 is not connected to flip-flop 338 and therefore passes a signal whenever the address stored in register 162 is or 111. Accordingly, the addresses which will energize AND circuit 340 may be written as I l-f AND circuit 342 is connected to be responsive to an address of 101, circuit 344 to an address of 100, circuit 346 to an address of 011, circuit 348 to an address of "010," and circuit 350 to addresses of 000 or 001 or, in other words, 00-.

The outputs of

circuits

340 and 342 are combined by an OR circuit 352 which thereby yields an output on line 358 whenever the contents of the key message address register 162 are "101, 110 or 111. It will be recalled that these are the three addresses that make it most appropriate that relay 252 be energized during presentation of a display on an expanded scale. Accordingly, line 358 is connected, through contact. 200-8 (which is closed when an expanded display is being presented), to the input of relay 252.

Similarly, the output of OR circuit 354 is connected via line 360 to energize relay 202 when the contents of the key message address register 162 are 011 or 100. Finally, the output of OR circuit 356 is connected via line 362 for energization of relay 250 when the contents of the register 162 are 000, 001, or 010.

The foregoing scheme of circuit organization and mode of operation can be extended with facility for embodiment in display systems having many more address bits in each axis than the three shown in FIGS. 3, 3a and 3b and many more available levels of expansion than the times one and times two choices X1 and X2 shown in that figure. It will be understood that any number of lower order bit significant flip-flops can be added to the register 132, with corresponding addition of channels in the decoder 136 and shifting selection means analagous to contacts 200-3 and 200-5. Higher levels of expansion can be enabled by providing cross-over connections similar to those controlled by contacts S2004 and 200-5 for effecting a shift of two bit positions for times four expansion, three bit positions for times eight expansion, and so on. Of course, as the level of expansion is increased, the areas which may be selected for expansion become different and smaller divisions of the original display. Progressively lower order bits of the original addresses become the most significant bit in the expanded address and require complementing means.

FIGS. 7a and 7b constitute a diagram of one display axis, showing address boundaries pertinent to the selection of the most appropriate square or address group for expansion factors of two, four, eight, sixteen and thirtytwo. Also shown are the address group boundaries for integral and overlap divisions of the axis for those levels of expansion. This chart may be correlated to the diagrams of FIG. 6 by observing that the integral division 1-33 in FIG. 7a represents the X axis interval corresponding to

areas

180, 182, and 188 in FIG. 6, and the Y axis interval corresponding to

areas

180, 184 and 194 in that figure. Overlap division 17-49 in FIGS. 7a and 7b corresponds for the X axis to FIG. 6 areas 194, @196, 198 and for the Y axis to areas 188, 190, 198. Integral division 33-65 in FIG. 7b corresponds for the X axis to FIG. 6

areas

184, 186, 190 and, for the Y axis, to

areas

182, 186 and 196 in FIG. 6.

The chart of FIGS. 7a and 7b shows the manner in which the same scheme is carried to higher levels of expansion. For example, in the case of times sixteen expansion, the integral divisions or address groups available for display are bounded by

lines

1, 5, 9, 13, 17 and so on, while the overlap groups are bounded by

lines

3, 7, 11, 15, 19 and so on. If a key message address falls between

boundary lines

1 and 4, then .the address group bounded by

lines

1 and 5 is the most appropriate; if the address falls between

boundaries

4 and 6, then the overlap address group bounded by

lines

3 and 7 is most appropriate; if the key message address falls between

boundaries

6 and 8, then the next integral address group bounded by

lines

5 and 9 is most appropriate; if the key address falls between

boundaries

8 and 10, then the next overlap address group bounded by

lines

7 and 11 is most appropriate, and so on.

FIGS. 80 and 8b constitute a table showing seven bit, binary encoded display addresses corresponding in FIGS. 70 and 7b to the

boundaries

2, 3 through 64, and mid-points or interpolations between those boundaries (2.5 through 63.5). The closest seven bit approach to boundary line 1 is 0000000 and the closest seven bit ap-v dress group for centering and expansion, at expansion levels of times two, times four, times eight, times sixteen, and times thirty-two. The boundaries are the numbered lines (and, in the case of times thirty-two expansion, the unnumbered mid-points between them) of FIGS. 7a and 7b, and the addresses are the corresponding addresses of FIGS. 8a and 8b. Bits which are not significant for key message purposes, that is ones which do not afiect the division selection are shown by a dash,

TABLE I Integral Divisions Overlap Divisions Expansion Display Key Address Display Key Address Factor Axis Axis Division Division Bound- Bound- Signifi- Bound- Bound- Signifiarles aries cant; aries aries cant Bits Bits Table I is carried to only three successive display axis divisions although in every case save times two (X2) expansion there are additional divisions defined by FIGS. 7a and 7b and 8a and 8b. For example, in the case of X32 expansion, there are-thirty-two integral divisions plus thirty-one overlap divisions.

In every expansion level, the lower boundary of the key address for the axis division beginning at boundary 1 is l, and the upper boundray of the key address for the axis division ending at boundary 65 is 65, since there is no overlap division required at either end of the axis. For this reason, the key message addresses defining these extreme boundaries have one less significant bit than the other key message .address employed in the same expansion level. For example, at times two, the lowest and highest key message boundaries have two significant bits; all the others in the same expansion level have three.

Table II shows the number of high order binary bits pertinent to selection of an address group for display.

TABLE II Expansion Factor X2 X4 X8 X16 X32 Significant binary bits to define integral division 1 2 3 4 5 Significant binary bits to define overlap divisions 2 3 4 5 6 Significant binary bits to select most appropriate division in system having mtegral and overlap divisions-.. 3 4 5 6 7 FIG. 9 shows, schematically, address group selector means for one axis, analogous to the key message decoder means of FIG. 3 but adapted to eifect selection of the most appropriate address group for display of a key message and its environs at a plurality of levels of expansion, in accordance with the criteria shown in FIGS. 7a and 7b and FIGS. 80 and 8b and Tables I and II.

Since expansion levels to times thirty-two (X32) are shown, the key message address register 162' has facilities for storing seven numerical orders. In the illustrated embodiment, it is a seven bit binary register having two line per bit output via the cable 380. A first branch 382 of the cable 380 feeds a decoder 384 through a six contact, normally open relay 386. The decoder 384 may be identical to the key address AND, OR

decoder organization

340, 342, 346, 348, 350, 352, 354, 356 of FIG. 3a, and has a three-line output cable 388 identical in function to the output on

lines

358, 360, 362 of FIG. 3a. Additional decoder means 390, 392, 394, 396 respond to four, five, six, and seven high order bits from the key message address register 162; as hereinabove explained, when called into action by corresponding normally

open relays

398, 400, 402, 406.

Switch 160 may be ganged with expansion level select switch means analogous to switch 160 of FIG. 3b to effect the corresponding expansion, as hereinabove described, as switch 160 is turned to one or another of its positions X2, X4, etc. When turned to one of those positions, switch 160' is operative to energize and close .the

corresponding relay

385, 398, 400, 402 or 406, whereby an output which is unique to the address group most appropriate for expansion and display appears on a unique one of the lines in one of the

decoder output cables

388, 408, 410, 412, 414, for operation of sensing and complementing circuitry analogous to the circuit means 150, 202-1, 202 2 of FIG. 3b.

It will be observed that in the illustrated embodiments of the invention, the key message address or area select AND-OR decoder means is interlocked with and thus programmed by the expansion select switch, and, in turn operates to program the legal address sensing AND-OR decoder means.

The AND and OR components of the area select decoder may be of the same general kind as the legal address sensing decoder. Any suitable kinds of components may be used for these purposes in accordance with the required speed of operation of the system, cost and other factors. For example, the afore-referenced Gerhardt patent refers to component kinds which are in many instances suitable for these and other parts of the system.

Although FIG. 9 shows, for schematic clarity, separate decoders for various levels of expansion, permutations (e.g. 000, 001, 010, etc.) may readily be made available from the area or axis division select decoders for lower levels (e.g. X2) of expansion for use in the decoding of additional bits or digits for employment in the decoding for higher expansion levels. This kind of decoder is sometimes called a tree decoder.

The key message registers may be constructed as counters so that information therein may be stepped up or down to change the display address group selection from the original display. Another register may be employed in each case to retain the original key message address, to enable the returning of the key message register to its former.content after that stepping operation.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. In a data processing system,

display means,

and means foroperatively supplying to said display means successive groups of signals representing messages and digital display addresses related thereto,

said display means having a display screen,

said addresses occurring along an axis of said screen divisable evenly into consecutive address groups comprising integral divisions of said axis,

means operative to provide a digital key address rep presentative of a positional value on said screen,

expansion level control means,

message display selection means comprising logical decoder means sensitive to a high order portion of said key address to define an address decision interval of which the key address is a member, said logical decoder means being operative to permit display of only those messages whose unaltered address equivalent contains high order bits defining a display interval containing said decision interval,

and centering and expansion means comprising controllable means to shift the weight significance of the message addresses n orders and to delete it high order bits thereof, wherein n is the power to which expansion is to be effected.

2. In a data processing system which includes display means and means for operatively supplying to said display means successive groups of signals representing messages and diigtal display addresses related thereto,

a display console comprising, i

a first register connected to receive said addresses in succession,

key message select means operable to identify a particular one of said groups of signals by its display address,

a second register,

control means connected to said first register and responsive to said key message select means for controlling the transfer of the key address from said firstregister into said second register,

expansion level control means,

said addresses occurring along an axis divisable evenly into consecutive address groups comprising integral divisions of said axis, and into overlap divisions of the same size centered on the boundaries of said integral divisions,

message display selection means comprising logical decoder means sensitive to it plus two high order bits of said key address, wherein n is the power to which expansion is to be effected, to define an address decision interval of which the key address is a memher, said logical decoder means being operative to permit display of only those messages whose unaltered address equivalent contains 21 plus one high order bits defining a display interval larger than and containing said decision interval,

and centering and expansion means comprising controllable means to shift the weight significance of the message addresses 1: orders and to delete 12 high order bits thereof,

said centering and expansion means being responsive to detection of an overlap division selection by said selection means additionally to complement the highest order remaining bit of the addresses of the messages to be displayed.

3. In a data processing system,

display means,

and means for operatively supplying to said display means successive groups of signals representing messages and digital display addresses related thereto,

said display means comprising address input means connected to receive said addresses in succession,

a manipulatable sensing device adapted to produce a signal by and upon the display of a message selected thereby,

a register,

control means connected to said address input means and responsive to the signal produced by said sensing device for controlling the transfer of information from said address input means into said register to constitute a key address therein,

expansion level control means,

message display selection means comprising a logical decoder sensitive to at least 11 plus one high order bits of said key address, wherein n is the power to which expansion is to be effected, to define an address decision interval of which the key address is a member, said logical decoder means being operative to permit display of only those messages whose unaltered address equivalent contains n plus one high order bits defining a display interval containing said decision interval,

and centering and expansion means comprising controllable means to shift the weight significance of the message addresses 22 orders and to delete it high order bits thereof,

4. In a data processing system,

display means comprising a plurality of display consoles and means for operatively supplying to said display consoles in parallel successive groups of signals representing messages and digital display addresses related thereto,

each of said display consoles comprising address input means connected to receive said addresses in succession,

a manipulatable sensing device adapted to produce a signalby and upon the display of a message selected thereby,

a register,

control means connected to said address input means and responsive to the signal produced by said sensing device for controlling the transfer of information from said address input means into said register to constitute a key message address therein,

expansion level control means,

message display selection means comprising logical decoder means sensitive to n plus two high order bits of said key address, wherein n is the power to which expansion is to be elfected, to define an address decision interval of which the key address is a member, said logical decoder means being operative to permit display of only those messages whose unaltered address equivalent contains n plus one high order bits defining a display interval larger than and containing said decision interval,

and centering and expansion means comprising controllable means to shift the weight significance of the message addresses n orders and to delete n high order bits thereof,

5. In a data processing system which includes display means and means for operatively supplying to said display means successive groups of signals representing messages and digital display addresses related thereto,

a display console comprising,

address input means connected to receive said addresses in succession,

a register,

control means connected to said address input means and responsive to the signal produced by said sensing device for controlling the transfer of information from said address input means into said register to constitute a digital key address therein,

expansion level control means,

message display selection means comprising logical decoder means sensitive to n plus two high order bits of said key address, wherein n is the power to which expansion is to be effected, to define an address decision interval of which the key address is a member, said logical decoder means being operative to permit display of only those messages whose unaltered address equivalent contains n plus one high order bits defining a display interval larger than and containing said decision interval,

and centering and expansion means comprising controllable means to shift the weight significance of the message addresses n orders and to delete it high order bits thereof,

6. In a data processing system which includes display means and means for operatively supplying to said display means successive groups of signals representing messages and binary encoded digital display addresses related thereto,

a display console comprising,

a first register connected to receive said addresses in succession,

a manipulatable sensing device adapted to produce a signal by and upon the display of a selected message,

a second register,

control means connected to said first register and responsive to the signal produced by said sensing device for controlling the transfer of information from said first register into said second register to constitute a key address therein,

expansion level control means,

message display selection means comprising logical decoder means sensitive to n plus two high order bits of said key address, wherein n is the power to which expansion is to be effected, to define an address'decision interval of which the key address is a member, said logical decoder means being operative to permit display of only those messages whose unaltered address equivalent contains n plus one high order bits defining a display interval larger than and containing said decision interval,

said centering and expansion means being repsonsive 3,256,516 15 16 to detection of an overlap division selection by said 3,037,192 5/1962 Everett 340 -172.5

selection means additionally to complement the highest order remaining bit of the addresses of the mes- ROBERT BAILEY Primary Examiner sages to be displayed.

5 References Cited by the Examiner MALCOLM A. MORRISON, Examiner.

UNITED STATES PATENTS P. L. BERGER, Assistant Examiner. 3,011,164 11/1961 Gerhardt 340-324.1

Claims

1. IN A DATA PROCESSING SYSTEM, DISPLAY MEANS, AND MEANS FOR OPERATIVELY SUPPLYING TO SAID DISPLAY MEANS SUCCESSIVE GROUPS OF SIGNALS REPRESENTING MESSAGES AND DIGITAL DISPLAY ADDRESSES RELATED THERETO, SAID DISPLAY MEANS HAVING A DISPLAY SCREEN, SAID ADDRESSES OCCURRING ALONG AN AXIS OF SAID SCREEN DIVISABLE EVENLY INTO CONSECUTIVE ADDRESS GROUPS COMPRISING INTEGRAL DIVISIONS OF SAID AXIS, MEANS OPERATIVE TO PROVIDE A DIGITAL KEY ADDRESS REPPRESENTATIVE OF A POSITIONAL VALUE ON SAID SCREEN EXPANSION LEVEL CONTROL MEANS, MESSAGE DISPLAY SELECTION MEANS COMPRISING LOGICAL DECODER MEANS SENSITIVE TO A HIGH ORDER PORTION OF SAID KEY ADDRESS TO DEFINE AN ADDRESS DECISION, INTEVAL OF WHICH THE KEY ADDRESS IS A MEMBER, SAID LOGICAL DECODER MEANS BEING OPERATIVE TO PERMIT DISPLAY OF ONLY THOSE MESSAGES WHOSE UNALTERED ADDRESS EQUIVALENT CONTAINS HIGH ORDER BITS DEFINING A DISPLAY INTERVAL CONTAINING SAID DECISION INTERVAL AND CENTERING AND EXPANSION MEANS COMPRISING CONTROLLABLE MEANS TO SHIFT THE WEIGHT SIGNIFICANCE OF THE MESSAGE ADDRESS N ORDERS AND TO DELETE N HIGH ORDER BITS THEREOF, WHEREIN N IS THE POWER TO WHICH EXPANSION IS TO BE EFFECTED.