US3223988A

US3223988A - Currency detectors

Info

Publication number: US3223988A
Application number: US35355A
Authority: US
Inventors: Donald M Danko
Original assignee: National Rejectors Inc GmbH
Current assignee: Crane Payment Innovations GmbH
Priority date: 1960-06-10
Filing date: 1960-06-10
Publication date: 1965-12-14
Anticipated expiration: 1982-12-14

Description

Dec. 14, 1965 D. M. DANKO CURRENCY DETECTORS Filed June 10, 1960 IN V EN TOR.

BY DONALD M. DANKO ATTORNEY tion, provides high gain, and has a low noise level.

United States Patent 3,223,988 CURRENCY DETECTORS Donald M. Danko, Parma, Ohio, assignor to National 131ejectors, Inc., St. Louis, Mo., a corporation of Missouri Filed June 10, 196i Ser. No. 35,355 2 Ciaims. (Cl. 340174.1)

This invention relates to improvements in currency detectors. More particularly, this invention relates to improvements in methods and apparatus for identifying authentic paper currency.

It is, therefore, an object of the present invention to provide an improved method and apparatus for identifying authentic paper currency.

Co-pending patent application Serial Number 849,066, now abandoned, for Currency Detectors, which was filed on October 27, 1959, by Theodore H. Smith, Sigmund Kramer and myself, discloses the movement of paper currency past a magnetic head at a predetermined rate of speed to enable authentic paper currency, that is printed with ink having magnetic properties, to generate voltage variations that cause the acceptance of such currency. That application discloses an electronic circuit which includes a pre-amplifier; and that pre-amplifier is well adapted for use with currency detectors that accept paper currency of a predetermined denomination. It is becoming progressively important to be able to detect paper bills of different denominations; and hence it would be desirable to provide a pre-amplifier that is well adapted for use with currency detectors that accept paper bills of different denominations. The present invention provides such a pre-amplifier; and it is therefore an object of the present invention to provide a pre-amplifier that is well adapted for use with currency detectors that accept paper bills of different denominations.

The pre-amplifier provided by the present invention coacts with the magnetic head of the currency detector to constitute a high pass amplifier that can provide a substantially flat frequency response throughout the range of frequencies generated by the paper bills of different denominations which are to be accepted by the currency detector. Further, that pre-amplifier is stable in opera- It is, therefore, an object of the present invention to provide a pre-amplifier that is stable in operation, that provides high gain, that has a low noise level, and that combines with the magnetic head of a currency detector to constitute a high pass amplifier that can provide a substantially flat frequency response throughout the range of frequencies generated by the paper bills of different denominations which are to be accepted by the currency detector.

The pre-amplifier of the present invention uses capacitance and resistance to couple voltage variations, generated in the coils of the magnetic head, to the first stage of pre-amplification; and it uses a capacitance value which coacts with the overall inductance value of those coils to produce resonance at a frequency close to the lower end of the desired frequency range. In doing so, that pre-amplifier coacts with the magnetic head to provide the needed high gain at the lower end of the desired frequency range. That pre-amplifier uses transistors rather than thermionic tubes; and it uses transistors which have beta cut'ofi' characteristics in the intermediate range. Those beta cut-off characteristics coact with the distributed capacities in the magnetic head to permit the attainment of a desirable gain in the intermediate portions of the desired frequency range but coact with those distributed capacities to provide a desirable limitation on the gain at the upper end of the desired frequency range; and, in doing so, those beta cut-off characteristics coact with those distributed capacities to tend to maintain the gain at those intermediate and higher frequencies at values comparable to the gain values at the lower end of the desired frequency range. In this way, the pre-amplifier of the present invention coacts with the magnetic head of a currency detector to help produce a substantially flat frequency response throughout the desired frequency range.

The interaction of the inductance of the magnetic head with the capacitance of the resistance-capacitance coupling between that magnetic head and the first transistor stage is additionally desirable because it increases the rate of rejection at the low end of the desired frequency range. That increased rate of rejection is important in reducing all undesired low frequency modulation, whether that modulation be due to hum, noise, or transients. In this Way, the pie-amplifier provided by the present invention coacts with the magnetic head of a currency detector to minimize low frequency modulation.

The capacitor of the resistance-capacitance coupling, which the pre-amplifier of the present invention uses to couple the magnetic head to the first transistor stage, coacts with the coils of that magnetic head to constitute a tuned circuit. Theoretically it would seem desirable to make the input impedance of that transistor stage substantially equal to the impedance of that tuned circuit, because the resultant impedance matching would provide maximum gain. The present invention does not, however, make the input impedance of the first transistor stage substantially equal to the impedance of that tuned circuit; instead, the present invention makes the input impedance of that transistor stage very much smaller than the impedance of that tuned circuit. In doing so, the present invention reduces the overall Q of the combination of magnetic head and pre-amplifier, and thereby prevents sharp peaking in the desired frequency range. It is, therefore, an object of the present invention to provide a pre-amplifier which has a coupling capacitor that coacts with the coils of a magnetic head to constitute a tuned circuit and which makes the input impedance of the first transistor stage very much smaller than the impedance of that tuned circuit.

The low input impedance of the first transistor stage is additionally desirable because it minimizes the effects which noise and other transients can have. Noise and other transients can coact with a high input impedance to produce voltage variations from which the pre-amplifier could not quickly recover, and this is undesirable. By using a low input impedance for the first transistor stage and by also using a low input impedance for the second transistor stage, the present invention limits the voltage variations which can be produced by noise and other transients to low values that are not troublesome.

The low input impedances of the transistor stages will coact with the beta cut-off characteristics of the transistors of those stages and with the distributed capacities of the magnetic head to increase the rate of rejection at frequencies above the upper end of the desired frequency range. That increased rate of rejection is important in reducing high frequency modulation, whether that modulation be due to harmonics, noise, or transients. In this way, the pre-amplifier provided by the present invention coacts with the magnetic head of a currency detector to minimize undesired high frequency modulation.

Other and further objects and advantages of the present invention should become apparent from an examination of the drawing and accompanying description.

In the drawing and accompanying description, a preferred embodiment of the present invention is shown and described but it is to be understood that the drawing and accompanying description are for the purpose of illustraand grounded terminal 24.

tion only and do not limit the invention and that the invention will be defined by the appended claims.

The drawing consists of a schematic diagram of the pre-amplifier of the present invention combined with the magnetic head of a currency detector.

Referring to the drawing in detail, the numeral 20 denotes a magnetic head which has a low inductance; and, in one preferred embodiment of the present invention, that inductance is eight hundred and seventy millihenries. The coils on the magnetic head 20 are connected in series, and they are connected to the input terminals 8 of the preamplifier provided by the present invention.

One end of a resistor 10 is connected to the upper of the terminals 8, and the other end of that resistor is connected to a positive voltage supply terminal 14 by a resistor 16. The other terminal 8 is connected to a negative Current will flow through the resistors 16 and 10 and through the coils of the magnetic head 20 to provide the biasing current needed by that head. A capacitor 12 is connected to the grounded terminal 24 and to the junction of resistors 10 and 16; and that capacitor coacts with the resistor 16 to provide de-coupling.

The numeral 18 denotes a coupling capacitor that is connected between the upper terminal 8 and the base of a transistor 22. The collector of the transistor 22 is connected to the grounded terminal 24 by serially-connected

resistors

34 and 36. The junction of those two resistors is connected to the base of the transistor 22 by a resistor 32. The base is also connected to the positive terminal 14 by a resistor 28, a resistor 38, and a resistor 40. The emitter of the transistor 22 is connected to the terminal 14 by a resistor 42 and the serially-connected

resistors

38 and 40. A by-pass capacitor 44 is provided for the resistor 42.

A coupling capacitor 26 extends between the collector of the transistor 22 and the base of a transistor 30. The collector of the transistor 30 is connected to the terminal 24 by serially-connected

resistors

46 and 48. The junction of those resistors is connected to the base of the transistor 30 by a resistor 50. That base is also connected to the terminal 14 by a resistor 52 and by resistor 40. The emitter of the transistor 30 is connected to the terminal 14 by a resistor 54 and by resistor 40. A by-pass capacitor 56 is provided for the resistor 54.

A resistor 58 is connected intermediate the resistor 38 and the grounded terminal 24. A by-pass capacitor 60 is provided for the resistor 58. A by-pass capacitor 62 is connected between the grounded terminal 24 and the junction of

resistors

38 and 40.

A coupling capacitor 64 is connected between the collector of the transistor 30 and terminal 66, which constitutes one of the output terminals of the pre-amplifier. The terminal 24 serves as the other output terminal of the pre-amplifier. The terminals 66 and 24 of the preamplifier will be suitably connected to the input of the next section of the electronic circuit of the currency detector.

The

resistors

40, 38 and 58 constitute a voltage-dividing network; and that network provides a positive voltage at the upper'end of the resistor 54 which is materially smaller than the positive voltage at the terminal 14. That network also provides a positive voltage at the upper end of the resistor 42 which is smaller than the voltage at the upper end of the resistor 54. In the said preferred embodiment of the present invention, the voltage at the terminal 14 is one hundred and eight volts, the voltage at the upper end of the resistor 54 is twenty volts, and the voltage at the upper end of the resistor 42 is five volts.

The

resistors

28, 32 and 36 constitute a further voltagedividing network; and that network establishes the voltage for the base of the transistor 22. The resistor 32 extends between the base of transistor 22 and the junction of

collector resistors

34 and 36, and it feeds back to that base a degenerative direct current and thereby stabilizes the first stage of the pre-amplifier with respect to ambient temperature conditions. Specifically, as the temperature of the transistor 22 increases, the current gain of that transistor will increase; but that current gain will be limited by the said degenerative direct current.

The

resistors

52, 50 and 48 constitute yet another voltage-dividing network, and that network establishes the voltage for the base of the transistor 30. The resistor 50 extends between the base of transistor 30 and the junction of

collector resistors

46 and 48, and it feeds back to that base a degenerative direct current and thereby stabilizes the second stage of the pro-amplifier with respect to ambient temperature conditions.

The voltage variations that are generated in the coils of the magnetic head, as authentic paper bills that are printed with ink having magnetic properties are moved past that head, are coupled to the base of the transistor 22 by capacitor 18; and hence that capacitor performs a coupling function. That capacitor also performs another function, because it coacts with the inductance of the coils of that magnetic head to constitute a series resonant circuit. In the said preferred embodiment of the present invention, the capacitor 18 has a value of onetenth of a microfarad; and hence the resonant frequency of that series resonant circuit will be between five hundred and six hundred cycles per second. This is desirable because it provides a desirable gain at frequencies close to the lower end of the range of frequencies generated by the paper bills of different denominations which are to be accepted by the currency detector.

The interaction of the inductance of the coils of the magnetic head 20 with the capacitance of the capacitor 18 is also important because it increases the rate of rejection at the low end of the desired frequency range. In the said one preferred embodiment of the present invention, that interaction provided a rate of rejection of at least sixteen decibels per octave at the lower end of the desired frequency range. In doing so, that interaction greatly minimized low frequency modulation of the voltage variations from the magnetic head, whether that modulation was due to hum, noise or transients.

In the said preferred embodiment of the present invention, the

transistors

22 and 30 are 2Nl374 PNP germanium transistors; and hence they have beta cut-off characteristics in the intermediate range of from twentyfive kilocycles to one megacycle. Such beta cut-off characteristics coact with the distributed capacities in the magnetic head 20 to assure the attainment of a desirable gain in the intermediate portions of the desired frequency range but coact with those distributed capacities to provide a desirable limitation on the gain at the upper end of the desired frequency range. In this way, the preamplifier of the present invention coacts with the magnetic head of the currency detector to help produce a substantially flat frequency response throughout the desired frequency range.

The impedance of the series resonant circuit constituted by capacitor 18 and by the coils of magnetic head 20 is high; but the input impedance of the first transistor stage of the pre-amplifier in the said preferred embodiment of the present invention is lowbeing about twenty two hundred ohms at a thousand cycles per second. This means that the overall Q of the combination of magnetic head and pre-arnplifier is very much less than it would be if the input impedance of the first transistor stage was substantially equal to the impedance of the series resonant circuit. That reduced Q is important in preventing sharp peaking in the desired frequency range.

The second transistor stage has a low input impedance comparable to that of the first transistor stage. As a result, noise and other transients cannot produce voltage variations from which the pre-amplifier could not quickly recover. Consequently, the pre-amplifier provided by the present invention is stable in operation and has a low noise level.

The low voltage for the first transistor stage, namely, five volts at the upper end of the resistor 42 is desirable because it enables that stage to operate in a quiet condition. The higher voltage for the second transistor stage, namely, twenty volts at the upper end of resistor 54, is desirable because it enables that stage to drive the subsequent section of the electronic circuit sufficiently to avoid clipping of the desired voltage variations.

The low input impedances of the two transistor stages coact with the beta cut-off characteristics of the

transistors

22 and 30 and with the distributed capacities of the magnetic head 20 to increase the rate of rejection at frequencies above the upper end of the desired frequency range. That increased rate of rejection is important in reducing the high frequency modulation of the voltage variations from the magnetic head 20, whether that modulation is due to harmonics, noise or transients. In this way, the pre-amplifier provided by the present invention coacts with the magnetic head of the currency detector to minimize undesired high frequency modulation.

Whereas the drawing and accompanying description have shown and described one preferred embodiment of the present invention it should be apparent to those skilled in the art that various changes may be made in the form of the invention without affecting the scope thereof.

What I claim is:

1. In a currency detector, the combination of a magnetic head that engages a bill to generate voltage variations and that has a low inductance, a resistance-capacitance network that couples said magnetic head to a transistor stage of a pre-amplifier, the capacitor of said resistance-capacitance network being connected in series relation with the coil of said magnetic head to constitute a series resonant circuit, and a second resistance-capacitance network that couples said transistor stage to a sec ond transistor stage of said pre-arnplifier, the capacitor of the first said resistance-capacitance network having a capacitance that coacts with the inductance of the coil of said magnetic head to make said capacitor and said coil constitute a series resonant circuit that resonates at a frequency below but adjacent the lower end of a desired frequency range, said series resonant circuit providing a high gain for frequencies below but adjacent said lower end of said desired frequency range, said resistancecapacitance networks passing signals within said desired frequency range but said series resonant circuit providing a high rate of rejection below the resonant frequency thereof and thus below said lower end of said desired frequency range and thereby minimizing low frequency modulation of voltage variations generated in said coil of said magnetic head as a bill engages and moves relative to said magnetic head, the first said transistor stage having an input impedance that is very much smaller than the impedance of said series resonant circuit to reduce the Q of the combination of said magnetic head and preamplifier, thereby preventing sharp peaking in said desired frequency range, said second transistor stage having a low input impedance that coacts with said low input impedance of the first said transistor stage to reduce the effect which noise and other transients can have upon the voltage variations generated in said coil of said magnetic head, the transistor of the first said transistor stage and the transistor of said second transistor stage coacting with the distributed capacities of said magnetic head to permit the attainment of desired gain at frequencies above said lower end of said desired frequency range and to limit the gain at frequencies adjacent the upper end of said desired frequency range, said series resonant circuit coacting with said transistors to provide a substantially flat frequency response throughout said desired frequency range, said transistors coacting with said distributed capacities and with said low input impedances of said transistor stages to increase the rate of rejection at frequencies above said desired frequency range, said capacitor of the first said resistance-capacitance network coacting with the first said transistor stage to constitute a high pass amplifier, the capacitor of said second resistance-capacitance network coacting with said second transistor stage to constitute a second high pass amplifier.

2. In a currency detector, the combination of a magnetic head that engages a bill to generate voltage variations and a resistance-capacitance network that couples said magnetic head to a transistor stage of an amplifier, the capacitor of said resistance-capacitance network being connected in series relation with the coil of said magnetic head to constitute a series resonant circuit, the capacitor of said resistance-capacitance network having a capacitance that coacts with the inductance of the coil of said magnetic head to make said capacitor and said coil constitute a series resonant circuit that resonates at a frequency below but adjacent the lower end of a desired frequency range, said series resonant circuit providing a high gain for frequencies below but adjacent said lower end of said desired frequency range, said resistancecapacitance network passing signals within said desired frequency range but said series resonant circuit providing a high rate of rejection below the resonant frequency thereof and thus below said lower end of said desired frequency range and thereby minimizing low frequency modulation of voltage variations generated in said coil of said magnetic head, said transistor having an input impedance that is very much smaller than the impedance of said series resonant circuit to reduce the Q .of the combination of said magnetic head and said amplifier, thereby preventing sharp peaking in said desired frequency range.

References Cited by the Examiner UNITED STATES PATENTS 2,213,246 9/1940 Heller 179-lO0.2 2,806,181 9/1957 Rockafellow 32441 2,861,258 11/1958 Walsh et al. 340174.1 2,924,812 2/1960 Merritt 340-149 3,026,380 3/1962 Reher et a1. 179100.2 3,068,327 12/1962 Davidson 179-100.2

IRVING L. SRAGOW, Primary Examiner.

EVERETT R. REYNOLDS, Examiner.

Claims

1. IN A CURRENCY DETECTOR, THE COMBINATION OF A MAGNETIC HEAD THAT ENGAGES A BILL T GENERATE VOLTAGE VARITIONS AND THAT HAS A LOW INDUCTANCE, A RESISTANCE-CAPACITANCE NETWORK THAT COUPLES SAID MAGNETIC HEAD TO A TRANSISTOR STAGE OF A PRE-AMPLIFIER, THE CAPACITOR OF SAID RESISTANCE-CAPACITANCE NETWORK BEING CONNECTED IN SERIES RELATION WITH THE COIL OF SAID MAGNETIC HEAD TO CONSTITUTE A SERIES RESONANT CIRCUIT, AND A SECOND RESISTANCE-CAPACITANCE NETWORK THAT COUPLES SAID TRANSISTOR STAGE TO A SECOND TRANSISTOR STAGE OF SAID PRE-AMPLIFIER, THE CAPACITOR OF THE FIRST SAID RESISTANCE-CAPACITANCE NETWORK HAVING A CAPACITANCE THAT COACTS WITH THE INDUCATANCE OF THE COIL OF SAID MAGNETIC HEAD TO MAKE SAID CAPACITOR AND THE COIL OF CONSTITUTE A SERIES RESONSTANT CIRCUIT THAT RESONATES AT A FREQUENCY BELOW BUT ADJACENT THE LOWER END OF A DESIRED FREQUENCY RANGE, SAID SERIES RESONANT CIRCUIT PROVIDING A HIGH GAIN FOR FREQUENCIES BELOW BUT ADJACENT SAID LOWER END OF SAID DESIRED FREQUENCY RANGE, SAID RESISTANCECAPACITANCE NETWORKS PASSING SIGNALS WITHIN SAID DESIRED FREQUENCY RANGE BUT SAID SERIES RESONANT CIRCUIT PROVIDING A HIGH RATE OF REJECTION BELOW THE RESONANT FREQUENCY THEREOF AND THUS BELOW SAID LOWER END OF SAID DESIRED FREQUENCY RANGE AND THEREBY MINIMIZING LOW FREQUENCY MODULATION OF VOLTAGE VARIATIONS GENERATED IN SAID COIL OF SAID MAGNETIC HEAD AS A BILL ENGAGES AND MOVES RELATIVE TO SAID MAGNETIC HEAD, THE FIRST SAID TRANSISTOR STAGE HAVING AN INPUT IMPEDANCE THAT IS VERY MUCH SMALLER THAN THE IMPEDANCE OF SAID SERIES RESONSANT CIRCUIT TO REDUCE THE Q OF THE COMBINATION OF SAID MAGNETIC HEAD AND PREAMPLIFIER, THEREBY PREVENTING SHARP PEAKING IN SAID DESIRED FREQUENCY RANGE, SAID SECOND TRANSISTOR STAGE HAVING A LOW INPUT IMPEDANCE THAT COACTS WITH SAID LOW INPUT IMPEDANCE OF THE FIRST SAID TRANSISTOR STAGE TO REDUCE THE EFFECT WHICH NOISE AND OTHER TRANSIENTS CAN HAVE UPON THE VOLTAGE VARIATIONS GENERATED IN SAID COIL OF SAID MAGNETIC HEAD, THE TRANSISTOR OF THE FIRST SAID TRANSISTOR STAGE AND THE TRANSISTOR OF SAID SECOND TRANSISTOR STAGE COACTING WITH THE DISTRIBUTED CAPACITIES OF SAID MAGNETIC HEAD TO PERMIT THE ATTAINMENT OF DESIRED FREQUENCIES ABOVE SAID LOWER END OF SAID DESIRED FREQUENCY RANGE AND TO LIMIT THE GAIN AT FREQUENCIES ADJACENT THE UPPER END SAID DESIRED FREQUENCY RANGE, SAID SERIES RESONANT CIRCUIT COACTING WITH SAID TRANSISTORS TO PROVIDE A SUBSTANTIALLY FLAT FREQUENCY RESPONSE THROUGOUT SAID DESIRED FREQUENCY RANGE, SAID TRANSISTORS COACTING WITH SAID DISTRIBUTED CAPACITIES AND WITH SAID LOW INPUT IMPEDANCES OF SAID TRANSISTOR STAGES TO INCREASE THE RATE OF REJECTION AT FREQUENCIES ABOVE SAID DESIRED FREQUENCY RANGE, SAID CAPACITOR OF THE FIRST SAID RESISTANCE-CAPACITANCE NETWORK COACTING WITH THE FIRST SAID TRANSISTOR STAGE TO CONSTITUTE A HIGH PASS AMPLIFIER, THE CAPACITOR OF SAID SECOND RESISTANCE-CAPACITANCE NETWORK COACTING WITH SAID SECOND TRANSISTOR STAGE TO CONSTITUTE A SECOND HIGH PASS AMPLIFIER.