US20140223214A1 - Dynamic power mode switching per rail - Google Patents

Dynamic power mode switching per rail Download PDF

Info

Publication number
US20140223214A1
US20140223214A1 US13/950,776 US201313950776A US2014223214A1 US 20140223214 A1 US20140223214 A1 US 20140223214A1 US 201313950776 A US201313950776 A US 201313950776A US 2014223214 A1 US2014223214 A1 US 2014223214A1
Authority
US
United States
Prior art keywords
power
amount
current
rails
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/950,776
Inventor
Walid Nabhane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Priority to US13/950,776 priority Critical patent/US20140223214A1/en
Assigned to BROADCOM CORPORATION reassignment BROADCOM CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NABHANE, WALID
Publication of US20140223214A1 publication Critical patent/US20140223214A1/en
Assigned to BANK OF AMERICA, N.A., AS COLLATERAL AGENT reassignment BANK OF AMERICA, N.A., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: BROADCOM CORPORATION
Assigned to AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. reassignment AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BROADCOM CORPORATION
Assigned to BROADCOM CORPORATION reassignment BROADCOM CORPORATION TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Assignors: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3287Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3058Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G06F11/3062Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3089Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
    • G06F11/3093Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/003Measuring mean values of current or voltage during a given time interval
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40Testing power supplies
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3031Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a motherboard or an expansion card
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3058Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Battery-powered computing systems and devices have been adopted for use in many aspects of daily life. As these systems and devices are more widely adopted and used in place of other computing systems and devices, they are designed to be more flexible and powerful, but are also more complex. With advances in the design of battery-powered computing devices, the availability of sufficient power for the devices continues to be an ongoing concern. For example, each new feature in a battery-powered computing device may require the provision of circuitry that supports a supply of power for the feature.
  • some battery-powered computing systems include power management processing circuitry that manages the supply of power in the system. Over time, this power management processing circuitry may need to adapt to certain needs in battery-operated systems.
  • FIG. 1 illustrates a system for dynamic power mode switching according to an example embodiment.
  • FIG. 2 illustrates a process flow diagram for a process of dynamic power mode switching performed by the system of FIG. 1 according to an example embodiment.
  • FIG. 3 further illustrates the process flow diagram for the process of dynamic power mode switching performed by the system of FIG. 1 according to an example embodiment.
  • FIG. 4 illustrates a power profile maintained by the system of FIG. 1 and the process of FIGS. 2 and 3 for dynamic power mode switching according to an example embodiment.
  • FIG. 5 illustrates a display of a power profile for dynamic power mode switching according to an example embodiment.
  • some battery-powered computing systems include power management processing circuitry that manages the supply of power in the system. Over time, this power management processing circuitry may need to adapt to certain needs in battery-operated systems, such as the need for measurement and profiling of power consumed by various subsystems per power rail.
  • an amount of current supplied by at least one of a plurality of power rails is sensed with a current sense circuit.
  • the amount of current is profiled over a period of time and a profile of power consumed is generated and maintained.
  • one or more power-related decisions may be made in a system.
  • One or more power rails may be powered off or placed into low power mode based on various factors, such as the amount of current being consumed per rail, the temperature of certain system components, or an unexpected ongoing consumption of power in the system.
  • FIG. 1 illustrates a system 10 for dynamic power mode switching according to an example embodiment.
  • the system 10 may embody a computing device that includes a number of general and/or specific purpose circuits, processing circuits, processors, registers, memories, sensors, displays, etc.
  • the system 10 may embody a handheld or portable computing device which is powered from charge stored in a battery.
  • the system 10 may be embodied as part of a cellular telephone, tablet computing device, laptop computer, or other computing device.
  • the system 10 may be embodied as part of a desktop or set top computing device, for example.
  • the system 10 may include one or more displays, microphones, speakers, buttons, indicator lights, haptic feedback elements, memory card readers, etc.
  • the system 10 includes a power management unit (PMU) 100 , a host system-on-chip (SOC) 130 , a system battery 182 , and a system memory 184 .
  • the system 10 also includes certain subsystems such as a bluetooth / wireless local area network (WLAN) subsystem 170 , a global positioning system (GPS) subsystem 171 , a camera subsystem 172 , and a sensor subsystem 173 .
  • the subsystems 170 - 173 are representative subsystems which may be included as elements of the system 10 , and other subsystems are within the scope and spirit of the embodiments described herein.
  • each of the subsystems 170 - 173 , the system memory 184 , and other elements and circuits of the system 10 depend on power for operation. As discussed below, this power may be supplied by and under the control of the PMU 100 .
  • the system battery 182 may be embodied as any rechargeable battery suitable for the application, such as a lithium-ion, nickel-metal-hydride, or other battery variant, without limitation.
  • the system memory 184 may be embodied as a volatile and/or non-volatile random access memory or combination thereof.
  • the system memory 184 may store computer-readable instructions thereon that, when executed by one or more of the processors 140 - 142 of the host SOC 130 , for example, direct the processors 140 - 142 to execute various aspects of the embodiments described herein.
  • the PMU 100 controls and/or facilitates control of the distribution of power from the system battery 182 to the elements of the system 10 , such as the host SOC 130 , the subsystems 170 - 173 , and the system memory 184 , for example. As further described below, depending upon the operating state of the system 10 and/or other factors, the PMU 100 may control the distribution of power to one or more elements of the system 10 , or the PMU 100 may receive instructions to control the distribution of power to one or more elements of the system 10 .
  • the PMU 100 includes a PMU controller 101 , a serial interface slave 102 , a PMU register bank 103 , a current (/) sense circuit 107 , a number 0 -N of analog-to-digital (ADC) circuits 110 - 112 , and a number of power rail circuits 120 - 124 .
  • FIG. 1 illustrates a representative example of elements of the PMU 100 , and it should be appreciated that the PMU 100 may include other elements in various embodiments.
  • the PMU 100 may include several additional power rails in addition to those illustrated in FIG. 1 , to provide power to each element in the system 10 , as needed.
  • each of the power rails 120 - 124 includes a low dropout regulator (LDO) or switching type of power rail.
  • LDO power rail includes a linear voltage regulator that operates suitably even with a relatively low differential input vs. output voltage.
  • a switching power rail includes an active switching circuit that charges and/or discharges reactive circuit elements to boost voltage or current, for example. It should be appreciated that an LDO or switching power rail is selected for each of the power rails 120 - 124 depending upon certain factors such as output voltage, input/output differential voltage, sourced current, power dissipation, cost, etc.
  • the host SOC 130 includes general and/or application specific processors.
  • the host SOC 130 includes a power manager 131 , an application processor 140 , a modem 141 , and a graphics processor 142 .
  • the host SOC 130 may omit one or more of the processors 140 - 142 or include processors in addition to the processors 140 - 142 .
  • the host SOC 130 also includes a subsystem interface 162 and memory interface 163 .
  • the subsystem interface 162 and the memory interface 163 electrically and communicatively couple the subsystems 170 - 173 and the system memory 184 to the host SOC 130 and, particularly, to one or more of the processors 140 - 142 .
  • the application processor 140 may be embodied as a general purpose processor for executing various applications.
  • the application processor 140 may execute an underlying operating system along with applications such as e-mail, short message service (SMS), telephone, camera, web-browser, and other applications, without limitation.
  • applications such as e-mail, short message service (SMS), telephone, camera, web-browser, and other applications, without limitation.
  • SMS short message service
  • the application processor 140 may consume relatively more power during operation.
  • the modem 141 may include a cellular-based (or similar) communications processor for the communication of data wirelessly in connection with radio-frequency front end circuitry, and the graphics processor 142 may include a processor for driving a display of the system 10 .
  • the power manager 131 includes a power or system power control processor 132 , a memory 133 , and a serial interface master 134 .
  • the power processor 132 may be embodied as a relatively small and low power processor or processing circuit for interfacing with the PMU 100 via a serial interface 128 .
  • the serial interface master 134 of the power manager 131 controls the serial interface 128 , although the PMU 100 may control the serial interface 128 in other embodiments.
  • the memory 133 stores computer-readable instructions for execution by the power processor 132 .
  • the PMU 100 may be designed, adapted, and configured to perform operations that support the host SOC 130 , the subsystems 170 - 173 , the system memory 184 , and other elements of the system 10 .
  • the PMU 100 supplies power from the system battery 182 to other elements of the system 10 via the power rails 120 - 124 .
  • the PMU 100 may charge the system battery 182 .
  • the PMU 100 may monitor the voltage VBat of the system battery 182 and store a value of the voltage in the PMU register bank 103 .
  • the PMU controller 101 coordinates and controls the operations of the PMU 100 .
  • the PMU controller 101 may be embodied as a general or specific purpose circuit, processing circuit, processor, state machine, etc.
  • the PMU controller 101 interfaces with the serial interface slave 102 to communicate with the host SOC 130 over the serial interface 128 , interfaces with the power rail circuits 120 - 124 to control and sense power that is supplied to the system 10 , and interfaces with the PMU register bank 103 to store and access data associated with the status of the PMU 100 and the system 10 .
  • the serial interface slave 102 comprises one end of the serial interface 128 that facilitates communication between the PMU 100 and the host SOC 130 .
  • the serial interface 128 is relied upon to communicate data between the PMU 100 and the host SOC 130 .
  • the current sense circuit 107 may be relied upon by the PMU 100 to determine an amount of current or power being supplied by at least one of a plurality of power rails 120 - 124 . In certain embodiments, current sense circuit 107 may determine an amount of current being supplied by each of the power rails 120 - 124 . Data on the amount of current supplied by one or more of the power rails 120 - 124 is relied upon as power profile data by the system 10 . This power profile data may be gathered by the current sense circuit 107 , as further described below, at the direction of the PMU controller 101 (and/or the power manager 131 ) and stored in the PMU register bank 103 . The power profile data may also be communicated by the PMU 100 to the power manager 131 and/or the application processor 140 of host SOC 130 for further evaluation and processing.
  • the ADCs 110 - 112 may be relied upon to determine the voltage VBat of the system battery 182 , the temperature of components in the system 10 , etc. Particularly, the ADCs 110 - 112 may convert analog values of the VBat voltage, and voltages representative of the temperature of components in the system 10 , into digital values for processing and/or storage by the PMU 100 . These digital values include examples of power and management system status data that may be relied upon by the power manager 131 when determining whether to power on or power off certain power rails, as described below.
  • the current sense circuit 107 relies upon representative-scale replica power rail circuits to sense an amount of current being supplied by each of the power rails 120 - 124 .
  • the amount of current may be sensed from time to time or over a period of time as directed by the PMU controller 101 and/or the power manager 131 .
  • the power profile data may be representative of operational aspects of the system 10 .
  • the host SOC 130 may be generally embodied as a full system-on-chip semiconductor device. In this sense, the host SOC 130 integrates various general and/or application specific processors and processing circuits into a single integrated circuit package, reducing space. Overall, the power manager 131 of the host SOC 130 supports the host SOC 130 and the power requirements of the host SOC 130 .
  • each of the power manager 131 , the application processor 140 , the modem 141 , and the graphics processor 142 may be powered by a respective power rail of the PMU 100 in the system 10 .
  • the power manager 131 may be powered by the power rail 1 120
  • the application processor 140 may be powered by the power rail 2 121 .
  • Other elements and/or subsystems in the system 10 and within the host SOC may also be powered, respectively, by one or more power rails of the PMU 100 .
  • Each of the power rails 120 - 124 may be electrically coupled from the PMU 100 to the host SOC 130 and to other subsystems in the system 10 by respective power traces in the system 10 and power pins or pads of the PMU 100 and the host SOC 130 .
  • power manager or power manager circuit 131 of the host SOC 130 may request and retrieve power profile data stored by the PMU 100 .
  • the power manager circuit 131 may further evaluate the power profile data stored in the PMU 100 , while coordinating power consumption by the host SOC 130 and/or the subsystems 170 - 173 in connection with control of the power rails 120 - 124 of the PMU 100 .
  • the power manger 131 may retrieve and evaluate the data on the amount of current or power sourced by each of the power rails 120 - 124 over time. Additionally, the power manger 131 may retrieve and evaluate voltages output by each of the power rails 120 - 124 over time. Using the current and voltage data, the power manger 131 may calculate the amount of power sourced by each of the power rails 120 - 124 .
  • the power manager 131 may evaluate the amount of current, voltage, or power sourced by one or more of the power rails 120 - 124 over a period of time and maintain a power profile of power consumed by one or more system elements in the system. In connection with other system status data from the PMU 100 , the power manger 131 may also identify one or more system elements as a source of heat in the system 10 based on the power profile. In response, the power manger 131 may change an output voltage of or power down a power rail associated with the system element which is the source of heat.
  • the power manager 131 may identify an unexpected ongoing processing status or state of a processor or other system element in the system 10 based on an amount of current identified in the power profile over a certain period of time. In certain cases, the identification of the unexpected ongoing processing status or state may be helpful to diagnose a system problem or troubleshoot hardware or software problems. Additionally, as further described below, the power manager 131 may also set the operating mode of one or more power rails over time based on whether an amount of current or power sourced by the one or more power rails is less than or approaches a threshold of current.
  • the power manager 131 may operate with the PMU 100 to power up and power down power rails in the system 10 in one or more groups or individually, as needed, over time. It is noted that, in certain embodiments, the host SOC 130 (including the power manager 131 ) and the PMU 100 may be combined in an integrated circuit. In this case, the serial interface 128 may be omitted and/or the power manager 131 and the PMU controller 101 may be combined.
  • FIGS. 2 and 3 process flow diagrams illustrating example processes performed by the system 10 for dynamic power mode switching per rail are illustrated. While the process flow diagrams are generally described as being performed by the PMU 100 and/or the power management processor 131 in the system 10 of FIG. 1 , it is noted that other systems may perform the illustrated processes. That is, in various embodiments, systems similar to the system 10 may perform the processes illustrated in FIGS. 2 and 3 .
  • FIGS. 2 and 3 may be considered to depict example steps performed by the system 10 according to one or more embodiments.
  • the process diagrams of FIGS. 2 and 3 illustrate an order, it should be understood that the order may differ from that which is depicted.
  • an order of two or more elements in the process may be scrambled relative to that shown, performed concurrently, or performed with partial concurrence.
  • one or more of the elements may be skipped or omitted within the scope and spirit of the embodiments described herein.
  • FIG. 2 illustrates a process flow diagram for a process 200 of dynamic power mode switching performed by the system 10 of FIG. 1 according to an example embodiment.
  • the process 200 includes sensing an amount of current or power supplied by at least one of a plurality of power rails.
  • the current sense circuit 107 in the PMU 100 may sense the amount of current supplied by one of more of the power rails 120 - 124 from time to time or periodically over time.
  • the current sense circuit 107 may sense the amount of current supplied by each of the power rails 120 - 124 from time to time or periodically over time.
  • the sensed current values are converted to digital values and stored by the PMU 100 in the PMU register bank 103 .
  • the amount of current sourced by the power rails 120 - 124 (and any others) is available as power profile data, for retrieval, reference, and evaluation by the PMU controller 101 and/or the power manager 131 .
  • the process 200 includes profiling and/or evaluating the amount of power or current supplied by the power rails 120 - 124 over a period of time. It is noted that the period of time for the evaluation may vary among embodiments. For example, the period of time may range from substantially no time (e.g., instantaneous) to microseconds, milliseconds, seconds, minutes, hours, etc., without limitation.
  • the profiling may include retrieving power profile data stored in the PMU register bank 103 from time to time as it is updated by the PMU 100 .
  • the power profile data retrieved from the PMU register bank 103 may include an amount of current supplied over time by each of the power rails 120 - 124 , a voltage output over time by each of the power rails 120 - 124 , system temperature data taken over time, and other system parameters such as the voltage VBat of the system battery 182 .
  • the profiling at reference numeral 204 may also include aggregating and organizing the retrieved data. In one embodiment, the data may be aggregated and organized by the power processor and stored, at least in part, in the memory 133 of the power manager 131 .
  • the process 200 includes generating and/or maintaining a power profile of power consumed by one or more of a plurality of system elements in the system 10 based on the profiling performed at reference numeral 204 .
  • the power profile may be maintained for one or more system elements in the system 10 , in association with one or more corresponding ones of the power rails 120 - 124 that supply power to the system elements.
  • FIG. 4 illustrates a power profile 410 maintained by the system 10 of FIG. 1 according to an example embodiment.
  • FIG. 4 generally illustrates current sourced or power consumed in the system 10 with reference to example power rails 1 - 8 , individually, and is representative of power consumed by elements or subsystems of the system 10 .
  • Power consumed or current sourced by the power rails 120 - 124 in the system 10 may be represented among the data plotted for one or more of the power rails 1 - 8 in FIG. 4 .
  • the y-axis in FIG. 4 may be representative of current, volts, or power, for example, in mA, mV, or mW, for example, and the x-axis in FIG. 4 may be representative of time.
  • the process 200 includes reviewing the power profile generated and/or maintained at reference numeral 206 .
  • the reviewing at reference numeral 208 includes comparing power sourced by one or more power rails to one or more thresholds, identifying correlations between power consumption and heat, and/or identifying unexpected ongoing processes, for example, among other processes. That is, at reference numeral 208 , a further review and analysis of the power profile is performed. Further details regarding reviewing the power profile at reference numeral 208 are described below with reference to FIG. 3 .
  • the process 200 includes dynamically switching one or more power rails based on the review of the power profile at reference numeral 208 .
  • the power manager 131 may set one or more of the power rails 120 - 124 into low power mode at reference numeral 210 , as necessary. Additionally or alternatively, the power manger 131 may power off or power on one or more of the power rails 120 - 124 , etc.
  • the operating parameters for any one of the power rails 120 - 124 may be set, modified, and updated individually, based on the review performed at reference numeral 208 .
  • operating settings for an entire group of the power rails 120 - 124 may be quickly modified to low power mode, normal mode, etc., by one command to the PMU 100 .
  • the dynamic switching at reference numeral 210 may be performed in a manner which is flexible, with reference to power data for each individual power rail in the system 10 . It is noted that the process 200 may return to reference numeral 202 as an iterative process of dynamic power mode switching.
  • the process 200 may include displaying a power profile as an amount of power consumed by one or more system elements of the system 10 over time.
  • FIG. 5 illustrates display 500 that may be displayed as representative of amount of power consumed by one or more system elements of the system 10 over time.
  • the display 500 may be rendered on a physical display of the system 10 , at the request of a user.
  • the x-axis may be representative of mA or mW hours or minutes, for example.
  • FIG. 5 generally illustrates power consumed in the system 10 with reference to example power rails 1 - 8 , individually.
  • the each of the power rails on the display 500 may be identified by system element or subsystem.
  • the display 500 may be generated by the system 10 based on actual data sensed by the current sense circuit 107 for current sourced by individual power rails.
  • the display 500 may also be generated using a combination of current and voltage data for respective power rails over time.
  • the display 500 may provide an accurate real-time display of power usage in battery-powered systems.
  • reviewing at reference numeral 208 may include identifying a system element as a source of heat in the system 10 .
  • the power manager 131 may correlate the relatively increased power consumption 402 for the power rail 5 as being associated with an increase in temperature 403 (dashed line) measured by the PMU 100 , based on the overlapped or coincident timing of the increased temperature 403 with the increased power consumption 402 .
  • the power manager 131 and/or the PMU 100 may correlate the element or subsystem associated with the power rail 5 (e.g., the BT/WLAN subsystem 170 , etc.) as being the cause of the increase in temperature. In this manner, the cause or root of increased temperatures in the system 10 may be more accurately identified. Further, if necessary, the power rail 5 may be powered off, set to an alternative voltage, etc., by the power manager 131 to prevent damage to the system 10 , for example.
  • the reviewing at reference numeral 208 includes identifying an unexpected ongoing processing status or state of an element in the system 10 based on the amount of current.
  • the increased and ongoing power consumptions 404 and 406 may be identified at reference numeral 208 by the power manager 131 as unexpected states of power consumption under certain circumstances.
  • abnormal or unexpected power consumption such as the power consumptions 404 and 406 , may be identified and addressed by the power manager 131 .
  • the system or subsystem element associated with the power consumption 404 and the power rail 6 may be reset or powered down, as necessary, to address the problem as illustrated in FIG. 4 .
  • the reviewing at reference numeral 208 includes comparing an amount of current or power to a threshold.
  • the amount of current sourced by the power rail 1 is compared to a current threshold.
  • the current sourced by the power rail 1 may be compared to a 20 mA threshold by the power manager 131 , although use of any current or power threshold values suitable for the application are within the scope and spirit of the embodiments described herein.
  • the amount of current sourced by the power rail 1 is less than the 20 mA threshold (e.g., at reference 408 in FIG.
  • the settings of the power rail 1 may be dynamically switched to place the power rail 1 into a low power mode of operation at reference numeral 210 of FIG. 2 .
  • switching the power rail 1 into the low power mode of operation may help conserve power for the system 10 .
  • the power rail 1 is sourcing such a low amount of current, at least part of the circuitry that supports the power rail 1 may be turned off until more current is demanded.
  • power rails are placed into low power mode depending upon the state of the system, without actual knowledge of measured current consumption. According to aspects of the embodiments described herein, however, power rails may be set into low power mode whenever they are not needed for high current sourcing, based on the power profile 410 maintained by the power manager 131 .
  • the settings of the power rail 1 may be dynamically switched at reference numeral 210 of FIG. 2 , to place the power rail 1 bank into a normal mode of operation.
  • the power rail 1 may be dynamically switched between low power and normal modes of operation based on actual power demands in the system 10 .
  • the power rail 1 may be dynamically switched back to a normal power mode of operation by the power manager 131 at some time before the power rail 1 is expected to need to source more than 20 mA of current, for example, or as it “approaches” the 20 mA threshold.
  • power rails may be set to appropriate operating parameters based on actual real time power consumption rather than on semiconductor characterizations of expected consumption and processing state assumptions. Using accurate power measurements and statistics, the overall power management in battery-powered systems may be improved.
  • each of the PMU controller 101 , the power processor 132 , and or other processors or processing circuits of the system 10 may comprise general purpose arithmetic processors, state machines, or Application Specific Integrated Circuits (“ASICs”), for example.
  • Each such processor or processing circuit may be configured to execute one or more computer-readable software instruction modules.
  • each processor or processing circuit may comprise a state machine or ASIC, and the processes described in FIGS. 5 and 6 may be implemented or executed by the state machine or ASIC according to the computer-readable instructions.
  • the memories and/or registers described herein may comprise any suitable memory devices that store computer-readable instructions to be executed by processors or processing circuits. These memories and/or registers store computer-readable instructions thereon that, when executed by the processors or processing circuits, direct the processors or processing circuits to execute various aspects of the embodiments described herein.
  • the memories and/or registers may include one or more of an optical disc, a magnetic disc, a semiconductor memory (i.e., a semiconductor, floating gate, or similar flash based memory), a magnetic tape memory, a removable memory, combinations thereof, or any other known memory means for storing computer-readable instructions.
  • a semiconductor memory i.e., a semiconductor, floating gate, or similar flash based memory
  • a magnetic tape memory i.e., a magnetic tape memory
  • removable memory i.e., a removable memory, combinations thereof, or any other known memory means for storing computer-readable instructions.
  • processors or processing circuits are configured to retrieve computer-readable instructions and/or data stored on the memories and/or registers for execution.
  • the processors or processing circuits are further configured to execute the computer-readable instructions to implement various aspects and features of the embodiments described herein.

Abstract

Aspects of dynamic power mode switching per rail based on power profiling are described. In one embodiment, an amount of current supplied by at least one of a plurality of power rails is sensed with a current sense circuit. The amount of current is profiled over a period of time and a profile of power consumed is generated and maintained. With reference to the power profile, one or more power-related decisions may be made in a system. One or more power rails may be powered off or placed into low power mode based on various factors, such as the amount of current being consumed per rail, the temperature of certain system components, or an unexpected ongoing consumption of power in the system.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of:
  • U.S. Provisional Application No. 61/759,470, filed Feb. 1, 2013;
  • U.S. Provisional Application No. 61/833,598, filed Jun. 11, 2013;
  • U.S. Provisional Application No. 61/834,513, filed Jun. 13, 2013;
  • U.S. Provisional Application No. 61/836,327, filed Jun. 18, 2013;
  • U.S. Provisional Application No. 61/836,306, filed Jun. 18, 2013;
  • U.S. Provisional Application No. 61/836,895, filed Jun. 19, 2013;
  • U.S. Provisional Application No. 61/836,886, filed Jun. 19, 2013; and
  • U.S. Provisional Application No. 61/836,903, filed Jun. 19, 2013, the entire contents of each of which are hereby incorporated herein by reference.
  • This application also makes reference to:
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4880), titled “Clock Domain Crossing Serial Interface, Direct Latching, and Response Codes” and filed on even date herewith;
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4890), titled “Power and System Management Information Visibility” and filed on even date herewith;
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4900), titled “Power Mode Register Reduction and Power Rail Bring Up Enhancement” and filed on even date herewith;
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4910), titled “Dynamic Power Profiling” and filed on even date herewith;
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4920), titled “Charger Detection and Optimization Prior to Host Control” and filed on even date herewith; and
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4940), titled “Enhanced Recovery Mechanism” and filed on even date herewith.
  • BACKGROUND
  • Battery-powered computing systems and devices have been adopted for use in many aspects of daily life. As these systems and devices are more widely adopted and used in place of other computing systems and devices, they are designed to be more flexible and powerful, but are also more complex. With advances in the design of battery-powered computing devices, the availability of sufficient power for the devices continues to be an ongoing concern. For example, each new feature in a battery-powered computing device may require the provision of circuitry that supports a supply of power for the feature.
  • In the context of system power management, some battery-powered computing systems include power management processing circuitry that manages the supply of power in the system. Over time, this power management processing circuitry may need to adapt to certain needs in battery-operated systems.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, with emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
  • FIG. 1 illustrates a system for dynamic power mode switching according to an example embodiment.
  • FIG. 2 illustrates a process flow diagram for a process of dynamic power mode switching performed by the system of FIG. 1 according to an example embodiment.
  • FIG. 3 further illustrates the process flow diagram for the process of dynamic power mode switching performed by the system of FIG. 1 according to an example embodiment.
  • FIG. 4 illustrates a power profile maintained by the system of FIG. 1 and the process of FIGS. 2 and 3 for dynamic power mode switching according to an example embodiment.
  • FIG. 5 illustrates a display of a power profile for dynamic power mode switching according to an example embodiment.
  • DETAILED DESCRIPTION
  • In the context of system power management, some battery-powered computing systems include power management processing circuitry that manages the supply of power in the system. Over time, this power management processing circuitry may need to adapt to certain needs in battery-operated systems, such as the need for measurement and profiling of power consumed by various subsystems per power rail.
  • Additionally, the need for power management processing circuitry to identify, profile, and evaluate the consumption of per-rail power is now more important, especially as the number of power rails continues to grow and integrated semiconductor circuitry continues to shrink in size. For example, without the ability to identify the consumption of per-rail power, it might not be possible to identify whether a certain subsystem is operating outside its nominal or expected operating parameters. Further, as semiconductor circuitry continues to shrink in size, current leakage, which is variable in part based on temperature, has become a greater problem.
  • Although an amount of current leakage may be expected and semiconductor circuitry may be characterized to determine an expected amount of current leakage, it has become more difficult in new systems to rely upon an assumed or expected amount of current leakage. Similarly, it has become more difficult in new systems to rely upon an assumed or expected amount of current consumption for subsystems. When accurate power usage measurements and statistics are unavailable, poor overall power management may result.
  • In this context, aspects of dynamic power mode switching per rail based on power profiling are described. In one embodiment, an amount of current supplied by at least one of a plurality of power rails is sensed with a current sense circuit. The amount of current is profiled over a period of time and a profile of power consumed is generated and maintained. With reference to the power profile, one or more power-related decisions may be made in a system. One or more power rails may be powered off or placed into low power mode based on various factors, such as the amount of current being consumed per rail, the temperature of certain system components, or an unexpected ongoing consumption of power in the system.
  • Turning now to the drawings, an introduction and general description of exemplary embodiments of a system is provided, followed by a description of the operation of the same.
  • I. System Introduction
  • FIG. 1 illustrates a system 10 for dynamic power mode switching according to an example embodiment. The system 10 may embody a computing device that includes a number of general and/or specific purpose circuits, processing circuits, processors, registers, memories, sensors, displays, etc. In one embodiment, the system 10 may embody a handheld or portable computing device which is powered from charge stored in a battery. In various embodiments, the system 10 may be embodied as part of a cellular telephone, tablet computing device, laptop computer, or other computing device. Alternatively, because the embodiments described herein are not limited to use in handheld or portable computing devices, the system 10 may be embodied as part of a desktop or set top computing device, for example. Although not illustrated in FIG. 1, it should be appreciated that the system 10 may include one or more displays, microphones, speakers, buttons, indicator lights, haptic feedback elements, memory card readers, etc.
  • Among other elements, the system 10 includes a power management unit (PMU) 100, a host system-on-chip (SOC) 130, a system battery 182, and a system memory 184. The system 10 also includes certain subsystems such as a bluetooth / wireless local area network (WLAN) subsystem 170, a global positioning system (GPS) subsystem 171, a camera subsystem 172, and a sensor subsystem 173. The subsystems 170-173 are representative subsystems which may be included as elements of the system 10, and other subsystems are within the scope and spirit of the embodiments described herein. It is noted that, just as the host SOC 130 requires power for operation, each of the subsystems 170-173, the system memory 184, and other elements and circuits of the system 10 depend on power for operation. As discussed below, this power may be supplied by and under the control of the PMU 100.
  • The system battery 182 may be embodied as any rechargeable battery suitable for the application, such as a lithium-ion, nickel-metal-hydride, or other battery variant, without limitation. The system memory 184 may be embodied as a volatile and/or non-volatile random access memory or combination thereof. The system memory 184 may store computer-readable instructions thereon that, when executed by one or more of the processors 140-142 of the host SOC 130, for example, direct the processors 140-142 to execute various aspects of the embodiments described herein.
  • In general, the PMU 100 controls and/or facilitates control of the distribution of power from the system battery 182 to the elements of the system 10, such as the host SOC 130, the subsystems 170-173, and the system memory 184, for example. As further described below, depending upon the operating state of the system 10 and/or other factors, the PMU 100 may control the distribution of power to one or more elements of the system 10, or the PMU 100 may receive instructions to control the distribution of power to one or more elements of the system 10.
  • Among other elements, the PMU 100 includes a PMU controller 101, a serial interface slave 102, a PMU register bank 103, a current (/) sense circuit 107, a number 0-N of analog-to-digital (ADC) circuits 110-112, and a number of power rail circuits 120-124. It is noted that FIG. 1 illustrates a representative example of elements of the PMU 100, and it should be appreciated that the PMU 100 may include other elements in various embodiments. For example, the PMU 100 may include several additional power rails in addition to those illustrated in FIG. 1, to provide power to each element in the system 10, as needed.
  • In general, each of the power rails 120-124 includes a low dropout regulator (LDO) or switching type of power rail. An LDO power rail includes a linear voltage regulator that operates suitably even with a relatively low differential input vs. output voltage. A switching power rail includes an active switching circuit that charges and/or discharges reactive circuit elements to boost voltage or current, for example. It should be appreciated that an LDO or switching power rail is selected for each of the power rails 120-124 depending upon certain factors such as output voltage, input/output differential voltage, sourced current, power dissipation, cost, etc.
  • Among other elements, the host SOC 130 includes general and/or application specific processors. In FIG. 1, the host SOC 130 includes a power manager 131, an application processor 140, a modem 141, and a graphics processor 142. In various embodiments, the host SOC 130 may omit one or more of the processors 140-142 or include processors in addition to the processors 140-142. The host SOC 130 also includes a subsystem interface 162 and memory interface 163. The subsystem interface 162 and the memory interface 163 electrically and communicatively couple the subsystems 170-173 and the system memory 184 to the host SOC 130 and, particularly, to one or more of the processors 140-142.
  • The application processor 140 may be embodied as a general purpose processor for executing various applications. For example, the application processor 140 may execute an underlying operating system along with applications such as e-mail, short message service (SMS), telephone, camera, web-browser, and other applications, without limitation. As compared to the PMU 100 and/or the power manager 131, the application processor 140 may consume relatively more power during operation. The modem 141 may include a cellular-based (or similar) communications processor for the communication of data wirelessly in connection with radio-frequency front end circuitry, and the graphics processor 142 may include a processor for driving a display of the system 10.
  • The power manager 131 includes a power or system power control processor 132, a memory 133, and a serial interface master 134. The power processor 132 may be embodied as a relatively small and low power processor or processing circuit for interfacing with the PMU 100 via a serial interface 128. In one embodiment, the serial interface master 134 of the power manager 131 controls the serial interface 128, although the PMU 100 may control the serial interface 128 in other embodiments. The memory 133 stores computer-readable instructions for execution by the power processor 132.
  • II. System Operation
  • With reference to the elements of the system 10 introduced above, aspects of the operation of the system 10 are described below.
  • A. PMU Operation
  • The PMU 100 may be designed, adapted, and configured to perform operations that support the host SOC 130, the subsystems 170-173, the system memory 184, and other elements of the system 10. As one operational aspect of the PMU 100, the PMU 100 supplies power from the system battery 182 to other elements of the system 10 via the power rails 120-124. Further, when the system 10 is coupled to charging power via the system bus 180, the PMU 100 may charge the system battery 182. In certain aspects, the PMU 100 may monitor the voltage VBat of the system battery 182 and store a value of the voltage in the PMU register bank 103.
  • In other operational aspects of the PMU 100, the PMU controller 101 coordinates and controls the operations of the PMU 100. The PMU controller 101 may be embodied as a general or specific purpose circuit, processing circuit, processor, state machine, etc. The PMU controller 101 interfaces with the serial interface slave 102 to communicate with the host SOC 130 over the serial interface 128, interfaces with the power rail circuits 120-124 to control and sense power that is supplied to the system 10, and interfaces with the PMU register bank 103 to store and access data associated with the status of the PMU 100 and the system 10.
  • The serial interface slave 102 comprises one end of the serial interface 128 that facilitates communication between the PMU 100 and the host SOC 130. Among various modes and states of operation of the system 10, the serial interface 128 is relied upon to communicate data between the PMU 100 and the host SOC 130.
  • The current sense circuit 107 may be relied upon by the PMU 100 to determine an amount of current or power being supplied by at least one of a plurality of power rails 120-124. In certain embodiments, current sense circuit 107 may determine an amount of current being supplied by each of the power rails 120-124. Data on the amount of current supplied by one or more of the power rails 120-124 is relied upon as power profile data by the system 10. This power profile data may be gathered by the current sense circuit 107, as further described below, at the direction of the PMU controller 101 (and/or the power manager 131) and stored in the PMU register bank 103. The power profile data may also be communicated by the PMU 100 to the power manager 131 and/or the application processor 140 of host SOC 130 for further evaluation and processing.
  • The ADCs 110-112 may be relied upon to determine the voltage VBat of the system battery 182, the temperature of components in the system 10, etc. Particularly, the ADCs 110-112 may convert analog values of the VBat voltage, and voltages representative of the temperature of components in the system 10, into digital values for processing and/or storage by the PMU 100. These digital values include examples of power and management system status data that may be relied upon by the power manager 131 when determining whether to power on or power off certain power rails, as described below.
  • In one aspect, the current sense circuit 107 relies upon representative-scale replica power rail circuits to sense an amount of current being supplied by each of the power rails 120-124. By configuring the current sense circuit 107, the amount of current may be sensed from time to time or over a period of time as directed by the PMU controller 101 and/or the power manager 131. In general, the power profile data may be representative of operational aspects of the system 10.
  • B. Host SOC Operation
  • The host SOC 130 may be generally embodied as a full system-on-chip semiconductor device. In this sense, the host SOC 130 integrates various general and/or application specific processors and processing circuits into a single integrated circuit package, reducing space. Overall, the power manager 131 of the host SOC 130 supports the host SOC 130 and the power requirements of the host SOC 130.
  • In the context of power usage by the host SOC 130, it is noted that each of the power manager 131, the application processor 140, the modem 141, and the graphics processor 142 may be powered by a respective power rail of the PMU 100 in the system 10. For example, in the embodiment illustrated in FIG. 1, the power manager 131 may be powered by the power rail 1 120, and the application processor 140 may be powered by the power rail 2 121. Other elements and/or subsystems in the system 10 and within the host SOC may also be powered, respectively, by one or more power rails of the PMU 100. Each of the power rails 120-124 (and others) may be electrically coupled from the PMU 100 to the host SOC 130 and to other subsystems in the system 10 by respective power traces in the system 10 and power pins or pads of the PMU 100 and the host SOC 130.
  • According to aspects of the embodiments described herein, power manager or power manager circuit 131 of the host SOC 130 may request and retrieve power profile data stored by the PMU 100. The power manager circuit 131 may further evaluate the power profile data stored in the PMU 100, while coordinating power consumption by the host SOC 130 and/or the subsystems 170-173 in connection with control of the power rails 120-124 of the PMU 100.
  • The power manger 131 may retrieve and evaluate the data on the amount of current or power sourced by each of the power rails 120-124 over time. Additionally, the power manger 131 may retrieve and evaluate voltages output by each of the power rails 120-124 over time. Using the current and voltage data, the power manger 131 may calculate the amount of power sourced by each of the power rails 120-124.
  • In this context, the power manager 131 may evaluate the amount of current, voltage, or power sourced by one or more of the power rails 120-124 over a period of time and maintain a power profile of power consumed by one or more system elements in the system. In connection with other system status data from the PMU 100, the power manger 131 may also identify one or more system elements as a source of heat in the system 10 based on the power profile. In response, the power manger 131 may change an output voltage of or power down a power rail associated with the system element which is the source of heat.
  • In another aspect, the power manager 131 may identify an unexpected ongoing processing status or state of a processor or other system element in the system 10 based on an amount of current identified in the power profile over a certain period of time. In certain cases, the identification of the unexpected ongoing processing status or state may be helpful to diagnose a system problem or troubleshoot hardware or software problems. Additionally, as further described below, the power manager 131 may also set the operating mode of one or more power rails over time based on whether an amount of current or power sourced by the one or more power rails is less than or approaches a threshold of current.
  • In connection with the evaluation and review of power profile data, the power manager 131 may operate with the PMU 100 to power up and power down power rails in the system 10 in one or more groups or individually, as needed, over time. It is noted that, in certain embodiments, the host SOC 130 (including the power manager 131) and the PMU 100 may be combined in an integrated circuit. In this case, the serial interface 128 may be omitted and/or the power manager 131 and the PMU controller 101 may be combined.
  • Turning to FIGS. 2 and 3, process flow diagrams illustrating example processes performed by the system 10 for dynamic power mode switching per rail are illustrated. While the process flow diagrams are generally described as being performed by the PMU 100 and/or the power management processor 131 in the system 10 of FIG. 1, it is noted that other systems may perform the illustrated processes. That is, in various embodiments, systems similar to the system 10 may perform the processes illustrated in FIGS. 2 and 3.
  • In certain aspects, the flowcharts of FIGS. 2 and 3 may be considered to depict example steps performed by the system 10 according to one or more embodiments. Although the process diagrams of FIGS. 2 and 3 illustrate an order, it should be understood that the order may differ from that which is depicted. For example, an order of two or more elements in the process may be scrambled relative to that shown, performed concurrently, or performed with partial concurrence. Further, in some embodiments, one or more of the elements may be skipped or omitted within the scope and spirit of the embodiments described herein.
  • FIG. 2 illustrates a process flow diagram for a process 200 of dynamic power mode switching performed by the system 10 of FIG. 1 according to an example embodiment. Starting at reference numeral 202, the process 200 includes sensing an amount of current or power supplied by at least one of a plurality of power rails. For example, the current sense circuit 107 in the PMU 100 (FIG. 1) may sense the amount of current supplied by one of more of the power rails 120-124 from time to time or periodically over time. In one embodiment, the current sense circuit 107 may sense the amount of current supplied by each of the power rails 120-124 from time to time or periodically over time. The sensed current values are converted to digital values and stored by the PMU 100 in the PMU register bank 103. Thus, the amount of current sourced by the power rails 120-124 (and any others) is available as power profile data, for retrieval, reference, and evaluation by the PMU controller 101 and/or the power manager 131.
  • Continuing to reference numeral 204, the process 200 includes profiling and/or evaluating the amount of power or current supplied by the power rails 120-124 over a period of time. It is noted that the period of time for the evaluation may vary among embodiments. For example, the period of time may range from substantially no time (e.g., instantaneous) to microseconds, milliseconds, seconds, minutes, hours, etc., without limitation. In certain aspects, the profiling may include retrieving power profile data stored in the PMU register bank 103 from time to time as it is updated by the PMU 100. The power profile data retrieved from the PMU register bank 103 may include an amount of current supplied over time by each of the power rails 120-124, a voltage output over time by each of the power rails 120-124, system temperature data taken over time, and other system parameters such as the voltage VBat of the system battery 182. The profiling at reference numeral 204 may also include aggregating and organizing the retrieved data. In one embodiment, the data may be aggregated and organized by the power processor and stored, at least in part, in the memory 133 of the power manager 131.
  • At reference numeral 206, the process 200 includes generating and/or maintaining a power profile of power consumed by one or more of a plurality of system elements in the system 10 based on the profiling performed at reference numeral 204. As further described below, the power profile may be maintained for one or more system elements in the system 10, in association with one or more corresponding ones of the power rails 120-124 that supply power to the system elements.
  • With reference to FIG. 4, further details on a maintaining a power profile are described. FIG. 4 illustrates a power profile 410 maintained by the system 10 of FIG. 1 according to an example embodiment. FIG. 4 generally illustrates current sourced or power consumed in the system 10 with reference to example power rails 1-8, individually, and is representative of power consumed by elements or subsystems of the system 10. Power consumed or current sourced by the power rails 120-124 in the system 10 may be represented among the data plotted for one or more of the power rails 1-8 in FIG. 4. The y-axis in FIG. 4 may be representative of current, volts, or power, for example, in mA, mV, or mW, for example, and the x-axis in FIG. 4 may be representative of time.
  • Referring back to FIG. 2, at reference numeral 208, the process 200 includes reviewing the power profile generated and/or maintained at reference numeral 206. In various aspects, the reviewing at reference numeral 208 includes comparing power sourced by one or more power rails to one or more thresholds, identifying correlations between power consumption and heat, and/or identifying unexpected ongoing processes, for example, among other processes. That is, at reference numeral 208, a further review and analysis of the power profile is performed. Further details regarding reviewing the power profile at reference numeral 208 are described below with reference to FIG. 3.
  • At reference numeral 210, the process 200 includes dynamically switching one or more power rails based on the review of the power profile at reference numeral 208. For example, the power manager 131 may set one or more of the power rails 120-124 into low power mode at reference numeral 210, as necessary. Additionally or alternatively, the power manger 131 may power off or power on one or more of the power rails 120-124, etc. In this context, it is noted that the operating parameters for any one of the power rails 120-124 (and any others) may be set, modified, and updated individually, based on the review performed at reference numeral 208. In other scenarios, operating settings for an entire group of the power rails 120-124 may be quickly modified to low power mode, normal mode, etc., by one command to the PMU 100. Thus, the dynamic switching at reference numeral 210 may be performed in a manner which is flexible, with reference to power data for each individual power rail in the system 10. It is noted that the process 200 may return to reference numeral 202 as an iterative process of dynamic power mode switching.
  • In other aspects, at reference numeral 212, the process 200 may include displaying a power profile as an amount of power consumed by one or more system elements of the system 10 over time. In this context, FIG. 5 illustrates display 500 that may be displayed as representative of amount of power consumed by one or more system elements of the system 10 over time. The display 500 may be rendered on a physical display of the system 10, at the request of a user. In FIG. 5, the x-axis may be representative of mA or mW hours or minutes, for example. FIG. 5 generally illustrates power consumed in the system 10 with reference to example power rails 1-8, individually. In practice, the each of the power rails on the display 500 may be identified by system element or subsystem. As opposed to other displays of power information that may be estimated by battery-powered systems, the display 500 may be generated by the system 10 based on actual data sensed by the current sense circuit 107 for current sourced by individual power rails. The display 500 may also be generated using a combination of current and voltage data for respective power rails over time. Thus, the display 500 may provide an accurate real-time display of power usage in battery-powered systems.
  • Turning to FIG. 3, further aspects of reviewing, as performed at reference numeral 208 of the process 200 of FIG. 2, are described. At reference numeral 302, reviewing at reference numeral 208 may include identifying a system element as a source of heat in the system 10. For example, referring to FIG. 4, the power manager 131 may correlate the relatively increased power consumption 402 for the power rail 5 as being associated with an increase in temperature 403 (dashed line) measured by the PMU 100, based on the overlapped or coincident timing of the increased temperature 403 with the increased power consumption 402. By system design, because the power manager 131 and/or the PMU 100 identifies the power rail 5 as being associated with a certain element or subsystem of the system 10, the power manager 131 and/or the PMU 100 may correlate the element or subsystem associated with the power rail 5 (e.g., the BT/WLAN subsystem 170, etc.) as being the cause of the increase in temperature. In this manner, the cause or root of increased temperatures in the system 10 may be more accurately identified. Further, if necessary, the power rail 5 may be powered off, set to an alternative voltage, etc., by the power manager 131 to prevent damage to the system 10, for example.
  • Referencing FIG. 3 again, at reference numeral 304, the reviewing at reference numeral 208 includes identifying an unexpected ongoing processing status or state of an element in the system 10 based on the amount of current. Referring again to FIG. 4, the increased and ongoing power consumptions 404 and 406 may be identified at reference numeral 208 by the power manager 131 as unexpected states of power consumption under certain circumstances. For troubleshooting software and/or hardware, for example, abnormal or unexpected power consumption, such as the power consumptions 404 and 406, may be identified and addressed by the power manager 131. The system or subsystem element associated with the power consumption 404 and the power rail 6, for example, may be reset or powered down, as necessary, to address the problem as illustrated in FIG. 4.
  • At reference numeral 306 of FIG. 3, the reviewing at reference numeral 208 includes comparing an amount of current or power to a threshold. In FIG. 4, for example, the amount of current sourced by the power rail 1 is compared to a current threshold. As one example, the current sourced by the power rail 1 may be compared to a 20 mA threshold by the power manager 131, although use of any current or power threshold values suitable for the application are within the scope and spirit of the embodiments described herein. In turn, when the amount of current sourced by the power rail 1 is less than the 20 mA threshold (e.g., at reference 408 in FIG. 4), the settings of the power rail 1 may be dynamically switched to place the power rail 1 into a low power mode of operation at reference numeral 210 of FIG. 2. Here, it is noted that switching the power rail 1 into the low power mode of operation may help conserve power for the system 10. Particularly, because the power rail 1 is sourcing such a low amount of current, at least part of the circuitry that supports the power rail 1 may be turned off until more current is demanded.
  • In other systems, certain power rails are placed into low power mode depending upon the state of the system, without actual knowledge of measured current consumption. According to aspects of the embodiments described herein, however, power rails may be set into low power mode whenever they are not needed for high current sourcing, based on the power profile 410 maintained by the power manager 131.
  • As another example of comparing current or power to a threshold at reference numeral 306, when the amount of current sourced by the power rail 1 approaches the 20 mA threshold (e.g., at reference 409 in FIG. 4), the settings of the power rail 1 may be dynamically switched at reference numeral 210 of FIG. 2, to place the power rail 1 bank into a normal mode of operation. Thus, the power rail 1 may be dynamically switched between low power and normal modes of operation based on actual power demands in the system 10. In certain aspects, the power rail 1 may be dynamically switched back to a normal power mode of operation by the power manager 131 at some time before the power rail 1 is expected to need to source more than 20 mA of current, for example, or as it “approaches” the 20 mA threshold.
  • Other manners and/or means of review of the power profile at reference numeral 208 are within the scope and spirit of the embodiments described herein. Generally, by relying upon the concepts for dynamic power mode switching per rail described above, power rails may be set to appropriate operating parameters based on actual real time power consumption rather than on semiconductor characterizations of expected consumption and processing state assumptions. Using accurate power measurements and statistics, the overall power management in battery-powered systems may be improved.
  • With regard to aspects of the structure or architecture of the system 10, in various embodiments, each of the PMU controller 101, the power processor 132, and or other processors or processing circuits of the system 10 may comprise general purpose arithmetic processors, state machines, or Application Specific Integrated Circuits (“ASICs”), for example. Each such processor or processing circuit may be configured to execute one or more computer-readable software instruction modules. In certain embodiments, each processor or processing circuit may comprise a state machine or ASIC, and the processes described in FIGS. 5 and 6 may be implemented or executed by the state machine or ASIC according to the computer-readable instructions.
  • The memories and/or registers described herein may comprise any suitable memory devices that store computer-readable instructions to be executed by processors or processing circuits. These memories and/or registers store computer-readable instructions thereon that, when executed by the processors or processing circuits, direct the processors or processing circuits to execute various aspects of the embodiments described herein.
  • As a non-limiting example group, the memories and/or registers may include one or more of an optical disc, a magnetic disc, a semiconductor memory (i.e., a semiconductor, floating gate, or similar flash based memory), a magnetic tape memory, a removable memory, combinations thereof, or any other known memory means for storing computer-readable instructions.
  • In certain aspects, the processors or processing circuits are configured to retrieve computer-readable instructions and/or data stored on the memories and/or registers for execution. The processors or processing circuits are further configured to execute the computer-readable instructions to implement various aspects and features of the embodiments described herein.
  • Although embodiments have been described herein in detail, the descriptions are by way of example. The features of the embodiments described herein are representative and, in alternative embodiments, certain features and elements may be added or omitted. Additionally, modifications to aspects of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the present invention defined in the following claims, the scope of which are to be accorded the broadest interpretation so as to encompass modifications and equivalent structures.

Claims (20)

1. A method, comprising:
sensing, with a current sense circuit in a system, an amount of current supplied by at least one of a plurality of power rails;
profiling the amount of current over a period of time; and
based on the profiling, maintaining a power profile of power consumed by at least one of a plurality of system elements in the system.
2. The method according to claim 1, further comprising:
based on the power profile, identifying a system element as a source of heat in the system; and
changing an output voltage of or powering down a power rail associated with the system element.
3. The method according to claim 1, further comprising identifying an unexpected ongoing processing status or state of an element in the system based on the amount of current.
4. The method according to claim 1, further comprising:
comparing the amount of current to a threshold; and
when the amount of current is less than the threshold, setting at least one of the plurality of power rails into a low power mode of operation.
5. The method according to claim 1, further comprising:
comparing the amount of current to a threshold; and
when the amount of current approaches the threshold, setting at least one of the plurality of power rails into a normal power mode of operation.
6. The method according to claim 1, wherein:
sensing the amount of current comprises sensing an amount of current supplied by each of the plurality of power rails; and
profiling the amount of current comprises profiling the amount of current supplied by each of the plurality of power rails over the period of time.
7. The method according to claim 6, further comprising, based on the profiling, maintaining a power profile for the plurality of system elements in the system
8. The method according to claim 6, further comprising displaying the power profile as an amount of power consumed by the plurality of system elements over time.
9. The method according to claim 1, wherein maintaining the power profile comprises maintaining the power profile based on the amount of current and a voltage of at least one of the plurality of system elements in the system.
10. A system, comprising:
a current sense circuit that senses an amount of current supplied by at least one of a plurality of power rails; and
a power manager circuit that:
evaluates the amount of current over a period of time; and
maintains a power profile of power consumed by at least one of a plurality of system elements in the system.
11. The system according to claim 10, wherein the power manager circuit further:
identifies a system element as a source of heat in the system based on the power profile; and
changes an output voltage of or powers down a power rail associated with the system element.
12. The system according to claim 10, wherein the power manager circuit further identifies an unexpected ongoing processing status or state of an element in the system based on the amount of current.
13. The system according to claim 10, wherein the power manager circuit further:
compares the amount of current to a threshold; and
sets at least one of the plurality of power rails into a low power mode of operation when the amount of current is less than the threshold.
14. The system according to claim 10, wherein the power manager circuit further:
compares the amount of current to a threshold; and
sets at least one of the plurality of power rails into a normal power mode of operation when the amount of current approaches the threshold.
15. The system according to claim 10, wherein:
the current sense circuit senses an amount of current supplied by each of the plurality of power rails; and
the power manager circuit profiles the amount of current supplied by each of the plurality of power rails over the period of time.
16. A method, comprising:
sensing, with a current sense circuit in a system, an amount of power supplied by a plurality of power rails;
profiling the amount of power; and
based on the profiling, maintaining a power profile of power consumed by a plurality of system elements in the system.
17. The method according to claim 16, further comprising:
based on the power profile, identifying a system element as a source of heat in the system; and
changing an output voltage of or powering down a power rail associated with the system element.
18. The method according to claim 16, further comprising identifying an unexpected ongoing processing status or state of an element in the system based on the amount of power.
19. The method according to claim 16, further comprising:
comparing the amount of power to a threshold;
when the amount of power is less than the threshold, setting at least one of the plurality of power rails into a low power mode of operation; and
when the amount of power approaches the threshold, setting at least one of the plurality of power rails into a normal power mode of operation.
20. The method according to claim 16, wherein
sensing the amount of power comprises sensing an amount of current supplied by each of the plurality of power rails; and
profiling the amount of power comprises profiling the amount of current supplied by each of the plurality of power rails over the period of time.
US13/950,776 2013-02-01 2013-07-25 Dynamic power mode switching per rail Abandoned US20140223214A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/950,776 US20140223214A1 (en) 2013-02-01 2013-07-25 Dynamic power mode switching per rail

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201361759470P 2013-02-01 2013-02-01
US201361833598P 2013-06-11 2013-06-11
US201361834513P 2013-06-13 2013-06-13
US201361836306P 2013-06-18 2013-06-18
US201361836327P 2013-06-18 2013-06-18
US201361836886P 2013-06-19 2013-06-19
US201361836895P 2013-06-19 2013-06-19
US201361836903P 2013-06-19 2013-06-19
US13/950,776 US20140223214A1 (en) 2013-02-01 2013-07-25 Dynamic power mode switching per rail

Publications (1)

Publication Number Publication Date
US20140223214A1 true US20140223214A1 (en) 2014-08-07

Family

ID=51258735

Family Applications (8)

Application Number Title Priority Date Filing Date
US13/950,762 Active 2034-07-11 US9424127B2 (en) 2013-02-01 2013-07-25 Charger detection and optimization prior to host control
US13/950,750 Active 2033-12-06 US9342400B2 (en) 2013-02-01 2013-07-25 Dynamic power profiling
US13/950,738 Active 2034-07-19 US9430323B2 (en) 2013-02-01 2013-07-25 Power mode register reduction and power rail bring up enhancement
US13/950,713 Active US8996736B2 (en) 2013-02-01 2013-07-25 Clock domain crossing serial interface, direct latching, and response codes
US13/950,725 Abandoned US20140223217A1 (en) 2013-02-01 2013-07-25 Power and system management information visibility
US13/950,776 Abandoned US20140223214A1 (en) 2013-02-01 2013-07-25 Dynamic power mode switching per rail
US13/950,769 Active 2034-11-28 US9542267B2 (en) 2013-02-01 2013-07-25 Enhanced recovery mechanisms
US14/631,709 Active US9448878B2 (en) 2013-02-01 2015-02-25 Clock domain crossing serial interface

Family Applications Before (5)

Application Number Title Priority Date Filing Date
US13/950,762 Active 2034-07-11 US9424127B2 (en) 2013-02-01 2013-07-25 Charger detection and optimization prior to host control
US13/950,750 Active 2033-12-06 US9342400B2 (en) 2013-02-01 2013-07-25 Dynamic power profiling
US13/950,738 Active 2034-07-19 US9430323B2 (en) 2013-02-01 2013-07-25 Power mode register reduction and power rail bring up enhancement
US13/950,713 Active US8996736B2 (en) 2013-02-01 2013-07-25 Clock domain crossing serial interface, direct latching, and response codes
US13/950,725 Abandoned US20140223217A1 (en) 2013-02-01 2013-07-25 Power and system management information visibility

Family Applications After (2)

Application Number Title Priority Date Filing Date
US13/950,769 Active 2034-11-28 US9542267B2 (en) 2013-02-01 2013-07-25 Enhanced recovery mechanisms
US14/631,709 Active US9448878B2 (en) 2013-02-01 2015-02-25 Clock domain crossing serial interface

Country Status (1)

Country Link
US (8) US9424127B2 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150370681A1 (en) * 2014-06-23 2015-12-24 Dell Products L.P. Power profile diagnostic system
US20160026227A1 (en) * 2014-07-22 2016-01-28 Empire Technology Development Llc Dynamic router power control in multi-core processors
EP3141984A1 (en) * 2015-09-09 2017-03-15 Samsung Electronics Co., Ltd. Electronic device for managing power and method of controlling same
WO2017172987A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Power consumption measurement for system-on-chip devices
US10877536B2 (en) * 2018-10-30 2020-12-29 Dell Products, L.P. Apparatus and method for providing smooth power-on operation with power assist unit
US10948959B2 (en) 2018-10-31 2021-03-16 Dell Products, L.P. Method and apparatus to control power assist unit
US10951051B2 (en) 2018-10-30 2021-03-16 Dell Products, L.P. Method and apparatus to charge power assist unit
US10990149B2 (en) 2018-10-31 2021-04-27 Dell Products L.P. Method and apparatus for providing peak optimized power supply unit
US11126250B2 (en) 2018-10-30 2021-09-21 Dell Products L.P. Method and apparatus for extending power hold-up with power assist unit
US11144105B2 (en) 2018-10-30 2021-10-12 Dell Products L.P. Method and apparatus to provide platform power peak limiting based on charge of power assist unit
US11199894B2 (en) 2018-10-30 2021-12-14 Dell Products L.P. Method and apparatus for providing high bandwidth capacitor circuit in power assist unit
US11599182B2 (en) 2018-10-31 2023-03-07 Dell Products L.P. Method and apparatus to distribute current indicator to multiple end-points
US11662803B2 (en) * 2020-07-31 2023-05-30 Lenovo (Beijing) Limited Control method, apparatus, and electronic device

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160048965A (en) * 2013-09-04 2016-05-04 첸트룸 미크로엘렉트로닉 드레스덴 악치엔게젤샤프트 Fpga power management system
US10079019B2 (en) 2013-11-12 2018-09-18 Apple Inc. Always-on audio control for mobile device
JP6285779B2 (en) * 2014-03-31 2018-02-28 ローム株式会社 Power management controller, power management circuit using the same, and electronic equipment
US10031000B2 (en) 2014-05-29 2018-07-24 Apple Inc. System on a chip with always-on processor
US9778728B2 (en) 2014-05-29 2017-10-03 Apple Inc. System on a chip with fast wake from sleep
US9619377B2 (en) 2014-05-29 2017-04-11 Apple Inc. System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode
JP6341795B2 (en) * 2014-08-05 2018-06-13 ルネサスエレクトロニクス株式会社 Microcomputer and microcomputer system
US9479331B2 (en) * 2014-08-20 2016-10-25 Apple Inc. Managing security in a system on a chip (SOC) that powers down a secure processor
US9682634B2 (en) * 2014-08-27 2017-06-20 Hyundai Motor Company Method and system for detecting charger
US9419624B2 (en) * 2014-11-12 2016-08-16 Xilinx, Inc. Power management system for integrated circuits
US9413354B2 (en) * 2014-12-23 2016-08-09 Apple Inc. Method for communication across voltage domains
US10324113B2 (en) 2015-11-17 2019-06-18 Cirrus Logic, Inc. Current sense amplifier with enhanced common mode input range
GB2544835B (en) * 2015-11-17 2020-02-12 Cirrus Logic Int Semiconductor Ltd Current sense amplifier with common mode rejection
CN105573932B (en) * 2015-12-11 2018-04-20 中国航空工业集团公司西安航空计算技术研究所 A kind of more bit wide data cross clock domain access methods based on register
US10073511B2 (en) * 2016-03-31 2018-09-11 Qualcomm Incorporated Apparatus and methods for embedded current measurements for performance throttling
CN105896679B (en) * 2016-05-31 2019-04-19 合肥联宝信息技术有限公司 A kind of charge control method and the electronic equipment using this method
CN106329631B (en) * 2016-08-31 2019-06-11 宇龙计算机通信科技(深圳)有限公司 A kind of charging method and device
CN106300533B (en) * 2016-08-31 2019-06-11 宇龙计算机通信科技(深圳)有限公司 A kind of charging method and device
CN106329628B (en) * 2016-08-31 2019-06-11 宇龙计算机通信科技(深圳)有限公司 A kind of charging method and device
CN106329629B (en) * 2016-08-31 2019-06-11 宇龙计算机通信科技(深圳)有限公司 A kind of charging method and device
CN106230070B (en) * 2016-08-31 2020-01-10 宇龙计算机通信科技(深圳)有限公司 Charging method and device
CN106329630B (en) * 2016-08-31 2019-06-11 宇龙计算机通信科技(深圳)有限公司 A kind of charging method and device
CN106706997A (en) * 2016-11-15 2017-05-24 捷开通讯(深圳)有限公司 Current dynamic detection method and device
CN107104478B (en) * 2017-03-29 2020-05-26 联想(北京)有限公司 Information processing method and electronic equipment
US10474174B2 (en) * 2017-04-04 2019-11-12 Intel Corporation Programmable supply generator
CN107146009B (en) * 2017-04-27 2020-09-04 杭州电子科技大学 Water supply pipe network operation state evaluation method
US11194684B2 (en) * 2019-01-17 2021-12-07 Dell Products L.P. Information handling system and methods to detect power rail failures and test other components of a system motherboard
US20230185351A1 (en) * 2021-12-09 2023-06-15 Rambus Inc. Power management integrated circuit device having multiple initialization/power up modes

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339445A (en) * 1992-11-16 1994-08-16 Harris Corporation Method of autonomously reducing power consumption in a computer sytem by compiling a history of power consumption
US20050240786A1 (en) * 2004-04-23 2005-10-27 Parthasarathy Ranganathan Selecting input/output devices to control power consumption of a computer system
US20080238216A1 (en) * 2007-03-30 2008-10-02 Kurt Heidmann Power floor method and assembly
US20100321883A1 (en) * 2008-02-12 2010-12-23 Tracy Mark S Computing devices having fail-safe mechanical shut-off switch
US20110071695A1 (en) * 2009-09-15 2011-03-24 Denis Kouroussis Smart-grid adaptive power management method and system with power factor optimization and total harmonic distortion reduction
US20120130657A1 (en) * 2010-11-19 2012-05-24 International Business Machines Corporation Measuring power consumption in an integrated circuit
US20130227261A1 (en) * 2012-02-24 2013-08-29 Qualcomm Incorporated System and Method For Thermally Aware Device Booting
US20130265088A1 (en) * 2012-04-04 2013-10-10 Honeywell International Inc. Overcurrent based power control and circuit reset
US20140075232A1 (en) * 2012-09-10 2014-03-13 Texas Instruments Incorporated Nonvolatile Logic Array Based Computing Over Inconsistent Power Supply
US20140096102A1 (en) * 2012-09-28 2014-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for across-chip thermal and power management in stacked ic designs

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218607A (en) * 1989-06-23 1993-06-08 Kabushiki Kaisha Toshiba Computer having a resume function and operable on an internal power source
US5307488A (en) * 1991-03-15 1994-04-26 Nippon Steel Corporation System interruption apparatus
US5936520A (en) * 1997-11-13 1999-08-10 Chrysler Corporation Analog sensor status detection single wire bus multiplex system
FR2782430B1 (en) * 1998-08-13 2004-05-28 Bull Sa INTERCONNECTION METHOD AND INTERFACE IMPLEMENTING HIGH-SPEED LINKS
US6301133B1 (en) * 1999-04-07 2001-10-09 Astec International Limited Power supply system with ORing element and control circuit
US6725388B1 (en) * 2000-06-13 2004-04-20 Intel Corporation Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains
US7274705B2 (en) * 2000-10-03 2007-09-25 Broadcom Corporation Method and apparatus for reducing clock speed and power consumption
US6883102B2 (en) * 2001-12-18 2005-04-19 Arm Limited Apparatus and method for performing power management functions
US7107393B1 (en) * 2003-03-28 2006-09-12 Xilinx, Inc. Systems and method for transferring data asynchronously between clock domains
US7263027B2 (en) * 2004-10-14 2007-08-28 Broadcom Corporation Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features
US7480282B2 (en) * 2005-03-17 2009-01-20 Agere Systems Inc. Methods and apparatus for controlling ethernet packet transfers between clock domains
JP4428272B2 (en) * 2005-03-28 2010-03-10 セイコーエプソン株式会社 Display driver and electronic device
US7500044B2 (en) * 2005-07-07 2009-03-03 P.A. Semi, Inc. Digital phase relationship lock loop
US8213141B2 (en) * 2006-01-17 2012-07-03 Broadcom Corporation Power over Ethernet electrostatic discharge protection circuit
WO2008022404A1 (en) * 2006-08-25 2008-02-28 Cochlear Limited Current leakage detection method and device
WO2008129364A1 (en) * 2007-04-23 2008-10-30 Nokia Corporation Transferring data between asynchronous clock domains
US20080272741A1 (en) * 2007-05-03 2008-11-06 Summit Microelectronics, Inc. Systems and methods for detecting power sources
US7984284B2 (en) * 2007-11-27 2011-07-19 Spansion Llc SPI auto-boot mode
US20090204835A1 (en) * 2008-02-11 2009-08-13 Nvidia Corporation Use methods for power optimization using an integrated circuit having power domains and partitions
JP2009301941A (en) * 2008-06-16 2009-12-24 Nec Tokin Corp Secondary battery pack
US20090315399A1 (en) * 2008-06-20 2009-12-24 Fujitsu Microelectronics Limited Semiconductor device
US8823209B2 (en) * 2008-06-20 2014-09-02 Fujitsu Semiconductor Limited Control of semiconductor devices to selectively supply power to power domains in a hierarchical structure
GB2472051B (en) * 2009-07-22 2012-10-10 Wolfson Microelectronics Plc Power management apparatus and methods
GB2472050B (en) * 2009-07-22 2013-06-19 Wolfson Microelectronics Plc Power management apparatus and methods
US8375236B2 (en) * 2009-08-04 2013-02-12 Red Hat, Inc. Methods for determining battery statistics using a system-wide daemon
US9300015B2 (en) * 2010-05-04 2016-03-29 Dell Products Lp Systems and methods for monitoring and characterizing information handling system use behavior
JP5703605B2 (en) * 2010-06-28 2015-04-22 富士通セミコンダクター株式会社 Semiconductor integrated circuit
US20120117364A1 (en) * 2010-11-04 2012-05-10 Russell Melvin Rosenquist Method and System for Operating a Handheld Calculator
JP5527895B2 (en) * 2010-11-18 2014-06-25 パナソニック株式会社 Secondary battery control device and control method
US8898502B2 (en) * 2011-07-05 2014-11-25 Psion Inc. Clock domain crossing interface
US9148026B2 (en) * 2011-09-30 2015-09-29 Fairchild Semiconductor Corporation Charger detection with proprietary charger support
US8278997B1 (en) * 2011-10-03 2012-10-02 Google Inc. Apparatus and methodology for controlling hot swap MOSFETs
US20130120010A1 (en) * 2011-11-10 2013-05-16 Qualcomm Incorporated Power Measurement System for Battery Powered Microelectronic Chipsets
US9471121B2 (en) * 2011-11-14 2016-10-18 Texas Instruments Incorporated Microprocessor based power management system architecture
US20130155081A1 (en) * 2011-12-15 2013-06-20 Ati Technologies Ulc Power management in multiple processor system
US20130231894A1 (en) * 2012-03-01 2013-09-05 Nokia Corporation Method and apparatus for providing battery information
US9026842B2 (en) * 2012-03-20 2015-05-05 Blackberry Limited Selective fault recovery of subsystems
US9048661B2 (en) * 2012-06-27 2015-06-02 Apple Inc. Battery protection circuits
US9411398B2 (en) * 2012-09-28 2016-08-09 Intel Corporation Electronic device and method to extend battery life

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339445A (en) * 1992-11-16 1994-08-16 Harris Corporation Method of autonomously reducing power consumption in a computer sytem by compiling a history of power consumption
US20050240786A1 (en) * 2004-04-23 2005-10-27 Parthasarathy Ranganathan Selecting input/output devices to control power consumption of a computer system
US20080238216A1 (en) * 2007-03-30 2008-10-02 Kurt Heidmann Power floor method and assembly
US20100321883A1 (en) * 2008-02-12 2010-12-23 Tracy Mark S Computing devices having fail-safe mechanical shut-off switch
US20110071695A1 (en) * 2009-09-15 2011-03-24 Denis Kouroussis Smart-grid adaptive power management method and system with power factor optimization and total harmonic distortion reduction
US20120130657A1 (en) * 2010-11-19 2012-05-24 International Business Machines Corporation Measuring power consumption in an integrated circuit
US20130227261A1 (en) * 2012-02-24 2013-08-29 Qualcomm Incorporated System and Method For Thermally Aware Device Booting
US20130265088A1 (en) * 2012-04-04 2013-10-10 Honeywell International Inc. Overcurrent based power control and circuit reset
US20140075232A1 (en) * 2012-09-10 2014-03-13 Texas Instruments Incorporated Nonvolatile Logic Array Based Computing Over Inconsistent Power Supply
US20140096102A1 (en) * 2012-09-28 2014-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for across-chip thermal and power management in stacked ic designs

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150370681A1 (en) * 2014-06-23 2015-12-24 Dell Products L.P. Power profile diagnostic system
US9514020B2 (en) * 2014-06-23 2016-12-06 Dell Products L.P. Power profile diagnostic system
US20160026227A1 (en) * 2014-07-22 2016-01-28 Empire Technology Development Llc Dynamic router power control in multi-core processors
US9678550B2 (en) * 2014-07-22 2017-06-13 Empire Technology Development Llc Dynamic router power control in multi-core processors
EP3141984A1 (en) * 2015-09-09 2017-03-15 Samsung Electronics Co., Ltd. Electronic device for managing power and method of controlling same
KR20170030338A (en) * 2015-09-09 2017-03-17 삼성전자주식회사 Electronic device for managing power and method for controlling thereof
CN107085462A (en) * 2015-09-09 2017-08-22 三星电子株式会社 For managing the electronic equipment of electric power and controlling its method
US10545555B2 (en) 2015-09-09 2020-01-28 Samsung Electronics Co., Ltd Electronic device for managing power and method of controlling same
US11733756B2 (en) 2015-09-09 2023-08-22 Samsung Electronics Co., Ltd Electronic device for managing power and method of controlling same
KR102523859B1 (en) * 2015-09-09 2023-04-21 삼성전자주식회사 Electronic device for managing power and method for controlling thereof
WO2017172987A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Power consumption measurement for system-on-chip devices
US11199894B2 (en) 2018-10-30 2021-12-14 Dell Products L.P. Method and apparatus for providing high bandwidth capacitor circuit in power assist unit
US11126250B2 (en) 2018-10-30 2021-09-21 Dell Products L.P. Method and apparatus for extending power hold-up with power assist unit
US11144105B2 (en) 2018-10-30 2021-10-12 Dell Products L.P. Method and apparatus to provide platform power peak limiting based on charge of power assist unit
US10951051B2 (en) 2018-10-30 2021-03-16 Dell Products, L.P. Method and apparatus to charge power assist unit
US10877536B2 (en) * 2018-10-30 2020-12-29 Dell Products, L.P. Apparatus and method for providing smooth power-on operation with power assist unit
US10990149B2 (en) 2018-10-31 2021-04-27 Dell Products L.P. Method and apparatus for providing peak optimized power supply unit
US11599182B2 (en) 2018-10-31 2023-03-07 Dell Products L.P. Method and apparatus to distribute current indicator to multiple end-points
US10948959B2 (en) 2018-10-31 2021-03-16 Dell Products, L.P. Method and apparatus to control power assist unit
US11662803B2 (en) * 2020-07-31 2023-05-30 Lenovo (Beijing) Limited Control method, apparatus, and electronic device

Also Published As

Publication number Publication date
US20140218078A1 (en) 2014-08-07
US20140223031A1 (en) 2014-08-07
US9448878B2 (en) 2016-09-20
US20140223217A1 (en) 2014-08-07
US20140218011A1 (en) 2014-08-07
US20140223153A1 (en) 2014-08-07
US20140223200A1 (en) 2014-08-07
US20150186209A1 (en) 2015-07-02
US9430323B2 (en) 2016-08-30
US9424127B2 (en) 2016-08-23
US9342400B2 (en) 2016-05-17
US9542267B2 (en) 2017-01-10
US8996736B2 (en) 2015-03-31

Similar Documents

Publication Publication Date Title
US20140223214A1 (en) Dynamic power mode switching per rail
US8248031B2 (en) Method for prioritizing load consumption within a notebook computer
US9134380B2 (en) Battery detection and user experience
US7987376B2 (en) Power supply controller configured to supply power to external device and modules of computer system according to the selected power supply mode
US11422601B2 (en) Methods and systems for advanced battery charge capacity forecasting
US11314311B2 (en) Battery runtime and performance management based upon presence detection
JP2011259625A (en) Information processing apparatus and power supply control method
KR20150068443A (en) Mixed cell type battery module and uses thereof
US11520498B2 (en) Memory management to improve power performance
KR20150085642A (en) Power supply, electronic apparatus including the same and method for power supplying
US20130049704A1 (en) Charging apparatus and charging method
CN101598770A (en) Testing method of computer and computer system
EP3885878A1 (en) Voltage minimum active protection circuit and method of operating same
CN105068915A (en) Power supply management device and method
CN103746417A (en) Low-power consumption control method and system for battery monitoring chip
US20130234649A1 (en) Battery management system and method therefor
KR101957245B1 (en) Electronic apparatus and method for drive control thereof
US8022676B2 (en) Electronic device
JP5415173B2 (en) Method for controlling power consumption of portable computer
JP5135463B1 (en) Electronic equipment, power consumption measurement method
US20220344728A1 (en) Battery temperature management
JP6649579B2 (en) Electronic system, function expansion device and power management program
US9836114B1 (en) Event-based trigger for managing battery consumption
US11237610B2 (en) Handling loss of power for uninterruptible power supply efficiency
CN114629187A (en) Charging control method and device and electronic equipment

Legal Events

Date Code Title Description
AS Assignment

Owner name: BROADCOM CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NABHANE, WALID;REEL/FRAME:031079/0654

Effective date: 20130717

AS Assignment

Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001

Effective date: 20160201

Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001

Effective date: 20160201

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001

Effective date: 20170120

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001

Effective date: 20170120

AS Assignment

Owner name: BROADCOM CORPORATION, CALIFORNIA

Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041712/0001

Effective date: 20170119