US20130185687A1

US20130185687A1 - Parameterized cell layout generation guided by a design rule checker

Info

Publication number: US20130185687A1
Application number: US13/684,496
Authority: US
Inventors: Chien-Fu Chung; Yuan-Kai Pei; Shyh-An Tang
Original assignee: Individual
Current assignee: Springsoft Inc; Synopsys Inc
Priority date: 2012-01-12
Filing date: 2012-11-24
Publication date: 2013-07-18
Anticipated expiration: 2032-11-24
Also published as: US8869084B2

Abstract

A method for generating a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC) is disclosed. In the method, a model is defined, wherein the model comprises a plurality of parameters for generating a layout of the cell. Next an initial layout for the cell can be generated according to an initial set of values for the plurality of parameters. Then design rule checking (DRC) is performed for the initial layout based on a set of design rules. If any violations are found, the corresponding violation reports will be associated with the model. Therefore, a new set of values for the plurality of parameters can be generated by analyzing the violation reports collectively based on the model. With the new set of values for the plurality of parameters and above steps repeated, until no violation is found, a “DRC clean” layout can be generated.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority of U.S. Provisional Application No. 61/585,650, filed Jan. 12, 2012, and titled “Parameterized Cell Layout Generation Guided by a Design Rule Checker”, the contents of which are herein incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The invention relates in general to a method for layout generation for an integrated circuits (IC), and more particular to a method for layout generation for a parameterized cell of an integrated circuit (IC) guided by design rule checking (DRC).
2. Description of the Prior Art
Analog circuit designers typically use parameterized cells (PCells) as building blocks to design analog ICs. PCells are design units which use parameter values to calculate IC layouts. An example is a PMOS PCell that takes channel width and channel length as parameters. After a user selecting the PMOS PCell and specifying values for the two parameters, a PMOS layout with the specified channel length and width is automatically generated and placed at the location indicated by the user. In addition, the generated layout satisfies all design rules that are typically described in a technology file which is set along with the definition of PCells initially. Thus, the generated PCell layout is free of design rule violations, which is also called “DRC clean”.
As process technology advances, new design rules become so complex that it's very difficult, if not impossible, to generate optimal layouts for PCells that are also DRC clean. The reason is that for many complex design rules, the PCell generator has to estimate the positions and dimensions of some geometry shapes that are yet to be generated. Often times, there is a deviation between the estimate and the actual numbers. So, to play safe,
PCell generators typically take a conservative approach, namely, using larger dimensions and spacing that can satisfy worst case scenarios. With this approach, the generated layouts are typically less than ideal.
FIG. 1 is an example for prior art. It shows a MOS layout which a PCell generator may generate. The layout consists of polygon 100 on poly layer for the gate of the MOS transistor, polygon 102 on diffusion layer for the source and drain, polygons 104 and 114 on metal layer (metal 1) for source and drain connections, and polygons 106, 108, 110 and 112 on contact cut layer (metal 1 to poly cut layer) for metal to diffusion connections. Dimensions and locations of the polygons in FIG. 1 may be determined in one of the following ways:
1. They may be specified directly by the user. For example, the horizontal span of polygon 100 is the value of the channel length parameter specified by the user.
2. They may be determined by user specified values and design rule values specified in the associated technology file. For example, the vertical span of polygon 100 is the sum of channel width parameter value specified by the user plus twice of the minimum value of extension of poly over diff, which is specified in the technology file.
3. They may be determined by specifications in the technology file. For example, enclosures 120 and 122 are metal over contact minimum required values, and are specified in the technology file.
As process technologies advance, design rules become more and more complex. Design rule values, such as metal over contact enclosures, are no longer simple constant values. Let's take enclosure 120 and enclosure 122 in FIG. 1 as an example. For advanced design rules, enclosures 120 and 122 may depend on the dimensions of polygon 104, dimensions of polygon 114, the distance between 104 and 114, and the parallel run length between 104 and 114. In other words, in order to calculate the optimal values for 120 and 122, we need to know the dimensions of 104, 114, the distance in between, and the parallel run length between 104 and 114.
Typically, PCell layouts are generated in a sequential manner. In FIG. 1 for example, polygons 100, 102 and 104 may be generated first; then polygons 106 and 108 are generated. The values for metal to contact enclosures will decide where and how many the contact polygons (e.g. polygons 106, 108) are to be generated. For complex enclosure rules, the value is a function of the dimensions of metals 104 and 114, the distance in between, and the parallel run length between 104 and 114. However, at this moment, polygon 114 is not generated yet, and so its location and dimensions are not known. In order to calculate the values for 120 and 122, we have to estimate the dimensions and the location for polygon 114. Later, when polygon 114 is generated, if it comes out as exact as previously estimated, then everything is good. More often than not, the actual dimensions and location for 114 are different from original estimation, and a DRC violation may occur. To fix the DRC violation, we will need to go back to re-calculate the values for 120 and 122 with a better estimation for polygon 114, and re-generate portions of the layout. The new result may be all correct, or may be not. If it's not correct, the same steps will have to repeat once more. This makes the layout generation complicated.
Besides the example for enclosure issue shown above, there may be many other advanced design rules that have to be taken care of. Each design rule posts a different challenge and has to be satisfied in the final layout.
Therefore, what is needed is a systematic way to efficiently and effectively generate layouts that satisfy all the advanced design rules while not relying on the estimation of layout components that are yet to be generated.

SUMMARY OF THE INVENTION

One object of the present invention is to generate a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC).
In one embodiment of the present invention, a model is defined, wherein the model comprises a plurality of parameters for generating a layout of the cell. Next an initial layout for the cell can be generated according to an initial set of values for the plurality of parameters. Then design rule checking (DRC) is performed for the initial layout based on a set of design rules. If any violations are found, the corresponding violation reports will be applied to the model. A violation report typically contains information such as the name of the design rule violated, the two edges on layout objects where the violation is detected, and the minimum desirable dimension needed to clear the violation, and etc. By analyzing these pieces of information in violation reports and applying the analysis results to the model, a new set of values for the plurality of parameters can be generated. With the new set of values for the plurality of parameters and above steps repeated until no violation is found, a “DRC clean” layout can be generated.
In one embodiment, the model comprises associating each design rule with a set of properties to indicate the information of the design rule name, the category of the design rule, the corresponding components/shapes in the PCell related to the violation checking for the design rule. The properties will be included in DRC violation reports, and can be used to adjust the set of parameter values.
In one embodiment, the actions for parameter value adjusting disclosed above can be done by executing callback functions. Furthermore, callback function names may be specified in properties.
Other objects, technical contents, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 illustrates an example to explain how a layout for a PCell is generated in prior art;

FIG. 2 depicts the schematic flow diagram of the current invention;

FIG. 3 shows an example of how to fix the metal 1 to contact enclosure violation;

FIG. 4 shows an example of how to fix the metal spacing violation; and

FIG. 5 illustrates a schematic flow diagram of one embodiment which contains the invocation of callback functions.

DETAILED DESCRIPTION OF THE INVENTION

The detailed explanation of the present invention is described as following. The described preferred embodiments are presented for purposes of illustrations and description, and they are not intended to limit the scope of the present invention.
Please refer to FIG. 2 which depicts the schematic flow diagram of the current invention for generating a layout for a parameterized cell (PCell) of an integrated circuit (IC). Firstly, a model is defined, wherein the model comprises a plurality of parameters for generating a set of geometry shapes to form the layout of the cell (step 210). In the model, the logics of DRC violation analysis and the corresponding parameter adjustment algorithms are grouped systematically, which will be explained later. Next an initial set of values for the plurality of parameters are assigned (step 220). Thus an initial layout for the cell can be generated according to the initial set of values for the plurality of parameters (step 230).
Then, a design rule checker is invoked to perform DRC for the initial layout based on a set of design rules (step 240). If any violations are found (step 250), the corresponding violation reports will be applied to the model (step 270). A new set of values for the plurality of parameters will be generated by analyzing the violation reports collectively based on the model. With the new set of values for the plurality of parameters, step 230˜step 270 are repeated until no violation is found, which means a “DRC clean” layout is generated (step 260). In one embodiment, the iteration stops when a pre-defined number of iteration cycles is reached before all violations are resolved.
In one embodiment, violation reports may be in the form of special type objects that the DRC checker generates and stores in the database in which PCell layouts reside. In another embodiment, violation reports may be in the form of external files that contain the descriptions for each design rule violation that the DRC checker detects, or any other forms.
In one embodiment, the model comprises associating each design rule with a set of properties. Each property indicates the information of the design rule name, the category of the design rule, the corresponding components/shapes in the PCell related to the violation checking for the design rule. Thus, when a violation is detected, the corresponding property is attached to the violation report.
To depict more details about the properties, in one embodiment, design rules can be categorized as “spacing” rules, “width” rules and “enclosure” rules. Spacing rules control the minimum distance required between two adjacent shapes; width rules control the minimum width a shape can take; and enclosure rules control the extent a shape has to cover over another shape underneath it.
As for the components/shapes in PCell, taking MOS transistor as an example, it may have “gate”, “source-drain” and “contact” components. Moreover, contacts may consist of “source-drain contact cut” and “metal over source-drain contact cut”. We can name each category of shapes by combining their functionality with its layer name. For example, “gate” components may be referred to as “GatePoly”, “source-drain” may be referred to as “ActiveOD” (source-drain are the “active” regions of the transistor and the layer that defines the source-drain area is usually called the OD layer), “source-drain contact cut” may be referred to as “ActiveContact” (for contact cuts over active regions), and “metal over source-drain contact cut” may be referred to as “ActiveMetal”.
Following is an exemplary format for design rule properties in accordance with the current invention:
{rule-name {rule-category {device-type shape-category . . . }}}
One property example is shown below:
{M1CO.EN.1 {enclosure {XTR ActiveMetal ActiveContact}}}.
It indicates that the rule name is “M1CO.EN.1” (metal on contact enclosure rule 1. Actual rule names should come from the process technology used); the rule category is “enclosure”; the device type is “XTR” (transistor type PCell); and the two objects involved are of type “ActiveMetal” and “ActiveContact”.
Another property example is provided:
{M1.S.1 {spacing {XTR ActiveMetal ActiveMetal}}}.
It indicates that the rule name is “M1.S.1” (metal spacing rule 1); the rule category is “spacing”; the device type is “XTR”; and the two objects involved are both of type “ActiveMetal”. The two metal objects are for the connections to source and drain contacts, respectively.
In one embodiment, properties may be specified in a property file. Upon invocation, current invention reads the design rules from a technology file and properties from a property file. It combines the two files and prepares an input rule deck in a format that the DRC checker supports. Then, it feeds the generated rule deck to the DRC checker.
FIG. 3 shows an example of how to fix the metal 1 to contact enclosure. To begin with, we may define the property as follows:
{M1CO.EN.1 {enclosure {XTR ActiveMetal ActiveContact}}}.
When we get a violation report containing such a property, we know we have to enlarge the enclosure for the specified metal and contact objects. The locations of the two violating edges which can be found in the violation report can lead us to the metal shape object and the contact shape object. The value for the minimum required enclosure is also available in the violation report.
Please refer to FIG. 3. To fix this DRC violation, two parameters EncX (301) and EncY (302) are defined for x-dimensional enclosure and y-dimensional enclosure respectively. Then parameter EncX (301) or parameter EncY (302) can be adjusted according to the minimum enclosure value. We can use the violation edges to decide if it's horizontal EncX (301) or vertical EncY (302) that is to be adjusted. If the two edges are horizontal edges, then it is EncY (302) that is to be adjusted. Otherwise, it's EncX (301).
FIG. 4 shows an example of how to fix the metal spacing (401). We may define the property as follows:
{M1.S.1 {spacing {XTR ActiveMetal ActiveMetal}}}.
When we get a violation report containing such a property, we know we have to enlarge the spacing between the two metal objects. This may affect the following two shapes:
1.The active region (i.e. source-drain region), and
2.The associated contact(s).
To simplify the fix procedure, we limit the fix to the metal, which is on the “right-hand side”, i.e. moving the shapes having larger X coordinate in the layout, leaving shapes on the “left-hand side” unchanged. To further simplify the fix procedure, we introduce two auxiliary parameters: ODlength (402) and contactMetalOrigin (contactMetalOriginX, contactMetalOriginY) (403). The ODlength (402) value determines the length of the OD region on the right-hand side, and the contactMetalOrigin (403) determines the location of the contact metal object.
To fix the metal spacing (401), we need to move the contactMetalOrigin (403) to the right. The amount can be readily calculated using the desired spacing value found in the violation report, and the current value in the layout. The other parameter, ODlength (402) may or may not need fixing. If we have to use the same contact, then ODlength (402) has to be incremented by the same amount as the displacement of contactMetalOrigin (403). On the other hand, if we can create a “narrower” contact based on the new location of contactMetalOrigin (403) and original value of ODlength (402), then we can leave ODlength (402) unchanged.
After the contactMetalOrigin (403) and ODlength (402) are determined, we can re-generate the layout for the transistor. The metal 1 spacing violation should be cleared.
FIG. 5 illustrates a schematic flow diagram of one embodiment which contains the invocation of callback functions after DRC checking. Most of the steps have been shown in FIG. 2. In step 510, callback functions are executed in order to apply the DRC violation reports to the model for generating a new set of values for the plurality of parameters.
In one embodiment, callback function names may be specified in properties as shown in below examples:
{M1CO.EN.1 {enclosure {XTR ActiveMetal ActiveContact {FixContactMetalEnclsoureCB }}}},
and
{M1.S.1 {spacing {XTR ActiveMetal ActiveMetal {FixActiveMetalSpacingCB}}}}
Then, in each DRC violation report, we can find the callback function name, and call the function accordingly. When calling a callback function, we can pass the DRC violation report object to it. Using the properties and attributes associated with the DRC violation report objects, the callback functions can decide what parameters to adjust and by how much.
By grouping the decision making and parameter value adjusting in callback functions, the flow for layout generation for PCells with the help from a DRC checker becomes well organized.
In one embodiment, when there are multiple objects under the same shape category, we can tag the shapes with unique identifiers so that we can know which specific shape or shapes the violation is pertaining to. For example, when there are multiple fingers (number of poly gate is greater than 1) on a transistor, there will be more than 2 source-drain regions.
When a metal 1 spacing rule or metal 1 to OD enclosure rule is violated, we need to know which source-drain region or which pair of source-drain regions is the source of this violation. As disclosed above, by using the information in the violation report, we can find the shape object or objects that cause the violation. Then, by using the tags in the shape objects, we know which parameters to adjust to clear the violation. The same technique can be applied to tagging contact and metal objects.
In one embodiment, to support new design rules, new entries can be added systematically to the property specification file for the new rules and new callback functions should be implemented accordingly.
To support changes to existing design rules, we just have to modify the associated callback functions accordingly.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustrations and description. They are not intended to be exclusive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

Claims

What is claimed is:

1. A computer-implemented method for generating a set of geometry shapes to form a layout for a parameterized cell (P-Cell) of an integrated circuit (IC) without violating design rules (DRC clean), wherein the cell is associated with a first set of design rules, the method comprising using a computer to perform the steps of:

a. defining a model comprising a plurality of parameters for generating the set of geometry shapes;

b. generating a first set of geometry shapes according to a first set of values for the plurality of parameters;

c. performing design rule checking on the first set of geometry shapes according to the first set of design rules to generate a first set of violation reports;

d. modifying the first set of values to generate a second set of values for the plurality of parameters by applying the first set of violation reports to the model; and

e. generating a second set of geometry shapes according to the second set of values for the plurality of parameters.

2. The computer-implemented method according to claim 1, further comprising the steps of:

f. performing design rule checking on the second set of geometry shapes according to the first set of design rules to generate a second set of violation reports;

g. modifying the second set of values to generate a third set of values for the plurality of parameters by applying the second set of violation reports to the model; and

h. generating a third set of geometry shapes according to the third set of values for the plurality of parameters.

3. The computer-implemented method according to claim 1, wherein each of the design rules is associated with at least one of a set of properties, wherein each of the set of properties comprises a design rule name, the category of the design rule, the device type of the P-cell that the design rule applies to, and at least one category of geometry shape in the P-cell layout that the design rule applies to, wherein violation reports pertaining to a design rule include the information from the at least one of a set of properties associated with that design rule.

4. The computer-implemented method according to claim 3, wherein each of the set of properties also comprises a callback function, the function name also being included in the corresponding violation reports, wherein applying the first set of violation reports to the model in step d is performed by executing each of the corresponding callback functions passing the violation report as an argument to the callback function.

5. The computer-implemented method according to claim 3, wherein edges violating the design rule are included in a violation report, and by using the edges information in the violation report, shape objects in the generated layout that violate the design rule can be identified.

6. The computer-implemented method according to claim 5, wherein shape objects in the generated layout are tagged with unique identifiers, and after the shape objects that violate the design rule are identified, tagged identifiers on the shape objects are used to determine which parameter values need adjusting.

7. A non-transitory computer readable medium storing one or more programs for generating a set of geometry shapes to form a layout for a cell of an integrated circuit (IC) with design rule checking (DRC), wherein the cell is associated with a first set of design rules, said one or more programs comprising instructions, which when executed by a computer, cause the computer to perform the steps of: