US20120049338A1 - Stackable semiconductor device packages - Google Patents
Stackable semiconductor device packages Download PDFInfo
- Publication number
- US20120049338A1 US20120049338A1 US13/290,819 US201113290819A US2012049338A1 US 20120049338 A1 US20120049338 A1 US 20120049338A1 US 201113290819 A US201113290819 A US 201113290819A US 2012049338 A1 US2012049338 A1 US 2012049338A1
- Authority
- US
- United States
- Prior art keywords
- package
- connecting elements
- substrate unit
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract
In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.
Description
- This application is a continuation of co-pending U.S. patent application Ser. No. 12/507,305, filed on Jul. 22, 2009, which claims the benefit of Taiwan Application Serial No. 98100325, filed on Jan. 7, 2009. The disclosures of both priority applications are incorporated herein by reference in their entireties.
- The present invention relates generally to semiconductor device packages. More particularly, the invention relates to stackable semiconductor device packages.
- Electronic products have become progressively more complex, driven at least in part by the demand for enhanced functionality and smaller sizes. While the benefits of enhanced functionality and smaller sizes are apparent, achieving these benefits also can create problems. In particular, electronic products typically have to accommodate a high density of semiconductor devices in a limited space. For example, the space available for processors, memory devices, and other active or passive devices can be rather limited in cell phones, personal digital assistants, laptop computers, and other portable consumer products. In conjunction, semiconductor devices are typically packaged in a fashion to provide protection against environmental conditions as well as to provide input and output electrical connections. Packaging of semiconductor devices within semiconductor device packages can take up additional valuable space within electronic products. As such, there is a strong drive towards reducing footprint areas taken up by semiconductor device packages. One approach along this regard is to stack semiconductor device packages on top of one another to form a stacked package assembly, which is also sometimes referred as a package-on-package (“PoP”) assembly.
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FIG. 1 illustrates astacked package assembly 100 implemented in accordance with a conventional approach, in which atop package 102 is disposed above and electrically connected to abottom package 104. Thetop package 102 includes asubstrate unit 106 and asemiconductor device 108, which is disposed on anupper surface 118 of thesubstrate unit 106. Thetop package 102 also includes apackage body 110 that covers thesemiconductor device 108. Similarly, thebottom package 104 includes asubstrate unit 112, asemiconductor device 114, which is disposed on anupper surface 120 of thesubstrate unit 112, and apackage body 116, which covers thesemiconductor device 114. Referring toFIG. 1 , a lateral extent of thepackage body 116 is less than that of thesubstrate unit 112, such that a peripheral portion of theupper surface 120 remains exposed. Extending between this peripheral portion and alower surface 122 of thesubstrate unit 106 are solder balls, includingsolder balls top package 102 and are reflowed during stacking operations to electrically connect thetop package 102 to thebottom package 104. As illustrated inFIG. 1 , thebottom package 104 also includessolder balls lower surface 128 of thesubstrate unit 112 and provide input and output electrical connections for theassembly 100. - While a higher density of the
semiconductor devices assembly 100 can suffer from a number of disadvantages. In particular, the relatively large solder balls, such as thesolder balls top package 102 and thebottom package 104 take up valuable area on theupper surface 120 of thesubstrate unit 112, thereby hindering the ability to reduce a distance between adjacent ones of the solder balls as well as hindering the ability to increase a total number of the solder balls. Also, manufacturing of theassembly 100 can suffer from undesirably low stacking yields, as thesolder balls substrate unit 112 of thebottom package 104 during reflow. This inadequate adherence can be exacerbated by molding operations used to form thepackage body 116, as a molding material can be prone to overflowing onto and contaminating the peripheral portion of theupper surface 120. Moreover, because of the reduced lateral extent of thepackage body 116, theassembly 100 can be prone to bending or warping, which can create sufficient stresses on thesolder balls - It is against this background that a need arose to develop the stackable semiconductor device packages and related stacked package assemblies and methods described herein.
- One aspect of the invention relates to semiconductor device packages. In one embodiment, a semiconductor device package includes: (1) a substrate unit including an upper surface, a lower surface, and a lateral surface disposed adjacent to a periphery of the substrate unit and extending between the upper surface and the lower surface of the substrate unit; (2) connecting elements disposed adjacent to the periphery of the substrate unit and extending upwardly from the upper surface of the substrate unit, at least one of the connecting elements having a width WC; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including an upper surface and a lateral surface, the lateral surface of the package body being substantially aligned with the lateral surface of the substrate unit, the package body defining openings disposed adjacent to the upper surface of the package body, the openings at least partially exposing respective ones of the connecting elements, at least one of the openings having a width WU adjacent to the upper surface of the package body, such that WU>WC.
- Another aspect of the invention relates to stacked package assemblies. In one embodiment, a stacked package assembly includes: (1) a first semiconductor device package including (a) a substrate unit including an upper surface, (b) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit, and (c) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including an upper surface and defining openings disposed adjacent to the upper surface of the package body; (2) a second semiconductor device package disposed adjacent to the upper surface of the package body, the second semiconductor device package including a lower surface; and (3) stacking elements extending through respective ones of the openings of the package body and electrically connecting the first semiconductor device package and the second semiconductor device package, at least one of the stacking elements corresponding to a pair of fused conductive bumps and including (a) an upper portion disposed adjacent to the lower surface of the second semiconductor device package and having a width WSU, (b) a lower portion having a lateral boundary that is at least partially covered by the package body and having a width WSL, and (c) a middle portion disposed between the upper portion and the lower portion and having a width WSM, such that WS.gtoreq.0.8.times.min (WSU, WSL).
- A further aspect of the invention relates to manufacturing methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including an upper surface and contact pads disposed adjacent to the upper surface of the substrate; (2) applying an electrically conductive material to the upper surface of the substrate to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to the upper surface of the substrate to form a molded structure covering the conductive bumps and the semiconductor device, the molded structure including an upper surface; (5) forming openings adjacent to the upper surface of the molded structure, the openings partially exposing respective ones of the conductive bumps to define covered portions and uncovered portions of the conductive bumps, at least one of the openings having a central depth DC and a peripheral depth DP, the central depth DC corresponding to a distance between the upper surface of the molded structure and an upper end of a respective one of the conductive bumps, the peripheral depth DP corresponding to a distance between the upper surface of the molded structure and a boundary between a covered portion and an uncovered portion of the respective one of the conductive bumps, the peripheral depth DP being greater than the central depth DC, such that DP=cDC, and c.gtoreq.1.5; and (6) forming cutting slits extending through the molded structure and the substrate.
- Other aspects and embodiments of the invention are also contemplated. The foregoing summary and the following detailed description are not meant to restrict the invention to any particular embodiment but are merely meant to describe some embodiments of the invention.
- For a better understanding of the nature and objects of some embodiments of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings. In the drawings, like reference numbers denote like elements, unless the context clearly dictates otherwise.
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FIG. 1 illustrates a stacked package assembly implemented in accordance with a conventional approach. -
FIG. 2 illustrates a perspective view of a stackable semiconductor device package implemented in accordance with an embodiment of the invention. -
FIG. 3 illustrates a cross-sectional view of the package ofFIG. 2 , taken along line A-A ofFIG. 2 . -
FIG. 4 illustrates an enlarged, cross-sectional view of a portion of the package ofFIG. 2 . -
FIG. 5 illustrates a cross-sectional view of a stacked package assembly formed using the package ofFIG. 2 , according to an embodiment of the invention. -
FIG. 6A throughFIG. 6C illustrate enlarged, cross-sectional views of a portion of the assembly ofFIG. 5 . -
FIG. 7 illustrates a cross-sectional view of a stackable semiconductor device package implemented in accordance with another embodiment of the invention. -
FIG. 8 illustrates a cross-sectional view of a stackable semiconductor device package implemented in accordance with another embodiment of the invention. -
FIG. 9A throughFIG. 9G illustrate a manufacturing method of forming the package ofFIG. 2 and the assembly ofFIG. 5 , according to an embodiment of the invention. - The following definitions apply to some of the aspects described with respect to some embodiments of the invention. These definitions may likewise be expanded upon herein.
- As used herein, the singular terms “a,”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a semiconductor device can include multiple semiconductor devices unless the context clearly dictates otherwise.
- As used herein, the term “set” refers to a collection of one or more components. Thus, for example, a set of layers can include a single layer or multiple layers. Components of a set also can be referred as members of the set. Components of a set can be the same or different. In some instances, components of a set can share one or more common characteristics.
- As used herein, the term “adjacent” refers to being near or adjoining Adjacent components can be spaced apart from one another or can be in actual or direct contact with one another. In some instances, adjacent components can be connected to one another or can be formed integrally with one another.
- As used herein, relative terms, such as “inner,” “interior,” “outer,” “exterior,” “top,” “bottom,” “upper,” “upwardly,” “lower,” “downwardly,” “vertical,” “vertically,” “lateral,” “laterally,” “above,” and “below,” refer to an orientation of a set of components with respect to one another, such as in accordance with the drawings, but do not require a particular orientation of those components during manufacturing or use.
- As used herein, the terms “connect,” “connected,” “connecting,” and “connection” refer to an operational coupling or linking. Connected components can be directly coupled to one another or can be indirectly coupled to one another, such as via another set of components.
- As used herein, the terms “substantially” and “substantial” refer to a considerable degree or extent. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation, such as accounting for typical tolerance levels of the manufacturing operations described herein.
- As used herein, the terms “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically correspond to those materials that exhibit little or no opposition to flow of an electric current. One measure of electrical conductivity is in terms of Siemens per meter (“Sm.sup.−1”). Typically, an electrically conductive material is one having a conductivity greater than about 10.sup.4 Sm.sup.−1, such as at least about 10.sup.5 Sm.sup.−1 or at least about 10.sup.6 Sm.sup.−1. Electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, electrical conductivity of a material is defined at room temperature.
- Attention first turns to
FIG. 2 andFIG. 3 , which illustrate a stackablesemiconductor device package 200 implemented in accordance with an embodiment of the invention. In particular,FIG. 2 illustrates a perspective view of thepackage 200, whileFIG. 3 illustrates a cross-sectional view of thepackage 200, taken along line A-A ofFIG. 2 . In the illustrated embodiment, sides of thepackage 200 are substantially planar and have a substantially orthogonal orientation so as to define a lateral profile that extends around substantially an entire periphery of thepackage 200. However, it is contemplated that the lateral profile of thepackage 200, in general, can be any of a number of shapes, such as curved, inclined, stepped, or roughly textured. - Referring to
FIG. 2 andFIG. 3 , thepackage 200 includes asubstrate unit 202, which includes anupper surface 204, alower surface 206, and lateral surfaces, includinglateral surfaces substrate unit 202 and extend between theupper surface 204 and thelower surface 206. In the illustrated embodiment, the lateral surfaces 242 and 244 are substantially planar and have a substantially orthogonal orientation with respect to theupper surface 204 or thelower surface 206, although it is contemplated that the shapes and orientations of thelateral surfaces substrate unit 202, namely a vertical distance between theupper surface 204 and thelower surface 206 of thesubstrate unit 202, can be in the range of about 0.1 millimeter (“mm”) to about 2 mm, such as from about 0.2 mm to about 1.5 mm or from about 0.4 mm to about 0.6 mm. - The
substrate unit 202 can be implemented in a number of ways, and includes electrical interconnect to provide electrical pathways between theupper surface 204 and thelower surface 206 of thesubstrate unit 202. As illustrated inFIG. 3 , thesubstrate unit 202 includescontact pads upper surface 204, andcontact pads lower surface 206. In the illustrated embodiment, thecontact pads contact pads FIG. 3 . Thecontact pads substrate unit 202, while thecontact pads contact pads contact pads contact pads contact pads substrate unit 202, such as a set of electrically conductive layers that are incorporated within a set of dielectric layers. The electrically conductive layers can be connected to one another by internal vias, and can be implemented so as to sandwich a core formed from a suitable resin, such as one based on bismaleimide and triazine or based on epoxy and polyphenylene oxide. For example, thesubstrate unit 202 can include a substantially slab-shaped core that is sandwiched by one set of electrically conductive layers disposed adjacent to an upper surface of the core and another set of electrically conductive layers disposed adjacent to a lower surface of the core. While not illustrated inFIG. 3 , it is contemplated that a solder mask layer can be disposed adjacent to either, or both, theupper surface 204 and thelower surface 206 of thesubstrate unit 202. - As illustrated in
FIG. 3 , thepackage 200 also includes connectingelements 218 a. 218 b, 218 c, and 218 d that are disposed adjacent to the peripheral portion of theupper surface 204. The connectingelements contact pads substrate unit 202. As further described below, the connectingelements package 200 and another package within a stacked package assembly. In the illustrated embodiment, the connectingelements elements FIG. 3 , a size of each connectingelement element element element element element element - Referring to
FIG. 3 , thepackage 200 also includes asemiconductor device 208, which is disposed adjacent to theupper surface 204 of thesubstrate unit 202, and connectingelements lower surface 206 of thesubstrate unit 202. In the illustrated embodiment, thesemiconductor device 208 is a semiconductor chip, such as a processor or a memory device. Thesemiconductor device 208 is wire-bonded to thesubstrate unit 202 via a set ofwires 212, which are formed from gold, copper, or another suitable electrically conductive material. For certain implementations, at least a subset of thewires 212 is desirably formed from copper, since, as compared to gold, copper has a superior electrical conductivity and a lower cost, while allowing thewires 212 to be formed with reduced diameters. Thewires 212 can be coated with a suitable metal, such as palladium, as a protection against oxidation and other environmental conditions. The connectingelements package 200, and are electrically connected to and extend downwardly from respective ones of thecontact pads elements elements elements semiconductor device 208 via electrical interconnect included in thesubstrate unit 202, and at least the same or a different subset of the connectingelements elements substrate unit 202. While thesingle semiconductor device 208 is illustrated inFIG. 3 , it is contemplated that additional semiconductor devices can be included for other implementations, and that semiconductor devices, in general, can be any active devices, any passive devices, or combinations thereof. - Referring to
FIG. 2 andFIG. 3 , thepackage 200 also includes apackage body 214 that is disposed adjacent to theupper surface 204 of thesubstrate unit 202. In conjunction with thesubstrate unit 202, thepackage body 214 substantially covers or encapsulates thesemiconductor device 208 and thewires 212 to provide structural rigidity as well as protection against oxidation, humidity, and other environmental conditions. Advantageously, thepackage body 214 extends to the sides of thesubstrate unit 202 and partially covers or encapsulates the connectingelements upper surface 204 so as to provide improved structural rigidity and reduced tendency towards bending or warping. - The
package body 214 is formed from a molding material, and includes anupper surface 224 and lateral surfaces, includinglateral surfaces package body 214. In the illustrated embodiment, theupper surface 224 is substantially planar and has a substantially parallel orientation with respect to theupper surface 204 or thelower surface 206 of thesubstrate unit 202. Accordingly, a thickness HP of thepackage body 214, namely a vertical distance between theupper surface 224 of thepackage body 214 and theupper surface 204 of thesubstrate unit 202, is substantially uniform across theupper surface 204 of thesubstrate unit 202, thereby allowing thepackage body 214 to provide a more uniform coverage of theupper surface 204 and improved structural rigidity. However, it is contemplated that theupper surface 224 can be curved, inclined, stepped, or roughly textured for other implementations. For certain implementations, the thickness HP of thepackage body 214 can be in the range of about 100 μm to about 600 μm, such as from about 150 μm to about 550 μm or from about 200 μm to about 500 μm. Disposed adjacent to a peripheral portion of theupper surface 224 and extending downwardly from theupper surface 224 are depressions, includingdepressions elements elements package 200. Like the connectingelements FIG. 2 andFIG. 3 , it is contemplated that more or less rows of openings can be included for other implementations, and that openings, in general, can be distributed in any one-dimensional pattern or any two-dimensional pattern. - Referring to
FIG. 2 andFIG. 3 , the lateral surfaces 220 and 222 of thepackage body 214 are substantially planar and have a substantially orthogonal orientation with respect to theupper surface 204 or thelower surface 206 of thesubstrate unit 202, although it is contemplated that thelateral surfaces lateral surfaces substrate unit 202, respectively, such that, in conjunction with thelateral surfaces package 200. More particularly, this alignment is accomplished such that a lateral extent of thepackage body 214 substantially corresponds to that of thesubstrate unit 202, thereby allowing thepackage body 214 to provide a more uniform coverage of theupper surface 204 and improved structural rigidity. For other implementations, it is contemplated that the shapes of thelateral surfaces lateral surfaces FIG. 2 andFIG. 3 , while providing sufficient structural rigidity and allowing the connectingelements - Attention next turns to
FIG. 4 , which illustrates an enlarged, cross-sectional view of a portion of thepackage 200 ofFIG. 2 andFIG. 3 . In particular,FIG. 4 illustrates a particular implementation of thepackage body 214 and the connectingelements package 200 are omitted for ease of presentation. - As illustrated in
FIG. 4 , thepackage body 214 is formed with thedepressions openings elements openings elements elements package 200. Also, the relatively large areas of the connection surfaces Sa and Sb can enhance reliability and efficiency of electrical connections, thereby improving stacking yields. During stacking operations, thepackage body 214 can have a tendency to expand towards and apply stresses onto the connectingelements elements contact pads openings elements package body 214, thereby relieving expansion stresses that can otherwise lead to connection failure. Moreover, theopenings - In the illustrated embodiment, an opening, such as the opening 400 a or 400 b, is shaped in the form of a circular cone or a circular funnel, including a substantially circular cross-section with a width that varies along a vertical direction. In particular, a lateral boundary of an opening, such as defined by the
depression element depression - For certain implementations, an upper width WU of each opening 400 a or 400 b, namely a lateral extent adjacent to an upper end of the opening 400 a or 400 b and adjacent to the
upper surface 224 of thepackage body 214, can be in the range of about 250 μm to about 650 μm, such as from about 300 μm to about 600 μm or from about 350 μm to about 550 μm, and a lower width WL of each opening 400 a or 400 b, namely a lateral extent adjacent to a lower end of the opening 400 a or 400 b and adjacent to the boundary between covered and uncovered portions of a respective connectingelement opening element elements openings lateral wall 402 that is disposed between the connectingelements lateral wall 402 can serve as a barrier to avoid or reduce instances of overflow of an electrically conductive material during stacking operations, thereby allowing stacking elements to be formed with a reduced distance with respect to one another. - Still referring to
FIG. 4 , a connecting element, such as the connectingelement package body 214, such that an upper end of the connecting element is recessed below theupper surface 224 of thepackage body 214, namely such that the height HC of the connecting element is less than the thickness HP of thepackage body 214. However, it is also contemplated that an upper end of a connecting element can be substantially aligned or co-planar with theupper surface 224 or can protrude above theupper surface 224. As illustrated inFIG. 4 , an opening, such as the opening 400 a or 400 b, has a depth that varies along a lateral direction or along a radial direction relative to a center of the opening. In the illustrated embodiment, a central depth DC of each opening 400 a or 400 b, namely a vertical distance between theupper surface 224 of thepackage body 214 and an upper end of a respective connectingelement upper surface 224 of thepackage body 214 and a boundary between covered and uncovered portions of a respective connectingelement package body 214 and the width WC of a respective connectingelement -
FIG. 5 illustrates a cross-sectional view of a stackedpackage assembly 500 implemented in accordance with an embodiment of the invention. In particular.FIG. 5 illustrates a particular implementation of theassembly 500 that is formed using thepackage 200 ofFIG. 2 throughFIG. 4 . - As illustrated in
FIG. 5 , theassembly 500 includes asemiconductor device package 502, which corresponds to a top package that is disposed above and electrically connected to thepackage 200 that corresponds to a bottom package. In the illustrated embodiment, thepackage 502 is implemented as a ball grid array (“BGA”) package, although it is contemplated that a number of other package types can be used, including a land grid array (“LGA”) package, a quad flat no-lead (“QFN”) package, an advanced QFN (“aQFN”) package, and other types of BGA package, such as a window BGA package. While the twostacked packages FIG. 5 , it is contemplated that additional packages can be included for other implementations. Certain aspects of thepackage 502 can be implemented in a similar fashion as previously described for thepackage 200 and, thus, are not further described herein. - Referring to
FIG. 5 , thepackage 502 includes asubstrate unit 504, which includes anupper surface 506, alower surface 508, and lateral surfaces, includinglateral surfaces substrate unit 504 and extend between theupper surface 506 and thelower surface 508. Thesubstrate unit 504 also includescontact pads lower surface 508. In the illustrated embodiment, thecontact pads FIG. 5 . - The
package 502 also includes asemiconductor device 516, which is a semiconductor chip that is disposed adjacent to theupper surface 506 of thesubstrate unit 504. In the illustrated embodiment, thesemiconductor device 516 is wire-bonded to thesubstrate unit 504 via a set ofwires 518, although it is contemplated that thesemiconductor device 516 can be electrically connected to thesubstrate unit 504 in another fashion, such as by flip chip-bonding. While thesingle semiconductor device 516 is illustrated within thepackage 502, it is contemplated that additional semiconductor devices can be included for other implementations. - Disposed adjacent to the
upper surface 506 of thesubstrate unit 504 is apackage body 520, which substantially covers or encapsulates thesemiconductor device 516 and thewires 518 to provide structural rigidity as well as protection against environmental conditions. Thepackage body 520 includes anupper surface 522 and lateral surfaces, includinglateral surfaces package body 520. In the illustrated embodiment, the lateral surfaces 524 and 526 are substantially aligned or co-planar with thelateral surfaces substrate unit 504, respectively, such that, in conjunction with thelateral surfaces package 502. Referring toFIG. 5 , a lateral extent of thepackage 502 substantially corresponds to that of thepackage 200, although it is contemplated that thepackage 502 can be implemented with a greater or a smaller lateral extent relative to thepackage 200. Also, a thickness T of thepackage 502, namely a vertical distance between theupper surface 522 of thepackage body 520 and thelower surface 508 of thesubstrate unit 504, substantially corresponds to that of thepackage 200, although it is contemplated that thepackage 502 can be implemented with a greater or a smaller thickness relative to thepackage 200. - Referring to
FIG. 5 , thepackage 502 also includes connectingelements 528 a. 528 b, 528 c, and 528 d, which are disposed adjacent to thelower surface 508 of thesubstrate unit 504. The connectingelements package 502, and are electrically connected to and extend downwardly from respective ones of thecontact pads elements elements elements - During stacking operations, the connecting
elements package 502 are reflowed and undergo metallurgical bonding with the connectingelements package 200. In particular, the connectingelements elements elements packages FIG. 5 , each stacking element, such as the stackingelement 530 a, extends and spans a distance between thepackages contact pad 246 a of thepackage 200 and thecontact pad 514 a of thepackage 502. In conjunction, the stackingelements packages lower surface 508 of thepackage 502 and theupper surface 224 of thepackage 200. For certain implementations, the gap G can be in the range of about 10 μm to about 100 μm, such as from about 20 μm to about 80 μm or from about 30 μm to about 70 μm. Suitable selection and control over sizes of the connectingelements elements lower surface 508 of thepackage 502 is in contact with theupper surface 224 of thepackage 200. - A number of advantages can be achieved by stacking the
packages FIG. 5 . In particular, because a pair of connecting elements, such as the connectingelements packages element 530 a, can have a reduced lateral extent and can take up less valuable area, thereby allowing the ability to reduce a distance between adjacent stacking elements as well as the ability to increase a total number of stacking elements. In the illustrated embodiment, the distance between adjacent stacking elements can be specified in accordance with a stacking element pitch P′, which corresponds to a distance between centers of nearest-neighbor stacking elements, such as the stackingelements 530 a and 530 b. For certain implementations, the stacking element pitch P′ can substantially correspond to the connecting element pitch P, which was previously described with reference toFIG. 4 . By suitable selection and control over sizes of the connectingelements elements - Certain aspects of stacking elements can be further appreciated with reference to
FIG. 6A throughFIG. 6C , which illustrate enlarged, cross-sectional views of a portion of theassembly 500 ofFIG. 5 . In particular,FIG. 6A throughFIG. 6C illustrate particular implementations of the opening 400 a and the stackingelement 530 a, while certain other details of theassembly 500 are omitted for ease of presentation. - As illustrated in
FIG. 6A throughFIG. 6C , the stackingelement 530 a is implemented as an elongated structure and, more particularly, as a conductive post that is formed as a result of fusing or merging of the connectingelements element 530 a is shaped in the form of a dumbbell, and includes anupper portion 600 and alower portion 604, which are relatively larger than amiddle portion 602 that is disposed between theupper portion 600 and thelower portion 604. However, it is contemplated that the shape of the stackingelement 530 a, in general, can be any of a number of shapes. Theupper portion 600 substantially corresponds to, or is formed from, the connectingelement 528 a, thelower portion 604 substantially corresponds to, or is formed from, the connectingelement 218 a, and themiddle portion 602 substantially corresponds to, or is formed from, an interface between the connectingelements FIG. 6A throughFIG. 6C , a lateral boundary of thelower portion 604 is substantially covered or encapsulated by thepackage body 214, and a lateral boundary of theupper portion 600 is at least partially disposed within the opening 400 a and is spaced apart from thepackage body 214 so as to remain exposed. However, it is contemplated that the extent of coverage of theupper portion 600 and thelower portion 604 can be varied for other implementations. - Referring to
FIG. 6A throughFIG. 6C , a size of the stackingelement 530 a can be specified in accordance with its height HS, namely a vertical extent of the stackingelement 530 a, a width WSU of theupper portion 600, namely a maximum lateral extent of theupper portion 600, a width WSL of thelower portion 604, namely a maximum lateral extent of thelower portion 604, and a width WSM of themiddle portion 602, namely a minimum lateral extent of themiddle portion 602. As can be appreciated, the height HS of the stackingelement 530 a can substantially correspond to a sum of the thickness HP of thepackage body 214 and the gap G between thepackages FIG. 3 throughFIG. 5 , and, as illustrated inFIG. 6A throughFIG. 6C , the stackingelement 530 a protrudes above theupper surface 224 of thepackage body 214 to an extent corresponding to the gap G. Also, the width WSL of thelower portion 604 can substantially correspond to the width WC of the connectingelement 218 a, which was previously described with reference toFIG. 3 andFIG. 4 . In addition, the width WSM of themiddle portion 602 can correspond to a minimum lateral extent of the stackingelement 530 a, and a ratio of the width WSM relative to the width WSU or the width WSL can correspond to an extent of inward tapering of themiddle portion 602, relative to theupper portion 600 or thelower portion 604. For certain implementations, the width WSM can be represented relative to the smaller of the width WSU and the width WSL as follows: WSM≧e×min(WSU, WSL), where e sets a lower bound on the extent of inward tapering and is less than or equal to 1. - The shape and size of the stacking
element 530 a can be controlled by suitable selection and control over the shape and size of the opening 400 a, the shapes and sizes of the connectingelements upper portion 600 and thelower portion 604 in terms of a ratio of their widths WSU and WSL, such as by selection and control over the relative sizes of the connectingelements middle portion 602, such as by selection and control over the size of the opening 400 a. In particular, because excessive inward tapering can lead to cracking, reducing the extent of inward tapering can improve structural rigidity of the stackingelement 530 a, thereby enhancing reliability and efficiency of electrical connections between thepackages - In accordance with a first implementation of
FIG. 6A , the width WSU is greater than the width WSL, such as by sizing the connectingelement 528 a to be greater than the connectingelement 218 a. More particularly, a ratio of the width WSU and the width WSL can be represented as follows: WSU=fWSL, where f is in the range of about 1.05 to about 1.7, such as from about 1.1 to about 1.6 or from about 1.2 to about 1.5. In addition, suitably sizing the opening 400 a allows accommodation of the greater sized connectingelement 528 a and control over the extent of inward tapering. In particular, the width WSM can be represented as follows: WSM≧e×min(WSU, WSL)=eWSL, where e can be, for example, about 0.8, about 0.85, or about 0.9. It is also contemplated that the width WSL can be greater than the width WSU, such as by sizing the connectingelement 218 a to be greater than the connectingelement 528 a, and that a ratio of the width WSL and the width WSU can be represented as follows: WSL=gWSU, where g is in the range of about 1.05 to about 1.7, such as from about 1.1 to about 1.6 or from about 1.2 to about 1.5. In the case that the width WSL is greater than the width WSU, the width WSL can be represented as follows: WSM≧e×min(WSU, WSL)=eWSU, where e can be, for example, about 0.8, about 0.85, or about 0.9. - In accordance with a second implementation of
FIG. 6B , the width WSU is substantially the same as the width WSL, such as by similarly sizing the connectingelements - Like the second implementation, the width WSU in accordance with a third implementation of
FIG. 6C is substantially the same as the width WSL, such as by similarly sizing the connectingelements -
FIG. 7 illustrates a cross-sectional view of a stackablesemiconductor device package 700 implemented in accordance with another embodiment of the invention. Certain aspects of thepackage 700 can be implemented in a similar fashion as previously described for thepackage 200 ofFIG. 2 throughFIG. 4 and, thus, are not further described herein. - Referring to
FIG. 7 , thepackage 700 includes multiple semiconductor devices, namely asemiconductor device 700, which is disposed adjacent to theupper surface 204 of thesubstrate unit 202, and asemiconductor device 702, which is disposed adjacent to thesemiconductor device 700. In the illustrated embodiment, thesemiconductor devices semiconductor devices package 700 achieves a higher density of semiconductor devices for a given footprint area, beyond that achieved by stacking multiple semiconductor device packages each including a single semiconductor device. While the twosemiconductor devices FIG. 7 , it is contemplated that additional semiconductor devices can be included within thepackage 700 to achieve an even higher density of semiconductor devices. - As illustrated in
FIG. 7 , thesemiconductor device 700 is wire-bonded to thesubstrate unit 202 via a set ofwires 704, and thesemiconductor device 702 is wire-bonded to thesubstrate unit 202 via a set ofwires 706 and a set ofwires 708, the latter of which electrically connect thesemiconductor device 702 to thesubstrate unit 202 via thesemiconductor device 700. Thewires wires -
FIG. 8 illustrates a cross-sectional view of a stackablesemiconductor device package 800 implemented in accordance with another embodiment of the invention. Certain aspects of thepackage 800 can be implemented in a similar fashion as previously described for thepackage 200 ofFIG. 2 throughFIG. 4 and, thus, are not further described herein. - Referring to
FIG. 8 , thepackage 800 includes asemiconductor device 800, which is a semiconductor chip that is disposed adjacent to theupper surface 204 of thesubstrate unit 202. In the illustrated embodiment, thesemiconductor device 800 is flip chip-bonded to thesubstrate unit 202 via a set ofconductive bumps 802, which are formed from solder, copper, nickel, or another suitable electrically conductive material. For certain implementations, at least a subset of theconductive bumps 802 is desirably fowled as a multi-layer bumping structure, including a copper post disposed adjacent to thesemiconductor device 800, a solder layer disposed adjacent to thesubstrate unit 202, and a nickel barrier layer disposed between the copper post and the solder layer to suppress diffusion and loss of copper. Certain aspects of such a multi-layer bumping structure is described in the co-pending and co-owned Patent Application Publication No. 2006/0094224, the disclosure of which is incorporated herein by reference in its entirety. As illustrated inFIG. 8 , thesemiconductor device 800 is secured to thesubstrate unit 202 using anunderfill material 804, which is formed from an adhesive or another suitable material, although it is contemplated that theunderfill material 804 can be omitted for other implementations. It is also contemplated that thesemiconductor device 800 can be electrically connected to thesubstrate unit 202 in another fashion, such as by wire-bonding. Moreover, while thesingle semiconductor device 800 is illustrated inFIG. 8 , it is contemplated that additional semiconductor devices can be included within thepackage 800 to achieve a higher density of semiconductor devices for a given footprint area. -
FIG. 9A throughFIG. 9G illustrate a manufacturing method of forming a stackable semiconductor device package and a stacked package assembly, according to an embodiment of the invention. For ease of presentation, the following manufacturing operations are described with reference to thepackage 200 ofFIG. 2 throughFIG. 4 and with reference to theassembly 500 ofFIG. 5 throughFIG. 6C . However, it is contemplated that the manufacturing operations can be similarly carried out to form other stackable semiconductor device packages and other stacked package assemblies, such as thepackage 700 ofFIG. 7 and thepackage 800 ofFIG. 8 . - Referring first to
FIG. 9A , asubstrate 900 is provided. To enhance manufacturing throughput, thesubstrate 900 includes multiple substrate units, including thesubstrate unit 202 and anadjacent substrate unit 202′, thereby allowing certain of the manufacturing operations to be readily performed in parallel or sequentially. Thesubstrate 900 can be implemented in a strip fashion, in which the multiple substrate units are arranged sequentially in an one-dimensional pattern, or in an array fashion, in which the multiple substrate units are arranged in a two-dimensional pattern. For ease of presentation, the following manufacturing operations are primarily described with reference to thesubstrate unit 202 and related components, although the manufacturing operations can be similarly carried for other substrate units and related components. - As illustrated in
FIG. 9A , multiple contact pads are disposed adjacent to anupper surface 902 of thesubstrate 900, and multiple contact pads are disposed adjacent to alower surface 904 of thesubstrate 900. In particular, thecontact pads upper surface 902, while thecontact pads lower surface 904. In the illustrated embodiment, conductive bumps are subsequently disposed adjacent to respective ones of thecontact pads contact pads substrate 900. Thecontact pads contact pads FIG. 9A , it is contemplated that a tape can be used to secure thelower surface 904 of thesubstrate 900 during subsequent operations. The tape can be implemented as a single-sided adhesive tape or a double-sided adhesive tape. - Once the
substrate 900 is provided, an electricallyconductive material 906 is applied to theupper surface 902 of thesubstrate 900 and disposed adjacent to thecontact pads conductive material 906 includes a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. For example, the electricallyconductive material 906 can include a solder, which can be formed from any of a number of fusible metal alloys having melting points in the range of about 90° C. to about 450° C. Examples of such fusible metal alloys include tin-lead alloys, copper-zinc alloys, copper-silver alloys, tin-silver-copper alloys, bismuth-containing alloys, indium-containing alloys, and antimony-containing alloys. As another example, the electricallyconductive material 906 can include a solid core formed from a metal, a metal alloy, or a resin, which solid core can be coated with a solder. As a further example, the electricallyconductive material 906 can include an electrically conductive adhesive, which can be formed from any of a number of resins having an electrically conductive filler dispersed therein. Examples of suitable resins include epoxy-based resins and silicone-based resins, and examples of suitable fillers include silver fillers and carbon fillers. - In the illustrated embodiment, a
dispenser 908 is laterally positioned with respect to thesubstrate 900 and is used to apply the electricallyconductive material 906. In particular, thedispenser 908 is substantially aligned with thecontact pads conductive material 906 to be selectively applied to thecontact pads single dispenser 908 is illustrated inFIG. 9A , it is contemplated that multiple dispersers can be used to further enhance manufacturing throughput. Still referring toFIG. 9A , thedispenser 908 applies the electricallyconductive material 906 in the form of conductive balls each having a substantially spherical or substantially spheroidal shape, although it is contemplated that the shapes of the conductive balls can vary for other implementations. - Once applied, the electrically
conductive material 906 is reflowed, such as by raising the temperature to near or above a melting point of the electricallyconductive material 906. As a result of gravity and other effects, the electricallyconductive material 906 is drawn downwardly towards thecontact pads FIG. 9B , thereby enhancing reliability and efficiency of electrical connections with thecontact pads conductive material 906 is hardened or solidified, such as by lowering the temperature to below the melting point of the electricallyconductive material 906. This solidification operation forms conductive bumps, which correspond to the connectingelements contact pads - Next, as illustrated in
FIG. 9C , thesemiconductor device 208 is disposed adjacent to theupper surface 902 of thesubstrate 900, and is electrically connected to thesubstrate unit 202. In particular, thesemiconductor device 208 is wire-bonded to thesubstrate unit 202 via thewires 212. It is contemplated that the ordering of operations by which the connectingelements semiconductor device 208 are disposed adjacent to thesubstrate 900 can be varied for other implementations. For example, thesemiconductor device 208 can be disposed adjacent to thesubstrate 900, and, subsequently, the electricallyconductive material 906 can be applied to thesubstrate 900 to form the connectingelements - Referring next to
FIG. 9D , amolding material 910 is applied to theupper surface 902 of thesubstrate 900 so as to substantially cover or encapsulate the connectingelements semiconductor device 208, and thewires 212. In particular, themolding material 910 is applied across substantially an entire area of theupper surface 902, thereby providing improved structural rigidity and avoiding or reducing issues related to overflowing and contamination for a conventional implementation. Also, manufacturing cost is reduced by simplifying molding operations as well as reducing the number of those molding operations. Themolding material 910 can include, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers also can be included, such as powdered SiO2. Themolding material 910 can be applied using any of a number of molding techniques, such as compression molding, injection molding, and transfer molding. Once applied, themolding material 910 is hardened or solidified, such as by lowering the temperature to below a melting point of themolding material 910, thereby forming a moldedstructure 912. To facilitate proper positioning of thesubstrate 900 during subsequent operations, fiducial marks can be formed in the moldedstructure 912, such as using laser marking. Alternatively, or in conjunction, fiducial marks can be formed adjacent to a periphery of thesubstrate 900. - Laser ablation or drilling is next carried out with respect to an
upper surface 914 of the moldedstructure 912. Referring toFIG. 9E , laser ablation is carried out using alaser 916, which applies a laser beam or another form of optical energy to remove portions of the moldedstructure 912. In particular, thelaser 916 is laterally positioned and substantially aligned with each connectingelement depressions elements laser 916 during laser ablation can be aided by fiducial marks, which allow proper positioning of thelaser 916 when forming thedepressions - The
laser 916 can be implemented in a number of ways, such as a green laser, an infrared laser, a solid-state laser, or a CO2 laser. Thelaser 916 can be implemented as a pulsed laser or a continuous wave laser. Suitable selection and control over operating parameters of thelaser 916 allow control over sizes and shapes of thedepressions openings laser 916 can be selected in accordance with a particular composition of the moldedstructure 912, and, for some implementations, the peak output wavelength can be in the visible range or the infrared range. Also, an operating power of thelaser 916 can be in the range of about 3 Watts (“W”) to about 20 W, such as from about 3 W to about 15 W or from about 3 W to about 10 W. In the case of a pulsed laser implementation, a pulse frequency and a pulse duration are additional examples of operating parameters that can be suitably selected and controlled. While thesingle laser 916 is illustrated inFIG. 9E , it is contemplated that multiple lasers can be used to further enhance manufacturing throughput. Also, it is contemplated that another suitable technique can be used in place of, or in conjunction with, laser ablation, such as chemical etching or mechanical drilling. - As a result of laser ablation, exposed connection surfaces of the connecting
elements - Next, as illustrated in
FIG. 9F , singulation is carried out with respect to theupper surface 914 of the moldedstructure 912. Such manner of singulation can be referred as “front-side” singulation. However, it is contemplated that singulation can be carried out with respect to thelower surface 904 of thesubstrate 900, and can be referred as “back-side” singulation. Referring toFIG. 9F , the “front-side” singulation is carried out using asaw 920, which forms cutting slits, including acutting slit 922. In particular, the cutting slits extend downwardly and completely through thesubstrate 900 and the moldedstructure 912, thereby sub-dividing thesubstrate 900 and the moldedstructure 912 into discrete units, including thesubstrate unit 202 and thepackage body 214. In such manner, thepackage 200 is formed. The alignment of thesaw 920 during the “front-side” singulation can be aided by fiducial marks, which allow proper positioning of thesaw 920 when forming the cutting slits. - Still referring to
FIG. 9F , the connectingelements lower surface 206 of thesubstrate unit 202. The connectingelements elements elements lower surface 206 of thesubstrate unit 202 prior to or subsequent to the “front-side” singulation. - Stacking is next carried out with respect to the
package 502 to form theassembly 500, as illustrated inFIG. 5 andFIG. 9G . In particular, thepackage 502 is positioned with respect to thepackage 200, such that the connectingelements package 502 are substantially aligned with and adjacent to respective ones of the connectingelements package 200. Once thepackages elements elements elements - While the invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. In particular, while the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.
Claims (21)
1.-20. (canceled)
21. A semiconductor package, comprising:
a substrate including an upper surface;
a plurality of connecting elements disposed adjacent to a periphery of the substrate and extending upwardly from the upper surface of the substrate;
a package body disposed adjacent to the upper surface of the substrate; and
a plurality of openings in the package body, the openings at least partially exposing respective ones of the connecting elements, at least one of the openings having a width WU adjacent to an upper surface of the package body, such that WU is in the range of about 250 μm to about 650 μm.
22. The semiconductor package of claim 21 , wherein at least one of the connecting elements has a height HC, such that HC is in the range of about 300 μm to about 350 μm prior to reflow.
23. The semiconductor package of claim 21 , wherein at least one of the connecting elements has a height HC, such that HC is in the range of about 200 μm to about 300 μm after reflow.
24. The semiconductor package of claim 21 , wherein the package body has a height HP, such that HP is in the range of about 100 μm to about 600 μm.
25. The semiconductor package of claim 24 , wherein WU>HP.
26. The semiconductor package of claim 21 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm.
27. The semiconductor package of claim 21 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package.
28. A semiconductor package, comprising:
a substrate including an upper surface;
a plurality of connecting elements disposed on the upper surface of the substrate;
a package body disposed on the upper surface of the substrate; and
a plurality of conical openings in the package body, the conical openings exposing respective portions of the connecting elements, at least one of the conical openings having a maximum diameter in the range of about 250 μm to about 650 μm.
29. The semiconductor package of claim 28 , wherein at least one of the connecting elements has a height HC, such that HC is in the range of about 300 μm to about 350 μm prior to reflow.
30. The semiconductor package of claim 28 , wherein at least one of the connecting elements has a height HC, such that HC is in the range of about 200 μm to about 300 μm after reflow.
31. The semiconductor package of claim 28 , wherein the package body has a height HP, such that HP is in the range of about 100 μm to about 600 μm.
32. The semiconductor package of claim 31 , wherein the maximum diameter of the at least one of the openings is greater than HP.
33. The semiconductor package of claim 28 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm.
34. The semiconductor package of claim 28 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package.
35. A semiconductor package, comprising:
a substrate including an upper surface;
a plurality of connecting elements disposed on the upper surface of the substrate;
a package body disposed on the upper surface of the substrate wherein the package body has a thickness HP; and
a plurality of openings in the package body, each of the openings exposing a respective portion of the connecting elements, wherein a maximum width of each of the openings is greater than the thickness H.
36. The semiconductor package of claim 35 , wherein at least one of the connecting elements has a height that is in the range of about 300 μm to about 350 μm prior to reflow.
37. The semiconductor package of claim 35 , wherein at least one of the connecting elements has a height that is in the range of about 200 μm to about 300 μm after reflow.
38. The semiconductor package of claim 35 , wherein HP is in the range of about 100 μm to about 600 μm.
39. The semiconductor package of claim 35 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm.
40. The semiconductor package of claim 35 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package.
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Also Published As
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US8076765B2 (en) | 2011-12-13 |
TWI499024B (en) | 2015-09-01 |
TW201027693A (en) | 2010-07-16 |
US20100171205A1 (en) | 2010-07-08 |
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