US20090190605A1 - Dynamic color threshold in a queue - Google Patents

Dynamic color threshold in a queue Download PDF

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US20090190605A1
US20090190605A1 US12/415,420 US41542009A US2009190605A1 US 20090190605 A1 US20090190605 A1 US 20090190605A1 US 41542009 A US41542009 A US 41542009A US 2009190605 A1 US2009190605 A1 US 2009190605A1
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queues
memory
buffers
packets
queue
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Erik Andersen
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Avago Technologies International Sales Pte Ltd
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Broadcom Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/50Queue scheduling

Definitions

  • the present invention relates to a network device in a packet switched network and more particularly to a method of dynamically allocating color thresholds in a queue to ensure that packets associated with each color are processed in proportion to thresholds defined for other colors.
  • a packet switched network may include one or more network devices, such as a Ethernet switching chip, each of which includes several modules that are used to process information that is transmitted through the device.
  • the device includes an ingress module, a Memory Management Unit (MMU) and an egress module.
  • the ingress module includes switching functionality for determining to which destination port a packet should be directed.
  • the MMU is used for storing packet information and performing resource checks.
  • the egress module is used for performing packet modification and for transmitting the packet to at least one appropriate destination port.
  • One of the ports on the device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
  • packets enter the device from multiple ports they are forwarded to the ingress module where switching and other processing are performed on the packets. Thereafter, the packets are transmitted to one or more destination ports through the MMU and the egress module.
  • the MMU enables sharing of packet buffer among different ports while providing resource guarantees for every ingress port, egress port and class of service queue.
  • packets may be colored based on metering and
  • the MMU acts on these packets differently depending on the color of the packet.
  • eight class of service queues are associated with each egress port. To ensure bandwidth guarantees across the ports and queues, the device assigns a fixed portion of the bandwidth for the port to each queue and shares unassigned bandwidth between queues that have used their allocated amount. However, the unassigned bandwidth provides a dynamic ceiling for each queue. As such, it is impossible to dynamically process packets in each queue according to predefined proportions assigned to each color.
  • a network device for dynamically allocating memory locations to plurality of queues.
  • the network device includes means for determining an amount of memory buffers that is associated with a port, for assigning a fixed allocation of memory buffers to each of a plurality of queues associated with the port and for sharing remaining memory buffers among the plurality of queues. The remaining memory buffers are used by each of the plurality of queues after the fixed allocation of memory buffers assigned to the queue is used.
  • the network device also includes means for setting a limit threshold for each of the plurality of queues. The limit threshold determines how much of the remaining memory buffer may be used by each of the plurality of queues.
  • the network device further includes means for defining at least one color threshold for packets including a specified color marking and for defining a virtual maximum threshold.
  • the virtual maximum threshold is defined for the queue.
  • the virtual maximum threshold replaces the limit threshold and packets associated with the at least one color threshold are processed in proportion with other color thresholds based on the virtual maximum threshold ceiling.
  • a method for dynamically allocating memory locations to plurality of queues includes the steps of determining an amount of memory buffers that is associated with a port, assigning a fixed allocation of memory buffers to each of a plurality of queues associated with the port and sharing remaining memory buffers among the plurality of queues.
  • the method also includes the steps of setting a limit threshold for each of the plurality of queues and defining at least one color threshold for packets including a specified color marking.
  • the method further includes the steps of accepting a request from one of the plurality of queues to access the remaining memory buffers when the remaining memory buffers is less than the limit threshold for the queue and defining a virtual maximum threshold for the queue, wherein the virtual maximum threshold replaces the limit threshold and packets associated with the at least one color threshold are processed in proportion with other color thresholds based on the virtual maximum threshold ceiling.
  • FIG. 1 illustrates a network device in which an embodiment of the present invention may be implemented
  • FIG. 2 a illustrates the shared memory architecture of the present invention
  • FIG. 2 b illustrates the Cell Buffer Pool of the shared memory architecture
  • FIG. 3 illustrates buffer management mechanisms that are used by the memory management unit to impose resource allocation limitations and thereby ensure fair access to resource;
  • FIG. 4 illustrates a configuration of an egress port arbitration implemented in the present invention
  • FIG. 5 illustrates the implementation of the minimum and maximum bandwidth metering mechanisms
  • FIG. 6 illustrates an embodiment in which four queues are serviced according to their minimum bandwidth specifications.
  • FIG. 1 illustrates a network device, such as a switching chip, in which an embodiment the present invention may be implemented.
  • Device 100 includes an ingress module 102 , a MMU 104 , and an egress module 106 .
  • Ingress module 102 is used for performing switching functionality on an incoming packet.
  • MMU 104 The primary function of MMU 104 is to efficiently manage cell buffering and packet pointer resources in a predictable manner even under severe congestion scenarios.
  • Egress module 106 is used for performing packet modification and transmitting the packet to an appropriate destination port.
  • Device 100 may also include one internal fabric high speed port, for example a HiGig port, 108 , one or more external Ethernet ports 109 a - 109 x , and a CPU port 110 .
  • High speed port 108 is used to interconnect various network devices in a system and thus form an internal switching fabric for transporting packets between external source ports and one or more external destination ports. As such, high speed port 108 is not externally visible outside of a system that includes multiple interconnected network devices.
  • CPU port 110 is used to send and receive packets to and from external switching/routing control entities or CPUs. According to an embodiment of the invention, CPU port 110 may be considered as one of external Ethernet ports 109 a - 109 x .
  • Device 100 interfaces with external/off-chip CPUs through a CPU processing module 111 , such as a CMIC, which interfaces with a PCI bus that connects device 100 to an external CPU.
  • a CPU processing module 111 such as a CMIC, which interfaces with a PCI bus that
  • traffic in device 100 is routed from an external Ethernet source port to one or more unique destination Ethernet ports.
  • device 100 supports twelve physical Ethernet ports 109 , each of which can operate in 10/100/1000 Mbps speed and one high speed port 108 which operates in either 10 Gbps or 12 Gbps speed.
  • device 100 is built around a shared memory architecture, as shown in FIGS. 2 a - 2 b wherein MMU 104 enables sharing of a packet buffer among different ports while providing for resource guarantees for every ingress port, egress port and class of service queue associated with each egress port.
  • FIG. 2 a illustrates the shared memory architecture of the present invention.
  • the memory resources of device 100 include a Cell Buffer Pool (CBP) memory 202 and a Transaction Queue (XQ) memory 204 .
  • CBP memory 202 is an off-chip resource that is made of 4 DRAM chips 206 a - 206 d .
  • each DRAM chip has a capacity of 288 Mbits, wherein the total capacity of CBP memory 202 is 122 Mbytes of raw storage.
  • CBP memory 202 is divided into 256K 576-byte cells 208 a - 208 x , each of which includes a 32 byte header buffer 210 , up to 512 bytes for packet data 212 and 32 bytes of reserved space 214 .
  • each incoming packet consumes at least one full 576 byte cell 208 . Therefore in an example where an incoming includes a 64 byte frame, the incoming packet will have 576 bytes reserved for it even though only 64 bytes of the 576 bytes is used by the frame.
  • XQ memory 204 includes a list of packet pointers 216 a - 216 x into CBP memory 202 , wherein different XQ pointers 216 may be associated with each port.
  • a cell count of CBP memory 202 and a packet count of XQ memory 204 is tracked on an ingress port, egress port and class of service basis. As such, device 100 can provide resource guarantees on a cell and/or packet basis.
  • FIG. 3 illustrates buffer management mechanisms that are used by MMU 104 to impose resource allocation limitations and thereby ensure fair access to resources.
  • MMU 104 includes an ingress backpressure (IB) mechanism 304 , a head of line (HOL) mechanism 306 and a weighted random early detection (WRED) mechanism 308 .
  • IB ingress backpressure
  • HOL head of line
  • WRED weighted random early detection
  • Ingress backpressure mechanism 304 supports lossless behaviour and manages buffer resources fairly across ingress ports.
  • Head of line mechanism 306 supports access to buffering resources while optimizing throughput in the system.
  • Weighted random early detection mechanism 308 improves overall network throughput.
  • Ingress backpressure mechanism 304 uses packet or cell counters to track the number of packets or cells used on an ingress port basis.
  • Ingress backpressure mechanism 304 includes registers for a set of 8 individually configurable thresholds and registers used to specify which of the 8 thresholds are to be used for every ingress port in the system.
  • the set of thresholds include a limit threshold 312 , a discard limit threshold 314 and a reset limit threshold 316 . If a counter associated with the ingress port packet/cell usage rises above discard limit threshold 314 , packets at the ingress port will be dropped.
  • a pause flow control is used to stop traffic from arriving on an ingress port that have used more than its fair share of buffering resources, thereby stopping traffic from an offending ingress port and relieving congestion caused by the offending ingress port.
  • each ingress port keeps track of whether or not it is in an ingress backpressure state based on ingress backpressure counters relative to the set of thresholds.
  • pause flow control frames with a timer value of (0xFFFF) are periodically sent out of that ingress port.
  • the pause flow control frame with a timer value of 0x00 is sent out of the ingress port and traffic is allowed to flow again. If an ingress port is not currently in an ingress backpressure state and the packet counter rises above limit threshold 312 , the status for the ingress port transitions into the ingress backpressure state. If the ingress port is in the ingress backpressure state and the packet counter falls below reset limit threshold 316 , the status for the port will transition out of the backpressure state.
  • Head of line mechanism 306 is provided to support fair access to buffering resources while optimizing throughput in the system. Head of line mechanism 306 relies on packet dropping to manage buffering resources and improve the overall system throughput. According to an embodiment of the invention, head of line mechanism 306 uses egress counters and predefined thresholds to track buffer usage on a egress port and class of service basis and thereafter makes decisions to drop any newly arriving packets on the ingress ports destined to a particular oversubscribed egress port/class of service queue. Head of line mechanism 306 supports different thresholds depending on the color of the newly arriving packet. Packets may be colored based on metering and marking operations that take place in the ingress module and the MMU acts on these packets differently depending on the color of the packet.
  • head of line mechanism 306 is configurable and operates independently on every class of service queue and across all ports, including the CPU port.
  • Head of line mechanism 306 uses counters that track XQ memory 204 and CBP memory 202 usage and thresholds that are designed to support a static allocation of CBP memory buffers 202 and dynamic allocation of the available XQ memory buffers 204 .
  • a discard threshold 322 is defined for all cells in CBP memory 202 , regardless of color marking. When the cell counter associated with a port reaches discard threshold 322 , the port is transition to a head of line status. Thereafter, the port may transition out of the head of line status if its cell counter falls below a reset limit threshold 324 .
  • a guaranteed fixed allocation of XQ buffers for each class of service queue is defined by a XQ entry value 330 a - 330 h .
  • Each of XQ entry value 330 a - 330 h defines how many buffer entries should be reserved for an associated queue. For example, if 100 bytes of XQ memory are assigned to a port, the first four class of service queues associated with XQ entries 330 a - 330 d respectively may be assigned the value of 10 bytes and the last four queues associated with XQ entries 330 d - 330 h respectively may be assigned the value of 5 bytes.
  • head of line mechanism 306 may not assign the unused buffer to another queue. Nevertheless, the remaining unassigned 40 bytes of XQ buffers for the port may be shared among all of the class of service queues associated with the port. Limits on how much of the shared pool of the XQ buffer may be consumed by a particular class of service queue is set with a XQ set limit threshold 332 . As such, set limit threshold 332 may be used to define the maximum number of buffers that can be used by one queue and to prevent one queue from using all of the available XQ buffers.
  • the available pool of XQ buffer for each port is tracked using a port dynamic count register 334 , wherein dynamic count register 334 keeps track of the number of available shared XQ buffers for the port.
  • the initial value of dynamic count register 334 is the total number of XQ buffers associated with the port minus a sum of the number of XQ entry values 320 a - 320 h .
  • Dynamic count register 334 is decremented when a class of service queue uses an available XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value 330 . Conversely, dynamic count register 334 is incremented when a class of service queue releases a XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value 330 .
  • head of line mechanism 306 determines if all entries used by the queue is less than the XQ entry value 330 for the queue and grants the buffer request if the used entries are less then the XQ entry value 330 . If however, the used entries are greater than the XQ entry value 330 for the queue, head of line mechanism 306 determines if the amount requested is less than the total available buffer or less then the maximum amount set for the queue by the associated set limit threshold 332 .
  • Set limit threshold 332 is in essence a discard threshold that is associated with the queue, regardless of the color marking of the packet. As such, when the packet count associated with the packet reaches set limit threshold 332 , the queue/port enters into a head of line status.
  • head of line mechanism 306 When head of line mechanism 306 detects a head of line condition, it sends an update status so that ingress module 102 can drop packets on the congested port. However, due to latency, there may be packets in transition between ingress module 102 and MMU 104 when the status update is sent by head of line mechanism 306 . In this case, the packet drops may occur at MMU 104 due to the head of line status. In an embodiment of the invention, due to the pipeline of packets between ingress module 102 and MMU 104 , the dynamic pool of XQ pointers is reduced by a predefined amount.
  • the port is transition to the head of line status and an update status is sent to by MMU 104 to ingress module 102 , thereby reducing the number of packets that may be dropped by MMU 104 .
  • the XQ packet count for the queue must fall below a reset limit (RL) threshold 336 .
  • intermediate discard thresholds 338 and 339 may also be defined for packets containing specific color markings, wherein each intermediate discard threshold defines when packets of a particular color should be dropped.
  • intermediate discard threshold 338 may be used to define when packets that are colored yellow should be dropped and intermediate discard threshold 339 may be used to define when packets that are colored red should be dropped.
  • packets may be colored one of green, yellow or red depending on the priority level assigned to the packet.
  • one embodiment of the present invention includes a virtual maximum (VM) threshold 340 .
  • Virtual maximum threshold 340 is equal to the number of unassigned and available buffers divided by the sum of the number of queues, wherein the quotient is added to the number of currently used buffers. Virtual maximum threshold 340 ensures that the packets associated with each color are processed in a relative proportion.
  • head of line mechanism 306 calculates the virtual maximum threshold 340 for the queue and processes a proportional amount of packets associated with each color relative to the defined ratios for each color.
  • the XQ thresholds may be expressed in a compressed form, wherein each unit represents a group of XQ entries.
  • the group size is dependent upon the number of XQ buffers that are associated with a particular egress port/class of service queue.
  • Weighted random early detection mechanism 308 is a queue management mechanism that preemptively drops packets based on a probabilistic algorithm before XQ buffers 204 are exhausted. Weighted random early detection mechanism 308 is therefore used to optimize the overall network throughput. Weighted random early detection mechanism 308 includes an averaging statistic that is used to track each queue length and drop packets based on a drop profile defined for the queue. The drop profile defines a drop probability given a specific average queue size. According to an embodiment of the invention, weighted random early detection mechanism 308 may defined separate profiles on based on a class of service queue and packet.
  • FIG. 4 illustrates a configuration of an egress port arbitration implemented in the present invention.
  • MMU 104 also includes a scheduler 402 that provides arbitration across the eight class of service (COS) queues 404 a - 404 h associated with each egress port to provide minimum and maximum bandwidth guarantees.
  • Scheduler 402 is integrated with a set of minimum and maximum metering mechanisms 406 a - 406 i that monitor traffic flows on a class of service basis and an overall egress port 109 basis.
  • Metering mechanisms 406 a - 406 i support traffic shaping functions and guarantee minimum bandwidth specifications on a class of service queue and/or egress port basis, wherein scheduling decisions by schedule 402 are configured largely via traffic shaping mechanisms 406 a - 406 h along with a set of control masks that modify how scheduler 402 uses traffic shaping mechanisms 406 a - 406 h.
  • minimum and maximum metering mechanisms 406 a - 406 i monitor traffic flows on a class of service queue basis and an overall egress port basis.
  • Maximum and minimum bandwidth meters 406 a - 406 h are used to feed state information to scheduler 402 which responds by modifying its service order across class of service queues 404 .
  • the inventive device 100 therefore enables system vendors to implement a quality of service model by configuring class of service queues 404 to support an explicit minimum and maximum bandwidth guarantee.
  • metering mechanisms 406 a - 406 h monitor traffic flow on a class of service queue basis, provides state information regarding whether or nor a class of service flow is above or below a specified minimum and maximum bandwidth specification, and transmits the information into scheduler 402 which uses the metering information to modify its scheduling decisions.
  • metering mechanisms 406 a - 406 h aid in partitioning class of service queues 404 into a set of queues that have not met the minimum bandwidth specification, a set that have met its minimum bandwidth but not its maximum bandwidth specification and a set that have exceeded its maximum bandwidth specification. If a queue is in the set that have not met its minimum bandwidth specification and there are packets in the queue, scheduler 402 services the queue according to the configured scheduling discipline.
  • scheduler 402 services the queue according to the configured scheduling discipline. If a queue is in the set that have exceeded its maximum bandwidth specification or if the queue is empty, scheduler 402 does not service the queue.
  • minimum and maximum bandwidth metering mechanisms 406 a - 406 h are implemented using a simple leaky bucket mechanism which tracks whether or not a class of service queue 404 has consumed its minimum or maximum bandwidth.
  • the range of the minimum and maximum bandwidth setting for each class of service 404 is between 64 kbps to 16 Gbps, in 64 kbps increments.
  • the leaky bucket mechanism has a configurable number of tokens “leaking” out of bucket 502 a - 502 h , each of which is associated with one of queues 404 a - 404 h , at a configurable rate.
  • the leaky bucket mechanism includes a refresh update interface and a minimum bandwidth 506 which defines how many tokens are to be removed every refresh time unit.
  • a minimum threshold 508 is set to indicate whether a flow has satisfied at least its minimum rate and a fill threshold 510 is set to indicate how many tokens are in leaky bucket 502 .
  • fill threshold 510 rises above minimum threshold 508 , a flag which indicates that the flow has satisfied its minimum bandwidth specification is set to true.
  • fill threshold 510 falls below minimum threshold 508 , the flag is set to false.
  • Minimum threshold 508 affects what timescale the minimum bandwidth metering mechanism 406 is required to operate. If the minimum threshold 508 is set at a very low level, class of service queue 404 will quickly flag that its minimum bandwidth has been met. This reduces the amount of time queue 404 is classified in the set of queues that have not met the minimum bandwidth requirement and reduces the time period that the queue is given preferential treatment from scheduler 402 .
  • High threshold 504 affects how much credit can be built up after a class of service queue meets it minimum bandwidth 506 . A large high threshold 504 may result in a reduction of time that the queue is classified with the set of queues that have not met the minimum bandwidth requirement and reduces the time period that the queue is given preferential treatment from scheduler 402 .
  • metering mechanisms 406 a - 406 h indicate that the maximum bandwidth specified has been exceeded high threshold 504 , scheduler 402 ceases to service the queue and the queue is classified as being in the set of queues that have exceeded it maximum bandwidth specification. A flag is then set to indicate that the queue has exceeded its maximum bandwidth. Thereafter, the queue will only receive service from scheduler 402 when its fill threshold 510 falls below high threshold 504 and the flag indicating that it has exceeded its maximum bandwidth is reset.
  • Metering mechanism 406 i is used to indicate that the maximum bandwidth specified for a port has been exceeded and operates in the same manner as meter mechanisms 406 a - 406 h when the maximum bandwidth has been exceeded.
  • the maximum metering mechanism on a queue and port basis generally affects whether or not queue 404 or a port is to be included in scheduling arbitration. As such, the maximum metering mechanism only has a traffic limiting effect on scheduler 402 .
  • scheduler 402 is configured to support a variety of scheduling disciplines that mimic the bandwidth sharing capabilities of a weighted fair queuing scheme.
  • the weighted fair queue scheme is a weighted version of packet based fair queuing scheme, which is defined as a method for providing “bit-based round robin” scheduling of packets. As such, packets are scheduled for access to an egress port based on their delivery time, which is computed as if the scheduler is capable of providing bit-based round robin service.
  • a relative weight field influences the specifics of how the scheduler makes use of the minimum metering mechanism, wherein the scheduler attempts to provide a minimum bandwidth guarantee.
  • the minimum bandwidth guarantee is a relative bandwidth guarantee wherein a relative field determines whether or not scheduler 402 will treat the minimum bandwidth metering settings as a specification for a relative or an absolute bandwidth guarantee. If the relative field is set, the scheduler treats minimum bandwidth 506 setting as a relative bandwidth specification. Scheduler 402 then attempts to provide relative bandwidth sharing across backlogged queues 404 .
  • FIG. 6 illustrates an embodiment in which four queues are serviced according to their minimum bandwidth specifications.
  • a 1 GE egress port has scheduler 402 configured to be in a weighted fair queue mode and has its relative field set to true, wherein the minimum bandwidth for queue 602 a and 602 b is 10 Mbps, for queue 602 c is 20 Mbps and for queue 602 d is 40 Mbps. If all queues 602 have packets to be serviced, then scheduler 402 will provide relative bandwidth sharing across the active queues according to the predefined minimum bandwidth for each queue.
  • queue 602 d will receive twice the bandwidth of queue 602 c which receives twice the bandwidth that is given to queues 602 a and 602 b . If queues 602 a - 602 d have enough packets to keep the 1 GE link fully utilized, queue 602 d will be allowed to process 500 Mbps, queue 602 c will be allowed to process 250 Mbps and queues 602 a and 602 b will be allowed to process 125 Mbps.
  • bandwidth distribution will change to appropriately provide relative bandwidth sharing, wherein queue 602 d will be allowed to process 571.4 Mbps, queue 602 c will be allowed to process 265.7 Mbps and queue 602 b will be allowed to process 142.9 Mbps.
  • minimum bandwidth metering mechanisms 406 are constantly being adjusted to achieve the relative bandwidth sharing.
  • a relative threshold 514 is also set in each of queues 404 .
  • Relative threshold 514 is used to indicate that the minimum bandwidth 506 is set too low when fill threshold 510 of all queues have exceeded relative threshold 514 .
  • device 100 calculates a new minimum bandwidth 506 , wherein:
  • the new minimum bandwidth therefore allows device 100 to leak more tokens out of bucket 502 for each of queues 404 a - 404 h , wherein the new leak is proportional to the old leak.
  • the new minimum bandwidth may be calculated for an individual queue when fill threshold for that queue rises above relative threshold 514 for that queue.

Abstract

A network device for dynamically allocating memory locations to plurality of queues. The network device includes means for determining an amount of memory buffers that is associated with a port, for assigning a fixed allocation of memory buffers to each of a plurality of queues associated with the port and for sharing remaining memory buffers among the plurality of queues. The remaining memory buffers are used by each of the plurality of queues after the fixed allocation of memory buffers assigned to the queue is used. The network device also includes means for setting a limit threshold for each of the plurality of queues. The limit threshold determines how much of the remaining memory buffer may be used by each of the plurality of queues. The network device further includes means for defining at least one color threshold for packets including a specified color marking and for defining a virtual maximum threshold. When one of the plurality of queues requests access to the remaining memory buffers and the remaining memory buffers is less than the limit threshold for the queue, the virtual maximum threshold is defined for the queue. The virtual maximum threshold replaces the limit threshold and packets associated with the at least one color threshold are processed in proportion with other color thresholds based on the virtual maximum threshold ceiling.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation of, and claims priority under 35 U.S.C. §120 to, application Ser. No. 11/060,490, titled DYNAMIC COLOR THRESHOLD IN A QUEUE, and filed on Feb. 18, 2005, which is incorporated herein by reference in its entirety.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a network device in a packet switched network and more particularly to a method of dynamically allocating color thresholds in a queue to ensure that packets associated with each color are processed in proportion to thresholds defined for other colors.
  • 2. Description of the Related Art
  • A packet switched network may include one or more network devices, such as a Ethernet switching chip, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device includes an ingress module, a Memory Management Unit (MMU) and an egress module. The ingress module includes switching functionality for determining to which destination port a packet should be directed. The MMU is used for storing packet information and performing resource checks. The egress module is used for performing packet modification and for transmitting the packet to at least one appropriate destination port. One of the ports on the device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
  • As packets enter the device from multiple ports, they are forwarded to the ingress module where switching and other processing are performed on the packets. Thereafter, the packets are transmitted to one or more destination ports through the MMU and the egress module. The MMU enables sharing of packet buffer among different ports while providing resource guarantees for every ingress port, egress port and class of service queue. According to a current switching system architecture, packets may be colored based on metering and
  • marking operations that take place in the ingress module and the MMU acts on these packets differently depending on the color of the packet. In a current device, eight class of service queues are associated with each egress port. To ensure bandwidth guarantees across the ports and queues, the device assigns a fixed portion of the bandwidth for the port to each queue and shares unassigned bandwidth between queues that have used their allocated amount. However, the unassigned bandwidth provides a dynamic ceiling for each queue. As such, it is impossible to dynamically process packets in each queue according to predefined proportions assigned to each color.
  • SUMMARY OF THE INVENTION
  • According to one aspect of the invention, there is provided a network device for dynamically allocating memory locations to plurality of queues. The network device includes means for determining an amount of memory buffers that is associated with a port, for assigning a fixed allocation of memory buffers to each of a plurality of queues associated with the port and for sharing remaining memory buffers among the plurality of queues. The remaining memory buffers are used by each of the plurality of queues after the fixed allocation of memory buffers assigned to the queue is used. The network device also includes means for setting a limit threshold for each of the plurality of queues. The limit threshold determines how much of the remaining memory buffer may be used by each of the plurality of queues. The network device further includes means for defining at least one color threshold for packets including a specified color marking and for defining a virtual maximum threshold. When one of the plurality of queues requests access to the remaining memory buffers and the remaining memory buffers is less than the limit threshold for the queue, the virtual maximum threshold is defined for the queue. The virtual maximum threshold replaces the limit threshold and packets associated with the at least one color threshold are processed in proportion with other color thresholds based on the virtual maximum threshold ceiling.
  • According to another aspect of the invention, there is provided a method for dynamically allocating memory locations to plurality of queues. The method includes the steps of determining an amount of memory buffers that is associated with a port, assigning a fixed allocation of memory buffers to each of a plurality of queues associated with the port and sharing remaining memory buffers among the plurality of queues. The method also includes the steps of setting a limit threshold for each of the plurality of queues and defining at least one color threshold for packets including a specified color marking. The method further includes the steps of accepting a request from one of the plurality of queues to access the remaining memory buffers when the remaining memory buffers is less than the limit threshold for the queue and defining a virtual maximum threshold for the queue, wherein the virtual maximum threshold replaces the limit threshold and packets associated with the at least one color threshold are processed in proportion with other color thresholds based on the virtual maximum threshold ceiling.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention that together with the description serve to explain the principles of the invention, wherein:
  • FIG. 1 illustrates a network device in which an embodiment of the present invention may be implemented;
  • FIG. 2 a illustrates the shared memory architecture of the present invention;
  • FIG. 2 b illustrates the Cell Buffer Pool of the shared memory architecture;
  • FIG. 3 illustrates buffer management mechanisms that are used by the memory management unit to impose resource allocation limitations and thereby ensure fair access to resource;
  • FIG. 4 illustrates a configuration of an egress port arbitration implemented in the present invention;
  • FIG. 5 illustrates the implementation of the minimum and maximum bandwidth metering mechanisms; and
  • FIG. 6 illustrates an embodiment in which four queues are serviced according to their minimum bandwidth specifications.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Reference will now be made to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
  • FIG. 1 illustrates a network device, such as a switching chip, in which an embodiment the present invention may be implemented. Device 100 includes an ingress module 102, a MMU 104, and an egress module 106. Ingress module 102 is used for performing switching functionality on an incoming packet. The primary function of MMU 104 is to efficiently manage cell buffering and packet pointer resources in a predictable manner even under severe congestion scenarios. Egress module 106 is used for performing packet modification and transmitting the packet to an appropriate destination port.
  • Device 100 may also include one internal fabric high speed port, for example a HiGig port, 108, one or more external Ethernet ports 109 a-109 x, and a CPU port 110. High speed port 108 is used to interconnect various network devices in a system and thus form an internal switching fabric for transporting packets between external source ports and one or more external destination ports. As such, high speed port 108 is not externally visible outside of a system that includes multiple interconnected network devices. CPU port 110 is used to send and receive packets to and from external switching/routing control entities or CPUs. According to an embodiment of the invention, CPU port 110 may be considered as one of external Ethernet ports 109 a-109 x. Device 100 interfaces with external/off-chip CPUs through a CPU processing module 111, such as a CMIC, which interfaces with a PCI bus that connects device 100 to an external CPU.
  • Network traffic enters and exits device 100 through external Ethernet ports 109 a-109 x. Specifically, traffic in device 100 is routed from an external Ethernet source port to one or more unique destination Ethernet ports. In one embodiment of the invention, device 100 supports twelve physical Ethernet ports 109, each of which can operate in 10/100/1000 Mbps speed and one high speed port 108 which operates in either 10 Gbps or 12 Gbps speed.
  • In an embodiment of the invention, device 100 is built around a shared memory architecture, as shown in FIGS. 2 a-2 b wherein MMU 104 enables sharing of a packet buffer among different ports while providing for resource guarantees for every ingress port, egress port and class of service queue associated with each egress port. FIG. 2 a illustrates the shared memory architecture of the present invention. Specifically, the memory resources of device 100 include a Cell Buffer Pool (CBP) memory 202 and a Transaction Queue (XQ) memory 204. CBP memory 202 is an off-chip resource that is made of 4 DRAM chips 206 a-206 d. According to an embodiment of the invention, each DRAM chip has a capacity of 288 Mbits, wherein the total capacity of CBP memory 202 is 122 Mbytes of raw storage. As shown in FIG. 2 b, CBP memory 202 is divided into 256K 576-byte cells 208 a-208 x, each of which includes a 32 byte header buffer 210, up to 512 bytes for packet data 212 and 32 bytes of reserved space 214. As such, each incoming packet consumes at least one full 576 byte cell 208. Therefore in an example where an incoming includes a 64 byte frame, the incoming packet will have 576 bytes reserved for it even though only 64 bytes of the 576 bytes is used by the frame.
  • Returning to FIG. 2 a, XQ memory 204 includes a list of packet pointers 216 a-216 x into CBP memory 202, wherein different XQ pointers 216 may be associated with each port. A cell count of CBP memory 202 and a packet count of XQ memory 204 is tracked on an ingress port, egress port and class of service basis. As such, device 100 can provide resource guarantees on a cell and/or packet basis.
  • Once a packet enters device 100 on a source port 109, the packet is transmitted to ingress module 102 for processing. During processing, packets on each of the ingress and egress ports share system resources 202 and 204. FIG. 3 illustrates buffer management mechanisms that are used by MMU 104 to impose resource allocation limitations and thereby ensure fair access to resources. MMU 104 includes an ingress backpressure (IB) mechanism 304, a head of line (HOL) mechanism 306 and a weighted random early detection (WRED) mechanism 308. Ingress backpressure mechanism 304 supports lossless behaviour and manages buffer resources fairly across ingress ports. Head of line mechanism 306 supports access to buffering resources while optimizing throughput in the system. Weighted random early detection mechanism 308 improves overall network throughput.
  • Ingress backpressure mechanism 304 uses packet or cell counters to track the number of packets or cells used on an ingress port basis. Ingress backpressure mechanism 304 includes registers for a set of 8 individually configurable thresholds and registers used to specify which of the 8 thresholds are to be used for every ingress port in the system. The set of thresholds include a limit threshold 312, a discard limit threshold 314 and a reset limit threshold 316. If a counter associated with the ingress port packet/cell usage rises above discard limit threshold 314, packets at the ingress port will be dropped. Based on the counters for tracking the number of cells/packets, a pause flow control is used to stop traffic from arriving on an ingress port that have used more than its fair share of buffering resources, thereby stopping traffic from an offending ingress port and relieving congestion caused by the offending ingress port. Specifically, each ingress port keeps track of whether or not it is in an ingress backpressure state based on ingress backpressure counters relative to the set of thresholds. When the ingress port is in ingress backpressure state, pause flow control frames with a timer value of (0xFFFF) are periodically sent out of that ingress port. When the ingress port is no longer in the ingress backpressure state, the pause flow control frame with a timer value of 0x00 is sent out of the ingress port and traffic is allowed to flow again. If an ingress port is not currently in an ingress backpressure state and the packet counter rises above limit threshold 312, the status for the ingress port transitions into the ingress backpressure state. If the ingress port is in the ingress backpressure state and the packet counter falls below reset limit threshold 316, the status for the port will transition out of the backpressure state.
  • Head of line mechanism 306 is provided to support fair access to buffering resources while optimizing throughput in the system. Head of line mechanism 306 relies on packet dropping to manage buffering resources and improve the overall system throughput. According to an embodiment of the invention, head of line mechanism 306 uses egress counters and predefined thresholds to track buffer usage on a egress port and class of service basis and thereafter makes decisions to drop any newly arriving packets on the ingress ports destined to a particular oversubscribed egress port/class of service queue. Head of line mechanism 306 supports different thresholds depending on the color of the newly arriving packet. Packets may be colored based on metering and marking operations that take place in the ingress module and the MMU acts on these packets differently depending on the color of the packet.
  • According to an embodiment of the invention, head of line mechanism 306 is configurable and operates independently on every class of service queue and across all ports, including the CPU port. Head of line mechanism 306 uses counters that track XQ memory 204 and CBP memory 202 usage and thresholds that are designed to support a static allocation of CBP memory buffers 202 and dynamic allocation of the available XQ memory buffers 204. A discard threshold 322 is defined for all cells in CBP memory 202, regardless of color marking. When the cell counter associated with a port reaches discard threshold 322, the port is transition to a head of line status. Thereafter, the port may transition out of the head of line status if its cell counter falls below a reset limit threshold 324.
  • For the XQ memory 204, a guaranteed fixed allocation of XQ buffers for each class of service queue is defined by a XQ entry value 330 a-330 h. Each of XQ entry value 330 a-330 h defines how many buffer entries should be reserved for an associated queue. For example, if 100 bytes of XQ memory are assigned to a port, the first four class of service queues associated with XQ entries 330 a-330 d respectively may be assigned the value of 10 bytes and the last four queues associated with XQ entries 330 d-330 h respectively may be assigned the value of 5 bytes. According to an embodiment of the invention, even if a queue does not use up all of the buffer entries reserved for it according to the associated XQ entry value, head of line mechanism 306 may not assign the unused buffer to another queue. Nevertheless, the remaining unassigned 40 bytes of XQ buffers for the port may be shared among all of the class of service queues associated with the port. Limits on how much of the shared pool of the XQ buffer may be consumed by a particular class of service queue is set with a XQ set limit threshold 332. As such, set limit threshold 332 may be used to define the maximum number of buffers that can be used by one queue and to prevent one queue from using all of the available XQ buffers. To ensure that the sum of XQ entry values 330 a-330 h do not add up to more than the total number of available XQ buffers for the port and to ensure that each class of service queue has access to its quota of XQ buffers as assigned by its entry value 330, the available pool of XQ buffer for each port is tracked using a port dynamic count register 334, wherein dynamic count register 334 keeps track of the number of available shared XQ buffers for the port. The initial value of dynamic count register 334 is the total number of XQ buffers associated with the port minus a sum of the number of XQ entry values 320 a-320 h. Dynamic count register 334 is decremented when a class of service queue uses an available XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value 330. Conversely, dynamic count register 334 is incremented when a class of service queue releases a XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value 330.
  • When a queue requests XQ buffer 204, head of line mechanism 306 determines if all entries used by the queue is less than the XQ entry value 330 for the queue and grants the buffer request if the used entries are less then the XQ entry value 330. If however, the used entries are greater than the XQ entry value 330 for the queue, head of line mechanism 306 determines if the amount requested is less than the total available buffer or less then the maximum amount set for the queue by the associated set limit threshold 332. Set limit threshold 332 is in essence a discard threshold that is associated with the queue, regardless of the color marking of the packet. As such, when the packet count associated with the packet reaches set limit threshold 332, the queue/port enters into a head of line status. When head of line mechanism 306 detects a head of line condition, it sends an update status so that ingress module 102 can drop packets on the congested port. However, due to latency, there may be packets in transition between ingress module 102 and MMU 104 when the status update is sent by head of line mechanism 306. In this case, the packet drops may occur at MMU 104 due to the head of line status. In an embodiment of the invention, due to the pipeline of packets between ingress module 102 and MMU 104, the dynamic pool of XQ pointers is reduced by a predefined amount. As such, when the number of available XQ pointers is equal to or less than the predefined amount, the port is transition to the head of line status and an update status is sent to by MMU 104 to ingress module 102, thereby reducing the number of packets that may be dropped by MMU 104. To transition out of the head of line status, the XQ packet count for the queue must fall below a reset limit (RL) threshold 336.
  • It is possible for the XQ counter for a particular class of service queue to not reach set limit threshold 332 and still have its packet dropped if the XQ resources for the port are oversubscribed by the other class of service queues. In an embodiment of the invention, intermediate discard thresholds 338 and 339 may also be defined for packets containing specific color markings, wherein each intermediate discard threshold defines when packets of a particular color should be dropped. For example, intermediate discard threshold 338 may be used to define when packets that are colored yellow should be dropped and intermediate discard threshold 339 may be used to define when packets that are colored red should be dropped. According to an embodiment of the invention, packets may be colored one of green, yellow or red depending on the priority level assigned to the packet. To ensure that packets associated with each color are processed in proportion to the color assignment in each queue, one embodiment of the present invention includes a virtual maximum (VM) threshold 340. Virtual maximum threshold 340 is equal to the number of unassigned and available buffers divided by the sum of the number of queues, wherein the quotient is added to the number of currently used buffers. Virtual maximum threshold 340 ensures that the packets associated with each color are processed in a relative proportion. Therefore, if the number of available unassigned buffers is less than the set limit threshold 332 for a particular queue and the queue requests access to all of the available unassigned buffers, head of line mechanism 306 calculates the virtual maximum threshold 340 for the queue and processes a proportional amount of packets associated with each color relative to the defined ratios for each color.
  • To conserve register space, the XQ thresholds may be expressed in a compressed form, wherein each unit represents a group of XQ entries. The group size is dependent upon the number of XQ buffers that are associated with a particular egress port/class of service queue.
  • Weighted random early detection mechanism 308 is a queue management mechanism that preemptively drops packets based on a probabilistic algorithm before XQ buffers 204 are exhausted. Weighted random early detection mechanism 308 is therefore used to optimize the overall network throughput. Weighted random early detection mechanism 308 includes an averaging statistic that is used to track each queue length and drop packets based on a drop profile defined for the queue. The drop profile defines a drop probability given a specific average queue size. According to an embodiment of the invention, weighted random early detection mechanism 308 may defined separate profiles on based on a class of service queue and packet.
  • FIG. 4 illustrates a configuration of an egress port arbitration implemented in the present invention. According to FIG. 4, MMU 104 also includes a scheduler 402 that provides arbitration across the eight class of service (COS) queues 404 a-404 h associated with each egress port to provide minimum and maximum bandwidth guarantees. Scheduler 402 is integrated with a set of minimum and maximum metering mechanisms 406 a-406 i that monitor traffic flows on a class of service basis and an overall egress port 109 basis. Metering mechanisms 406 a-406 i support traffic shaping functions and guarantee minimum bandwidth specifications on a class of service queue and/or egress port basis, wherein scheduling decisions by schedule 402 are configured largely via traffic shaping mechanisms 406 a-406 h along with a set of control masks that modify how scheduler 402 uses traffic shaping mechanisms 406 a-406 h.
  • As shown in FIG. 4, minimum and maximum metering mechanisms 406 a-406 i monitor traffic flows on a class of service queue basis and an overall egress port basis. Maximum and minimum bandwidth meters 406 a-406 h are used to feed state information to scheduler 402 which responds by modifying its service order across class of service queues 404. The inventive device 100 therefore enables system vendors to implement a quality of service model by configuring class of service queues 404 to support an explicit minimum and maximum bandwidth guarantee. In an embodiment of the invention, metering mechanisms 406 a-406 h monitor traffic flow on a class of service queue basis, provides state information regarding whether or nor a class of service flow is above or below a specified minimum and maximum bandwidth specification, and transmits the information into scheduler 402 which uses the metering information to modify its scheduling decisions. As such, metering mechanisms 406 a-406 h aid in partitioning class of service queues 404 into a set of queues that have not met the minimum bandwidth specification, a set that have met its minimum bandwidth but not its maximum bandwidth specification and a set that have exceeded its maximum bandwidth specification. If a queue is in the set that have not met its minimum bandwidth specification and there are packets in the queue, scheduler 402 services the queue according to the configured scheduling discipline. If a queue is in the set that have met its minimum bandwidth specification but has not exceeded it maximum bandwidth specification and there are packets in the queue, scheduler 402 services the queue according to the configured scheduling discipline. If a queue is in the set that have exceeded its maximum bandwidth specification or if the queue is empty, scheduler 402 does not service the queue.
  • In an embodiment of the invention, as illustrated in FIG. 5, minimum and maximum bandwidth metering mechanisms 406 a-406 h are implemented using a simple leaky bucket mechanism which tracks whether or not a class of service queue 404 has consumed its minimum or maximum bandwidth. The range of the minimum and maximum bandwidth setting for each class of service 404 is between 64 kbps to 16 Gbps, in 64 kbps increments. The leaky bucket mechanism has a configurable number of tokens “leaking” out of bucket 502 a-502 h, each of which is associated with one of queues 404 a-404 h, at a configurable rate. In metering the minimum bandwidth for a class of service queue 404, as packets enter the class of service queue 404, a number of tokens in proportion to the size of the packet is added to bucket 502, with a ceiling of bucket at high threshold 504. The leaky bucket mechanism includes a refresh update interface and a minimum bandwidth 506 which defines how many tokens are to be removed every refresh time unit. A minimum threshold 508 is set to indicate whether a flow has satisfied at least its minimum rate and a fill threshold 510 is set to indicate how many tokens are in leaky bucket 502. When fill threshold 510 rises above minimum threshold 508, a flag which indicates that the flow has satisfied its minimum bandwidth specification is set to true. When fill threshold 510 falls below minimum threshold 508, the flag is set to false.
  • Minimum threshold 508 affects what timescale the minimum bandwidth metering mechanism 406 is required to operate. If the minimum threshold 508 is set at a very low level, class of service queue 404 will quickly flag that its minimum bandwidth has been met. This reduces the amount of time queue 404 is classified in the set of queues that have not met the minimum bandwidth requirement and reduces the time period that the queue is given preferential treatment from scheduler 402. High threshold 504 affects how much credit can be built up after a class of service queue meets it minimum bandwidth 506. A large high threshold 504 may result in a reduction of time that the queue is classified with the set of queues that have not met the minimum bandwidth requirement and reduces the time period that the queue is given preferential treatment from scheduler 402.
  • After metering mechanisms 406 a-406 h indicate that the maximum bandwidth specified has been exceeded high threshold 504, scheduler 402 ceases to service the queue and the queue is classified as being in the set of queues that have exceeded it maximum bandwidth specification. A flag is then set to indicate that the queue has exceeded its maximum bandwidth. Thereafter, the queue will only receive service from scheduler 402 when its fill threshold 510 falls below high threshold 504 and the flag indicating that it has exceeded its maximum bandwidth is reset. Metering mechanism 406 i is used to indicate that the maximum bandwidth specified for a port has been exceeded and operates in the same manner as meter mechanisms 406 a-406 h when the maximum bandwidth has been exceeded. According to an embodiment of the invention, the maximum metering mechanism on a queue and port basis generally affects whether or not queue 404 or a port is to be included in scheduling arbitration. As such, the maximum metering mechanism only has a traffic limiting effect on scheduler 402.
  • On the other hand, minimum metering on a class of service queue 404 basis has a more complex interaction with scheduler 402. In one embodiment of the invention, scheduler 402 is configured to support a variety of scheduling disciplines that mimic the bandwidth sharing capabilities of a weighted fair queuing scheme. The weighted fair queue scheme is a weighted version of packet based fair queuing scheme, which is defined as a method for providing “bit-based round robin” scheduling of packets. As such, packets are scheduled for access to an egress port based on their delivery time, which is computed as if the scheduler is capable of providing bit-based round robin service. A relative weight field influences the specifics of how the scheduler makes use of the minimum metering mechanism, wherein the scheduler attempts to provide a minimum bandwidth guarantee. In an embodiment of the invention, the minimum bandwidth guarantee is a relative bandwidth guarantee wherein a relative field determines whether or not scheduler 402 will treat the minimum bandwidth metering settings as a specification for a relative or an absolute bandwidth guarantee. If the relative field is set, the scheduler treats minimum bandwidth 506 setting as a relative bandwidth specification. Scheduler 402 then attempts to provide relative bandwidth sharing across backlogged queues 404.
  • FIG. 6 illustrates an embodiment in which four queues are serviced according to their minimum bandwidth specifications. According to FIG. 6, a 1 GE egress port has scheduler 402 configured to be in a weighted fair queue mode and has its relative field set to true, wherein the minimum bandwidth for queue 602 a and 602 b is 10 Mbps, for queue 602 c is 20 Mbps and for queue 602 d is 40 Mbps. If all queues 602 have packets to be serviced, then scheduler 402 will provide relative bandwidth sharing across the active queues according to the predefined minimum bandwidth for each queue. However, since as mentioned above only queues 602 a-602 d have packets to be serviced, queue 602 d will receive twice the bandwidth of queue 602 c which receives twice the bandwidth that is given to queues 602 a and 602 b. If queues 602 a-602 d have enough packets to keep the 1 GE link fully utilized, queue 602 d will be allowed to process 500 Mbps, queue 602 c will be allowed to process 250 Mbps and queues 602 a and 602 b will be allowed to process 125 Mbps. On the other hand, if only queues 602 b-602 d are active, the bandwidth distribution will change to appropriately provide relative bandwidth sharing, wherein queue 602 d will be allowed to process 571.4 Mbps, queue 602 c will be allowed to process 265.7 Mbps and queue 602 b will be allowed to process 142.9 Mbps. As such, minimum bandwidth metering mechanisms 406 are constantly being adjusted to achieve the relative bandwidth sharing.
  • Returning to FIG. 5, according to an embodiment of the invention, in addition to the relative field, a relative threshold 514 is also set in each of queues 404. Relative threshold 514 is used to indicate that the minimum bandwidth 506 is set too low when fill threshold 510 of all queues have exceeded relative threshold 514. As such, when fill threshold 510 for each of queues 404 a-404 h rises above relative threshold 514, device 100 calculates a new minimum bandwidth 506, wherein:
  • new minimum bandwidth=old minimum bandwidth<<(K−MSB.POS)
      • wherein K is equal to a constant, and
      • MSB.POS is equal to a position of the Most Significant Bit
  • The new minimum bandwidth therefore allows device 100 to leak more tokens out of bucket 502 for each of queues 404 a-404 h, wherein the new leak is proportional to the old leak. According to another embodiment of the invention, the new minimum bandwidth may be calculated for an individual queue when fill threshold for that queue rises above relative threshold 514 for that queue.
  • The foregoing description has been directed to specific embodiments of this invention. It will be apparent, however, that other variations and modifications may be made to the described embodiments, with the attainment of some or all of their advantages. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.

Claims (20)

1. A memory management controller of a network switching device having an ingress module for associating packets received at an ingress port of the network switching device with one of a plurality of colors, a memory management unit, and an egress module, the memory management unit associated with a plurality of queues for storing packets received from the ingress module prior to outputting the packets from the network device via the egress module, the memory management controller comprising:
a resource guarantee module configured to determine a relative proportion of the plurality of colors to one another, and to determine memory locations available for use by the plurality of queues for the storing of the packets;
a memory allocation unit configured to receive a request for a subset of the available memory locations from one of the plurality of queues, and to determine that the request is associated with a potential inability of the memory management unit to maintain the relative proportion when storing the packets, and
a threshold determining unit configured to set a virtual maximum threshold for assigning the available memory locations to the plurality of queues, wherein
the memory allocation unit is configured to assign the memory locations to the plurality of queues in accordance with the virtual maximum threshold and the relative proportion, to thereby maintain the relative proportion during the storing of the packets.
2. The memory management controller of claim 1, comprising:
a determining unit configured to determine an amount of memory buffers of the memory locations that is associated with an egress port of the egress module, and configured to assign a fixed allocation of memory buffers to each of the plurality of queues associated with the port and for sharing remaining memory buffers of the memory locations among the plurality of queues, wherein the remaining memory buffers are used by each of the plurality of queues after the fixed allocation of memory buffers assigned to the queue is used; and
a setting unit configured to set a limit threshold for each of the plurality of queues, wherein the limit threshold determines how much of the remaining memory buffers may be used by each of the plurality of queues.
3. The memory management controller of claim 2, comprising:
a defining unit configured to define a plurality of color thresholds for each of the plurality of queues, wherein each of the plurality of color thresholds corresponds to the plurality of colors, and each of the plurality of color thresholds corresponds to a number of memory buffers,
wherein when one of the plurality of queues requests access to the remaining memory buffers and the remaining memory buffers is less than the limit threshold for the queue, the threshold determining unit is configured to set the virtual maximum threshold for the queue, wherein the virtual maximum threshold replaces the limit threshold.
4. The memory management controller of claim 3, wherein the threshold determining unit is configured to calculate the virtual maximum threshold for each of the plurality of queues by dividing the remaining memory buffers by a sum of the number of queues and adding a quotient to a number of currently used buffers.
5. The memory management controller of claim 3, further configured to track the remaining memory buffers with a dynamic register counter, wherein the dynamic register counter tracks the available memory buffers that are assigned to each port, to set an initial value of the dynamic register counter to a total number of memory buffers associated with the port minus a sum of the fixed allocation of memory buffers and to decrement the dynamic register counter when one of the plurality of queues uses one of the remaining memory buffers.
6. The memory management controller of claim 5, further configured to increment the dynamic register counter when one of the plurality of queues releases one of the remaining memory buffers.
7. The memory management controller of claim 3, wherein the determining unit is configured to determine if one of the plurality of queues has used less than its fixed allocation and to grant a buffer request by the one of the plurality of queues if queue has used less than the fixed allocation.
8. The memory management controller of claim 3, wherein the determining unit is configured to determine if one of the plurality of queues has used more than its fixed allocation and to grant a buffer request by the one of the plurality of queues if an amount requested by the queue is less than the remaining memory buffer and less than the limit threshold for the queue.
9. The memory management controller of claim 1, wherein the memory allocation unit is configured to drop packets based on their color and on the virtual maximum threshold in order to maintain the relative proportion.
10. The memory management controller of claim 1, wherein the plurality of colors correspond to a priority level assigned to the packet.
11. A method comprising:
associating packets received at an ingress port of a network switching device with one of a plurality of colors; and
storing the packets at a memory management unit of the network switching device, the memory management unit associated with a plurality of queues for storing the packets prior to outputting the packets from the network device using an associated egress port thereof, the storing of the packets including
determining a relative proportion of the plurality of colors to one another,
determining memory locations available for use by the plurality of queues for the storing of the packets,
receiving a request for a subset of the available memory locations from one of the plurality of queues,
determining that the request is associated with a potential inability of the memory management unit to maintain the relative proportion when storing the packets,
setting a virtual maximum threshold for assigning the available memory locations to the plurality of queues, and
assigning the memory locations to the plurality of queues in accordance with the virtual maximum threshold and the relative proportion, to thereby maintain the relative proportion during the storing of the packets.
12. The method of claim 11, wherein determining the memory locations comprises determining an amount of memory buffers of the memory locations that is associated with an egress port of the egress module, and wherein assigning the memory locations comprises
assigning a fixed allocation of memory buffers to each of the plurality of queues associated with the port,
sharing remaining memory buffers of the memory locations among the plurality of queues, wherein the remaining memory buffers are used by each of the plurality of queues after the fixed allocation of memory buffers assigned to the queue is used; and
setting a limit threshold for each of the plurality of queues, wherein the limit threshold determines how much of the remaining memory buffers may be used by each of the plurality of queues.
13. The method of claim 12, comprising:
defining a plurality of color thresholds for each of the plurality of queues, wherein each of the plurality of color thresholds corresponds to the plurality of colors, and each of the plurality of color thresholds corresponds to a number of memory buffers,
wherein when one of the plurality of queues requests access to the remaining memory buffers and the remaining memory buffers is less than the limit threshold for the queue, the virtual maximum threshold is set for the queue and replaces the limit threshold.
14. The method of claim 13, wherein setting the virtual maximum threshold comprises setting the virtual maximum threshold for each of the plurality of queues by dividing the remaining memory buffers by a sum of the number of queues and adding a quotient to a number of currently used buffers.
15. The method of claim 13, wherein storing the packets comprises:
tracking the remaining memory buffers with a dynamic register counter, wherein the dynamic register counter tracks the available memory buffers that are assigned to each port,
setting an initial value of the dynamic register counter to a total number of memory buffers associated with the port minus a sum of the fixed allocation of memory buffers, and
decrementing the dynamic register counter when one of the plurality of queues uses one of the remaining memory buffers.
16. The method of claim 15, comprising incrementing the dynamic register counter when one of the plurality of queues releases one of the remaining memory buffers.
17. A network device for dynamically allocating memory locations to a plurality of queues, the network device comprising:
an ingress module configured to associate packets received at an ingress port of the network switching device with one of a plurality of colors;
a memory management unit associated with a plurality of queues for storing packets received from the ingress module; and
an egress module configured to receive the packets from the memory management unit and configured to output the packets using an egress port of the network device,
wherein the memory management unit is configured to:
determine a relative proportion of the plurality of colors to one another, and to determine memory locations available for use by the plurality of queues for the storing of the packets;
receive a request for a subset of the available memory locations from one of the plurality of queues, and to determine that the request is associated with a potential inability of the memory management unit to maintain the relative proportion when storing the packets,
set a virtual maximum threshold for assigning the available memory locations to the plurality of queues, and
assign the memory locations to the plurality of queues in accordance with the virtual maximum threshold and the relative proportion, to thereby maintain the relative proportion during the storing of the packets.
18. The network device of claim 17, wherein the memory management unit is further configured to:
determine an amount of memory buffers of the memory locations that is associated with an egress port of the egress module;
assign a fixed allocation of memory buffers to each of the plurality of queues associated with the port and for sharing remaining memory buffers of the memory locations among the plurality of queues, wherein the remaining memory buffers are used by each of the plurality of queues after the fixed allocation of memory buffers assigned to the queue is used; and
set a limit threshold for each of the plurality of queues, wherein the limit threshold determines how much of the remaining memory buffers may be used by each of the plurality of queues.
19. The network device of claim 18, wherein the memory management unit is further configured to:
define a plurality of color thresholds for each of the plurality of queues, wherein each of the plurality of color thresholds corresponds to the plurality of colors, and each of the plurality of color thresholds corresponds to a number of memory buffers,
wherein when one of the plurality of queues requests access to the remaining memory buffers and the remaining memory buffers is less than the limit threshold for the queue, the threshold determining unit is configured to set the virtual maximum threshold for the queue, wherein the virtual maximum threshold replaces the limit threshold.
20. The network device of claim 19, wherein the memory management unit is further configured to calculate the virtual maximum threshold for each of the plurality of queues by dividing the remaining memory buffers by a sum of the number of queues and adding a quotient to a number of currently used buffers.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130163418A1 (en) * 2011-12-23 2013-06-27 Electronics And Telecommunications Research Institute Packet transport system and traffic management method thereof
US20140105218A1 (en) * 2012-10-12 2014-04-17 Prashant H. Anand Queue monitoring to filter the trend for enhanced buffer management and dynamic queue threshold in 4g ip network/equipment for better traffic performance
US8867360B2 (en) 2012-03-22 2014-10-21 Avaya Inc. Method and apparatus for lossless behavior for multiple ports sharing a buffer pool

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7609709B2 (en) * 2006-01-23 2009-10-27 Alcatel-Lucent Usa Inc. Video aware traffic management
JP4899961B2 (en) * 2007-03-19 2012-03-21 富士通株式会社 Communication apparatus and output control method
EP2290552A4 (en) * 2008-06-03 2012-08-15 Fujitsu Ltd Data transfer device, information processing device, and control method
CN108153689B (en) * 2016-12-06 2020-04-24 比亚迪股份有限公司 Method and apparatus for polling arbitration
US10536505B2 (en) * 2017-04-30 2020-01-14 Cisco Technology, Inc. Intelligent data transmission by network device agent
WO2019232694A1 (en) * 2018-06-05 2019-12-12 华为技术有限公司 Queue control method, device and storage medium
US11902167B2 (en) * 2019-07-04 2024-02-13 Nippon Telegraph And Telephone Corporation Communication apparatus having delay guarantee shaping function

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414704A (en) * 1992-10-22 1995-05-09 Digital Equipment Corporation Address lookup in packet data communications link, using hashing and content-addressable memory
US5423015A (en) * 1988-10-20 1995-06-06 Chung; David S. F. Memory structure and method for shuffling a stack of data utilizing buffer memory locations
US5541912A (en) * 1994-10-04 1996-07-30 At&T Corp. Dynamic queue length thresholds in a shared memory ATM switch
US5610905A (en) * 1993-07-19 1997-03-11 Alantec Corporation Communication apparatus and methods
US5892922A (en) * 1997-02-28 1999-04-06 3Com Corporation Virtual local area network memory access system
US5991295A (en) * 1995-10-10 1999-11-23 Madge Networks Limited Digital switch
US6016310A (en) * 1997-06-30 2000-01-18 Sun Microsystems, Inc. Trunking support in a high performance network device
US6088356A (en) * 1997-06-30 2000-07-11 Sun Microsystems, Inc. System and method for a multi-layer network element
US6119196A (en) * 1997-06-30 2000-09-12 Sun Microsystems, Inc. System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates
US6219728B1 (en) * 1996-04-22 2001-04-17 Nortel Networks Limited Method and apparatus for allocating shared memory resources among a plurality of queues each having a threshold value therefor
US6259699B1 (en) * 1997-12-30 2001-07-10 Nexabit Networks, Llc System architecture for and method of processing packets and/or cells in a common switch
US6335935B2 (en) * 1998-07-08 2002-01-01 Broadcom Corporation Network switching architecture with fast filtering processor
US6425015B1 (en) * 1997-11-28 2002-07-23 3 Com Technologies Stacked communication devices and method for port mirroring using modified protocol
US6591299B2 (en) * 1997-11-25 2003-07-08 Packeteer, Inc. Method for automatically classifying traffic with enhanced hierarchy in a packet communications network
US6724776B1 (en) * 1999-11-23 2004-04-20 International Business Machines Corporation Method and system for providing optimal discard fraction
US20060187826A1 (en) * 2005-02-18 2006-08-24 Broadcom Corporation Dynamic sharing of a transaction queue
US20070189283A1 (en) * 2002-03-06 2007-08-16 Agere Systems Inc. Characterizing transmission of data segments within a switch fabric using multiple counters for each destination node
US7284076B2 (en) * 2003-06-27 2007-10-16 Broadcom Corporation Dynamically shared memory
US7403976B2 (en) * 2000-07-24 2008-07-22 Mosaid Technologies Inc. Method and apparatus for reducing pool starvation in a shared memory switch

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4899334A (en) 1987-10-19 1990-02-06 Oki Electric Industry Co., Ltd. Self-routing multistage switching network for fast packet switching system
US5689506A (en) 1996-01-16 1997-11-18 Lucent Technologies Inc. Multicast routing in multistage networks
US6094435A (en) 1997-06-30 2000-07-25 Sun Microsystems, Inc. System and method for a quality of service in a multi-layer network element
US5920566A (en) 1997-06-30 1999-07-06 Sun Microsystems, Inc. Routing in a multi-layer distributed network element
US6680933B1 (en) 1999-09-23 2004-01-20 Nortel Networks Limited Telecommunications switches and methods for their operation

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5423015A (en) * 1988-10-20 1995-06-06 Chung; David S. F. Memory structure and method for shuffling a stack of data utilizing buffer memory locations
US5414704A (en) * 1992-10-22 1995-05-09 Digital Equipment Corporation Address lookup in packet data communications link, using hashing and content-addressable memory
US5610905A (en) * 1993-07-19 1997-03-11 Alantec Corporation Communication apparatus and methods
US5541912A (en) * 1994-10-04 1996-07-30 At&T Corp. Dynamic queue length thresholds in a shared memory ATM switch
US5991295A (en) * 1995-10-10 1999-11-23 Madge Networks Limited Digital switch
US6219728B1 (en) * 1996-04-22 2001-04-17 Nortel Networks Limited Method and apparatus for allocating shared memory resources among a plurality of queues each having a threshold value therefor
US5892922A (en) * 1997-02-28 1999-04-06 3Com Corporation Virtual local area network memory access system
US6119196A (en) * 1997-06-30 2000-09-12 Sun Microsystems, Inc. System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates
US6088356A (en) * 1997-06-30 2000-07-11 Sun Microsystems, Inc. System and method for a multi-layer network element
US6016310A (en) * 1997-06-30 2000-01-18 Sun Microsystems, Inc. Trunking support in a high performance network device
US6591299B2 (en) * 1997-11-25 2003-07-08 Packeteer, Inc. Method for automatically classifying traffic with enhanced hierarchy in a packet communications network
US6425015B1 (en) * 1997-11-28 2002-07-23 3 Com Technologies Stacked communication devices and method for port mirroring using modified protocol
US6259699B1 (en) * 1997-12-30 2001-07-10 Nexabit Networks, Llc System architecture for and method of processing packets and/or cells in a common switch
US6335935B2 (en) * 1998-07-08 2002-01-01 Broadcom Corporation Network switching architecture with fast filtering processor
US6724776B1 (en) * 1999-11-23 2004-04-20 International Business Machines Corporation Method and system for providing optimal discard fraction
US7403976B2 (en) * 2000-07-24 2008-07-22 Mosaid Technologies Inc. Method and apparatus for reducing pool starvation in a shared memory switch
US20070189283A1 (en) * 2002-03-06 2007-08-16 Agere Systems Inc. Characterizing transmission of data segments within a switch fabric using multiple counters for each destination node
US7284076B2 (en) * 2003-06-27 2007-10-16 Broadcom Corporation Dynamically shared memory
US20060187826A1 (en) * 2005-02-18 2006-08-24 Broadcom Corporation Dynamic sharing of a transaction queue

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130163418A1 (en) * 2011-12-23 2013-06-27 Electronics And Telecommunications Research Institute Packet transport system and traffic management method thereof
US9215187B2 (en) * 2011-12-23 2015-12-15 Electronics And Telecommunications Research Institute Packet transport system and traffic management method thereof
US8867360B2 (en) 2012-03-22 2014-10-21 Avaya Inc. Method and apparatus for lossless behavior for multiple ports sharing a buffer pool
US20140105218A1 (en) * 2012-10-12 2014-04-17 Prashant H. Anand Queue monitoring to filter the trend for enhanced buffer management and dynamic queue threshold in 4g ip network/equipment for better traffic performance

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