US20090134462A1 - Semiconductor integrated circuit and method of fabricating same - Google Patents
Semiconductor integrated circuit and method of fabricating same Download PDFInfo
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- US20090134462A1 US20090134462A1 US12/361,923 US36192309A US2009134462A1 US 20090134462 A1 US20090134462 A1 US 20090134462A1 US 36192309 A US36192309 A US 36192309A US 2009134462 A1 US2009134462 A1 US 2009134462A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 41
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 46
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 39
- 239000012535 impurity Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 239000010408 film Substances 0.000 abstract description 108
- 239000012212 insulator Substances 0.000 abstract description 31
- 239000010409 thin film Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 49
- 229910052698 phosphorus Inorganic materials 0.000 description 48
- 239000011574 phosphorus Substances 0.000 description 48
- -1 phosphorus ions Chemical class 0.000 description 32
- 238000000034 method Methods 0.000 description 31
- 239000011159 matrix material Substances 0.000 description 26
- 229910052782 aluminium Inorganic materials 0.000 description 24
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 23
- 239000011229 interlayer Substances 0.000 description 21
- 125000004429 atom Chemical group 0.000 description 20
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 19
- 150000002500 ions Chemical class 0.000 description 17
- 239000002019 doping agent Substances 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 229910052796 boron Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 239000002994 raw material Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000001272 nitrous oxide Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052706 scandium Inorganic materials 0.000 description 2
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 208000022010 Lhermitte-Duclos disease Diseases 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring.
Description
- 1. Field of the Invention
- The present invention relates to an integrated circuit comprising an insulating substrate on which insulated-gate semiconductor devices (TFTs) in the form of thin films are formed and also to a method of fabricating the integrated circuit. The insulated substrate referred to herein means a whole object having a dielectric surface and embraces semiconductors, metals, and other materials on which an insulator layer is formed, unless stated otherwise. Semiconductor integrated circuits according to the invention can be used in various circuits and devices, such as active matrix circuits of liquid crystal displays, their peripheral driver circuits, driver circuits for driving image sensors or the like, SOI integrated circuits, and conventional semiconductor integrated circuits (e.g., microprocessors, microcontrollers, microcomputers, and semiconductor memories, and so forth).
- 2. Description of the Related Art
- Where an active matrix liquid crystal display, an image sensor circuit, or other circuit is formed on a glass substrate, use of integrated thin-film transistors (TFTs) has enjoyed wide acceptance. In this case, it is customary to first form a first wiring including a gate electrode. Then, an interlayer insulator layer is formed. Subsequently, a second wiring is formed. If necessary, a third and even a fourth wirings may be formed.
- A serious problem with such a TFT integrated circuit is that the second wiring breaks at the intersections of this second wiring and a gate wiring which is an extension of a gate electrode. This is caused by the fact that it is difficult to form an interlayer insulator layer over a gate electrode and wiring with a good step coverage and to flatten the insulator layer.
-
FIG. 4 illustrates wiring breakage often occurring in the prior art TFT integrated circuit. ATFT region 401 and agate wiring 402 are formed over a substrate. Aninterlayer insulator 403 is formed on these region and wiring. If the edges of thegate wiring 402 are sharp, theinterlayer insulator 403 cannot fully cover the gate wiring. Under this condition, if the second wiring, 404 and 405, is formed, it is likely that the second layer breaks, as shown, atportions 406. - In order to prevent such wiring breakage, it is necessary to increase the thickness of the second wiring. For example, it has been desired to increase the thickness of the gate wiring about twofold. However, this means that the unevenness on the integrated circuit is increased further. If a further wiring is required to be deposited, breakage due to the thickness of the second wiring must be taken into consideration. Where an integrated circuit whose unevenness should be suppressed as in a liquid crystal display, it is substantially impossible to address the problem by increasing the thickness of the second wiring.
- In an integrated circuit, if a wiring breakage occurs even at one edge of a step, then the whole circuit is made useless. Therefore, it is important to reduce wiring breakages at steps.
- It is an object of the present invention to provide a method of fabricating a semiconductor integrated circuit with minimum wiring breakages at steps and thus with improved production yield.
- It is another object of the invention to provide a semiconductor integrated circuit in which wiring breakages at steps are reduced to a minimum.
- In the present invention, after forming gate electrodes and gate wiring, a silicon nitride film is formed at least on their top surfaces, preferably even on their side surfaces, by plasma CVD or sputtering. Then, a substantially triangular regions (side walls) is formed out of the insulator on the side surfaces of the gate electrodes and of the gate wiring by anisotropic etching. Subsequently, an interlayer insulator is deposited, followed by formation of a second wiring. Silicon nitride exhibits a small etch rate under conditions in which silicon oxide forming the side walls is etched by dry etching. Therefore, the silicon nitride can be used as an etching stopper.
- In a first method embodying the present invention, a semiconductor layer in the form of islands is first formed. A coating becoming a gate-insulating film is formed on the semiconductor layer. Then, gate electrodes and gate wiring are formed. Thereafter, silicon nitride is deposited as a film to a thickness of 100 to 2000 Å, preferably 200 to 1000 Å, by plasma-assisted CVD. Other CVD processes or sputtering techniques can also be employed. Thus, the first step of the inventive method is completed.
- Then, a coating of an insulator is formed on the silicon nitride. In this stage of formation of the coating, the coverage is important. Preferably, the thickness of the coating is one-third to 2 times the height of the gate electrodes and the gate wiring. For this purpose, plasma-assisted CVD, LPCVD, atmospheric pressure CVD, and other CVD processes are preferably used. The insulator layer formed in this way is preferentially etched in a direction substantially vertical to the substrate by anisotropic etching. The etching terminates at the surface of the silicon nitride. The underlying gate electrodes and gate wiring are prevented from being etched.
- As a result, substantially triangular regions of an insulator, or side walls, are left on the side surfaces of the gate electrodes and gate wiring, because the coating of the insulator is intrinsically thick on steps such as on the side surfaces of the gate electrodes and gate wiring. Thus, the second step of the inventive method is completed.
- Then, an interlayer insulator is deposited. Contact holes are formed in one or both of source and drain regions of each TFT. The second wiring is formed, thus completing the third step of the inventive method.
- Immediately after the side walls are formed in the second step, the film of silicon nitride can be etched by dry etching. Preferably, this etching step is performed while monitoring it with an endpoint monitor or other instrument. The etching of the film of silicon nitride can be controlled well with the monitor. The thickness of the etched silicon nitride film is 100 to 2000 Å. Therefore, even if overetching occurs, the depth is much smaller than the thickness of the gate electrodes and gate-insulating film. Hence, the gate electrodes and gate-insulating film are little affected thereby.
- This method is effective where the gate-insulating film and the interlayer insulator are made from the same material different from silicon nitride. That is, if the interlayer insulator layer is formed after etching the silicon nitride film, the etching can be completed in one operation when the contact holes are formed.
- Dopants are implanted to form the source and drain regions of each TFT. This implantation step can be varied variously. For example, where only N-channel TFTs are formed on a substrate, an N-type impurity may be introduced into the semiconductor layer at a relatively high concentration by self-alignment techniques, using the gate electrodes as a mask. This step is carried out between the first and second steps described above.
- Similarly, where N-channel TFTs are formed, if they have the lightly doped drain (LDD) structure, an impurity is introduced into the semiconductor layer at a relatively low concentration. This step is effected between the first and second steps described above. Then, an N-type impurity is introduced into the semiconductor layer at a higher concentration by self-alignment techniques, using the gate electrodes and the side walls as a mask. This step is performed between the second and third steps described above. In this case, the width of the lightly doped drains is approximate to the width of the side walls. Where only P-channel TFTs are formed on a substrate, similar steps may be carried out.
- Where offset TFTs are fabricated, an impurity is introduced into the semiconductor layer at a high concentration, using the gate electrodes and side walls as a mask, by self-alignment techniques. This step is carried out between the second and third steps described above. In this case, the width of the offset structure is approximate to the width of the side walls. In the TFT of this construction, the width of the substantially intrinsic region becoming a channel formation region is approximately equal to the sum of the width of the gate electrode and the widths of both side walls.
- A complementary MOS (CMOS) circuit having N-channel TFTs and P-channel TFTs can be fabricated similarly on a substrate. Where N-channel TFTs and P-channel TFTs are composed of ordinary TFTs, or where both kinds of TFTs are composed of LDD TFTs, an N-type impurity and a P-type impurity are implanted similarly to the above-described method in which only one kind of TFTs, or N-channel or P-channel TFTs, is formed on a substrate.
- For example, where N-channel TFTs which are required to take countermeasures against hot carriers are made of the LDD type and P-channel TFTs which are not required to take such countermeasures are both made of ordinary TFTs, the impurity implantation step is a slightly special step. In this case, an N-type impurity is introduced into the semiconductor layer at a relatively low concentration. This step is carried out between the first and second steps described above. This is referred to as the first impurity introduction. At this time, the N-type impurity may be added even into the semiconductor layer of the P-channel TFTs.
- Then, masking the semiconductor layer of the N-channel TFTs, a P-type impurity is introduced only into the semi-conductor layer of the P-channel TFTs at a higher concentration. This is referred to as the second impurity introduction. Even if the N-type impurity exists in the P-channel TFTs as a result of the previous introduction of the N-type impurity, the P-type impurity is introduced at a higher concentration as a result of the second impurity introduction. As a result, the semi-conductor is rendered P-type. Of course, the concentration of the second impurity is greater than that of the first impurity. Preferably, the concentration of the second impurity is one to three orders of magnitude greater than that of the first impurity.
- Finally, in order to form source/drain regions of the N-channel TFTS, an N-type impurity is introduced at a relatively high concentration. This step is carried out between the second and third steps described above. This is referred to as the third impurity introduction. In this case, in order to prevent the N-type impurity from being introduced into the P-channel TFTs, they may or may not be masked. In the latter case, it is necessary that the concentration of the introduced N-type impurity be lower than that of the P-type impurity introduced by the second impurity introduction. Preferably, the concentration of the introduced N-type impurity is one-tenth to two-thirds of the concentration of the P-type impurity introduced by the second impurity introduction. As a result, the N-type impurity is introduced even into the P-channel TFTs but at a lower concentration than the P-type impurity previously introduced. Therefore, the P-channel TFTs are maintained as P-type.
- In the present invention, the presence of the side walls improves the step coverage at portions at which the gate wiring extends over the interlayer insulator layer, thus reducing breakages of the second wiring. Furthermore, the lightly doped structure or the offset structure can be obtained by making use of the side walls described above.
- In the present invention, the existence of the silicon nitride film is of importance. In the above-described second step, anisotropic etching is done to form the side walls. However, on a dielectric surface, it is difficult to control plasma. The substrate is inevitably etched non-uniformly.
- The etching depth is one-third to 2 times as large as the height of the gate electrodes and gate wiring. Therefore, the nonuniform etching produces great effects. If no silicon nitride film is formed on the top surfaces of the gate electrodes, the gate electrodes and gate wiring will be etched severely at some locations within the same substrate during the etching of the side walls.
- If any silicon nitride film exists during the etching of the side walls, the etching stops at this location, thus protecting the gate electrodes and gate wiring. If the silicon nitride film is removed later by dry etching, the etching depth is much smaller than the etching depth in the side walls. Consequently, even if the gate electrodes and gate wiring are overetched, no great effects are produced.
- Other objects and features of the invention will appear in the course of the description thereof, which follows.
-
FIGS. 1(A)-1(F) are cross sectional views for showing the manufacturing method in accordance with Example 1 of the present invention; -
FIGS. 2(A)-2(F) are cross sectional views for showing the manufacturing method in accordance with Example 2 of the present invention; -
FIGS. 3(A)-3(E) are cross sectional views for showing the manufacturing method in accordance with Example 3 of the present invention; -
FIG. 4 is a cross section of a TFT circuit, illustrating the prior art fabrication method; -
FIGS. 5(A)-5(F) are cross sectional views for showing the manufacturing method in accordance with Example 4 of the present invention; -
FIGS. 6(A)-6(F) are cross sectional views for showing the manufacturing method in accordance with Example 5 of the present invention; -
FIGS. 7(A)-7(F) are cross sectional views for showing the manufacturing method in accordance with Example 6 of the present invention; -
FIGS. 8(A)-8(G) are cross sectional views for showing the manufacturing method in accordance with Example 7 of the present invention; - The present example is illustrated in
FIGS. 1(A)-1(F) . First, silicon oxide was deposited as abuffer layer 102 on asubstrate 101 made of Corning 7059 glass. Thesubstrate 101 measured 300 mm×400 mm or 100 mm×100 mm. The thickness of thebuffer layer 102 was 1000 to 5000 Å, e.g., 2000 Å. The oxide film was formed in an oxygen ambient by sputtering or by plasma-assisted CVD, using TEOS as a raw material. The silicon oxide film formed in this way could be annealed at 400 to 650° C. - Then, an amorphous silicon film was deposited to a thickness of 300 to 5000 Å, preferably 400 to 1000 Å, e.g., 500 Å, by plasma-assisted CVD or LPCVD. The laminate was allowed to stand in a reducing ambient of 550 to 600° C. for 8 to 24 hours, thus crystallizing the amorphous film. At this time, a trace amount of a metal element for promoting crystallization such as nickel could be added. This step could also use laser irradiation. The silicon film crystallized in this way was etched to form
island regions 103. Then, silicon oxide was deposited as a gate-insulatingfilm 104 on the laminate to a thickness of 700 to 1500 Å, e.g., 1200 Å, by plasma-assisted CVD. - Thereafter, an aluminum film having a thickness of 1000 Å to 3 μm, e.g., 5000 Å, was formed by sputtering and etched to form a
gate electrode 105 and agate wiring 106. If an appropriate amount of silicon, copper, scandium, or other material were contained in the aluminum film, generation of hillocks could be suppressed when a silicon nitride film was formed subsequently. For example, where scandium was contained, its concentration was 0.1 to 0.3% by weight (FIG. 1(A) ). - Subsequently, a
silicon nitride film 107 was formed to a thickness of 100 to 2000 Å, preferably 200 to 1000 Å, e.g., 500 Å, by plasma-assisted CVD using a mixture gas of NH3, SiH4, and H2. Other CVD processes or sputtering methods may also be used but it is desired that the gate electrode be covered with good step coverage. - Thereafter, using the gate electrode as a mask, an impurity (in this example, phosphorus) was implanted into the
silicon film 103 in the form of islands by self-aligned ion doping techniques. In this way, lightly dopedregions 108 were formed, as shown inFIG. 1(B) . The dose was 1×1013 to 5×1014 atoms/cm2. The accelerating voltage was 10 to 90 kV. For example, the dose was 5×1013 atoms/cm2. The accelerating voltage was 80 kV (FIG. 1(B) ). - A silicon oxide was deposited as a
film 109 by plasma-assisted CVD, using TEOS and oxygen as raw materials or using monosilane and nitrous oxide as raw materials. The optimum value of thesilicon oxide film 109 varies, depending on the height of the gate electrode and gate wiring. For example, where the height of the gate electrode and gate wiring including the silicon nitride film is about 5000 Å as in the present example, the optimum value is preferably one-third to 2 times this value, i.e., 2000 Å to 1.2 μm. In this example, the value was 6000 Å. In this film formation step, the film thickness of planar portions is required to be uniform. In addition, the step coverage must be good. As a result, the thickness of the silicon oxide film at the side surfaces of the gate electrode and gate wiring is increased by the portions indicated by the broken lines inFIG. 1(C) (FIG. 1(C) ). - This
silicon oxide film 109 was etched by anisotropic etching, using the well-known RIE process. This etching terminated at the surface of thesilicon nitride film 107. Since the silicon nitride film was not readily etched by anisotropic etching using the RIE process, the etching did not progress into the gate-insulatingfilm 104. By the steps described thus far, substantially triangular region of an insulator orside walls FIG. 1(D) ). - Then, phosphorus ions were implanted again by ion doping. In this case, the dose is preferably one to three orders of magnitude higher than the dose used in the step shown in
FIG. 1(B) . In the present example, the dose was 40 times as high as the dose of the initially implanted phosphorus, i.e., 2×1015 atoms/cm2. The accelerating voltage was 80 kV. As a result, source/drain regions 113 heavily doped with phosphorus were created. Lightly dopedregions 112 were left under the side walls (FIG. 1(E) ). - The laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 nsec to activate the dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2. In the present example, the gate electrode was made of aluminum. Since the gate electrode was capped with the
silicon nitride film 107, the gate electrode was not affected by the laser irradiation. Instead of the laser irradiation, rapid thermal annealing (RTA) or rapid thermal processing (RTP) can be utilized. - Finally, silicon oxide was deposited as an
interlayer insulator layer 114 over the whole surface to a thickness of 5000 Å by CVD. Contact holes were created in the source/drain regions of the TFT. The second wiring, oraluminum wiring 115 andaluminum electrodes 116, was formed. The thickness of the aluminum wiring was approximate to the thickness of the gate electrode and wiring, i.e., 4000 to 6000 Å. - TFTs having N-channel LDDs were completed by the manufacturing steps described thus far. In order to activate the doped regions, hydrogen annealing may be carried out at 200 to 400° C. The presence of the
side walls 111 make milder the steps over which thesecond wiring 116 are extended. Therefore, little breakages were observed although the thickness of the second wiring was substantially the same as the thickness of the gate electrode and wiring (FIG. 1(F) ). - When the thickness of the gate electrode/wiring is x (Å) and the thickness of the second wiring is y (Å), the following relation should be satisfied in order to prevent wire disconnection.
-
y≧x−1000(Å) - As the thickness y is reduced, more desirable results are obtained. The inventors of the present invention have found that in the case of a circuit required to have a less uneven surface as in the active matrix circuit of a liquid crystal display, if the relations given by
-
x−1000(Å)≦y≦x+1000(Å) - are met, then satisfactory results arise.
-
FIGS. 2(A)-2(F) illustrate the second example of the present invention. The present example pertains to a monolithic active matrix circuit having an active matrix circuit and a driver circuit for driving the active matrix circuit. Both the active matrix circuit and the driver circuit are formed on the same substrate. In the present example, P-channel TFTs are used for the switching devices of the active matrix circuit. The driver circuit is a complementary circuit consisting of N-channel and P-channel TFTs. Shown at the left sides ofFIGS. 2(A)-2(F) are cross-sectional views of the N-channel TFT used in the driver circuit, illustrating the process sequence. Shown at the right sides ofFIGS. 2(A)-2(F) are cross-sectional views of the P-channel TFT used in the driver circuit or in the active matrix circuit, illustrating the process sequence. P-channel TFTs are used as the switching circuits of the active matrix circuit, because the leakage current (also called as OFF current) is small. - First, an insulating oxide was deposited as a
buffer layer 202 on asubstrate 201 made of Corning 7059 glass, in the same way as in Example 1. A semiconductor region in the form of islands was formed on thebuffer layer 202. Asilicon oxide film 203 acting as a gate oxide film was formed.Gate electrodes silicon oxide film 206 having a thickness of 100 to 2000 Å, e.g., 1000 Å, was formed. Using the gate electrode as a mask, phosphorus ions were implanted by ion doping. As a result, lightly doped N-type regions - The laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 nsec to activate the implanted dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2 (
FIG. 2(A) ). - Then, the N-channel TFT regions were masked with
photoresist 209. Under this condition, boron ions were implanted at a high dose of 5×1015 atoms/cm2 by ion doping. The accelerating voltage was 65 kV. As a result, theregion 208 which was lightly doped N-type by the previous implant of phosphorus was changed into a strong P-type. Thus, a P-type dopedregion 210 was formed. The laminate was then irradiated with laser light to activate the dopant (FIG. 2(B) ). - After removing the
mask 209 of the photoresist, asilicon oxide film 211 having a thickness of 4000 to 8000 Å was formed by plasma-assisted CVD (FIG. 2(C) ). -
Side walls FIG. 2(D) ). - Then, phosphorus ions were implanted by ion doping. In this case, the dose was 1 to 3 orders of magnitude greater than the dose used in the step illustrated in
FIG. 2(A) . Preferably, the dose is one-tenth to two-thirds of the dose used in the step illustrated inFIG. 2(B) . In the present example, the dose was 200 times as high as the dose of the phosphorus ions first implanted, i.e., 2×1015 atoms/cm2. This is 40% of the dose of the boron used in the step illustrated inFIG. 2(B) . The accelerating voltage was 80 kV. As a result, source/drain regions 214 heavily doped with phosphorus were formed. Lightly doped drain (LDD)regions 215 were formed under the side walls. - The laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 sec to activate the implanted dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2.
- The P-channel TFT (the right side in the figure) was doped with phosphorus and maintained in P-type, because the concentration of the previously doped boron was 2.5 times as high as the concentration of the phosphorus. Apparently, the P-type region of the P-channel TFT had two kinds of regions, i.e.,
regions 217 under the side walls andouter regions 216 on the opposite side of the channel formation regions. However, these two kinds of regions made no great difference in electrical characteristics (FIG. 2(E) ). - Finally, as shown in
FIG. 2(F) , silicon oxide was deposited as aninterlayer insulator layer 218 to a thickness of 3000 Å over the whole surface, as shown inFIG. 2(F) . Contact holes were created in the source/drain regions of the TFT. Aluminum wiring/electrodes - The interlayer insulator layer was not very thick at the portion at which the second wiring went over the gate wiring. However, almost no wiring breakages were observed in the same way as in Example 1.
- In the present example, the N-channel TFT assumed the LDD structure to prevent hot carriers from deteriorating the performance of the device. However, the LDD region was a parasitic resistor inserted in series with the source/drain regions and so the operating speed dropped. Accordingly, in the case of the P-channel TFT which has a small mobility and is less susceptible to deterioration due to hot carriers, it is desired that no LDD exist as in the present example.
- In the present example, the dopant was activated by laser irradiation whenever a doping step was carried out. Alternatively, all activation steps may be simultaneously performed immediately before all the doping steps were ended and the interlayer insulator layer was formed.
- The present example is illustrated in
FIGS. 3(A)-3(E) . The present example is an example of fabrication of a TFT, using formation of offset regions employing side walls. - First, silicon oxide was formed as a
buffer layer 302 on asubstrate 301 to a thickness of 1000 to 5000 Å, e.g., 2000 Å, in the same way as in Example 1. The silicon oxide film could be annealed at 400 to 650° C. Aregion 303 in the form of islands was formed by the method described in Example 1. Asilicon oxide film 304 having a thickness of 700 to 1500 Å, e.g., 1200 Å, was formed by plasma-assisted CVD. - Then, a phosphorus-doped polycrystalline silicon film having a thickness of 1000 Å to 3 μm, e.g., 5000 Å, was formed by LPCVD. This was etched to form a
gate electrode 305 and a gate wiring 306 (FIG. 3(A) ). - Thereafter, a
silicon nitride film 307 was formed to a thickness of 100 to 2000 Å, preferably 200 to 1000 Å, within a mixture gas of phosphine (NH3), monosilane (SiH4), and hydrogen (H2) by plasma-assisted CVD. This silicon nitride film may also be formed by sputtering or other method. - A
silicon oxide film 308 was deposited by plasma-assisted CVD, using TEOS and oxygen as gaseous raw materials or using monosilane and nitrous oxide as gaseous raw materials. The optimum thickness of thesilicon oxide film 110 varies, depending on the height of the gate electrode and gate wiring. For example, where the thickness of the gate electrode and gate wiring including the thickness of the silicon nitride film is about 6000 Å as in the present example, the optimum thickness of thelayer 308 is preferably one-third to 2 times this value, i.e., 2000 Å to 1.2 μm. In this example, the thickness was 6000 Å. In this film formation step, the film thickness of planar portions is required to be uniform. In addition, the step coverage must be good (FIG. 3(B) ). - This
silicon oxide film 308 was etched by anisotropic etching, using the well-known RIE process. This etching terminated at the surface of thesilicon nitride film 307. Since the silicon nitride film was not readily etched by anisotropic etching using the RIE process, the etching did not progress into the gate-insulatingfilm 304. By the manufacturing steps described thus far,side walls FIG. 3(C) ). - Then, phosphorus ions were introduced by ion doping techniques. The dose was 1×1014 to 5×1017 atoms/cm2. The accelerating voltage was 10 to 90 kV. For example, the dose was 2×1015 atoms/cm2. The accelerating voltage was 80 kV. As a result, source/
drain regions 311 doped with phosphorus were formed. Phosphorus was not introduced into regions located under the side walls. In this way, offset regions were created (FIG. 3(D) ). - The laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 nsec to activate the introduced dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2. Instead of the laser irradiation, thermal annealing may be effected.
- Finally, a silicon oxide film was deposited as an
interlayer insulator layer 312 to a thickness of 5000 Å over the whole surface by CVD. Contact holes were created in the source/drain regions of the TFT. The second aluminum layer formingaluminum wiring - A TFT having an N-channel offset region was completed by the manufacturing steps described thus far. In order to activate the doped regions, the laminate may be subsequently subjected to hydrogen annealing conducted at 200 to 400° C. The presence of the
side wall 310 makes milder the step at which thesecond wiring 314 goes over thegate wiring 306. Therefore, almost no wiring breakages were observed irrespective of the fact that the thickness of the wiring of the second layer is approximate to that of the gate electrode/wiring (FIG. 3(D) ). - The present example is illustrated in
FIGS. 5(A)-5(F) . In the present example, a TFT having an N-channel offset region and a TFT having an N-channel LDD region are formed on the same substrate. - First, in the same way as in Example 1, an
oxide film 502 acting as a buffer layer, a silicon semiconductor region in the form of islands, and asilicon oxide film 503 serving as a gate oxide film were formed on asubstrate 501.Gate electrodes silicon nitride film 506 was formed to a thickness of 100 to 2000 Å, e.g., 1000 Å, in the same way as in Example 1 (FIG. 5(A) ). - Thereafter, the offset TFT regions were masked with
photoresist 507. Under this condition, phosphorus ions were implanted into the TFT having the LDD region by ion doping, using the gate electrode as a mask. Thus, lightly doped N-type regions 508 were created. The dose was 1×1013 atoms/cm2, for example. - The laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 nsec to activate the introduced dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2 (
FIG. 5(B) ). - After removing the
mask 507 of the photoresist, asilicon oxide film 509 having a thickness of 4000 to 8000 Å, e.g., 6000 Å, was formed by plasma-assisted CVD (FIG. 5(C) ). - In the same way as in Example 1, the
silicon oxide film 509 was etched by anisotropic etching, in the same way as in Example 1.Side walls FIG. 5(D) ). - Then, phosphorus ions were implanted again by ion doping. In this case, the dose is preferably one to three orders of magnitude higher than the dose used in the step shown in
FIG. 5(B) . In the present example, the dose was 200 times as high as the dose of the initially implanted phosphorus, i.e., 2×1015 atoms/cm2. The accelerating voltage was 80 kV. As a result, source/drain regions FIG. 5(B) , an offset region was left under the side wall of the masked TFT. A lightly dopedregion 514 was left under the side wall of the TFT lightly doped with phosphorus. - Then, the laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 nsec to activate the introduced dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2 (
FIG. 5(E) ). - Finally, as shown in
FIG. 5(F) , silicon oxide was deposited as aninterlayer insulator layer 515 to a thickness of 3000 Å over the whole surface. Contact holes were created in the source/drain regions of the TFT. Aluminum wiring andelectrodes - The interlayer insulator layer was not very thick at the portion (not shown) at which the second wiring went over the gate wiring. However, almost no wiring breakages were observed in the same way as in Example 1.
- In the present example, the dopant was activated by laser irradiation whenever an implantation step was carried out. Alternatively, all activation steps may be simultaneously performed immediately after all the implantation steps were ended but before the interlayer insulator layer was formed.
- In the description made in connection with
FIGS. 5(A)-5(F) , only the N-channel TFT was described. A CMOS circuit may be constructed by forming both an N-channel TFT and a P-channel TFT on the same substrate, in the same way as in Example 2. For example, in a monolithic active matrix circuit comprising a substrate on which a peripheral circuit and an active matrix circuit are both formed, a CMOS circuit using an LDD N-channel TFT having a high operating speed and an ordinary NMOS TFT is used as the peripheral circuit. N- or P-channel offset TFTs are used as the active matrix circuit which is required to exhibit low leakage current. Especially, the P-channel offset TFT is effective in reducing the leakage current. Of course, both N- and P-channel types can be composed of LDD TFTs. - The present example is illustrated in
FIGS. 6(A)-6(F) . First, silicon oxide was formed as abuffer layer 602 on asubstrate 601 to a thickness of 1000 to 5000 Å, e.g., 2000 Å, in the same way as in Example 1. Then, in the same way as in Example 1, a silicon region in the form of islands was formed to a thickness of 500 Å. Silicon oxide was deposited as a gate-insulatingfilm 603 on the laminate to a thickness of 700 to 1500 Å, e.g., 1200 Å, by plasma-assisted CVD. - Then, a
gate electrode 604 and agate wiring 605 were formed out of an aluminum film having a thickness of 5000 Å. Furthermore, asilicon nitride film 606 was deposited to a thickness of 100 to 2000 Å, preferably 200 to 1000 Å, e.g., 500 Å, by plasma-assisted CVD. - Thereafter, using the gate electrode as a mask, an impurity (in this example, phosphorus) was implanted into the silicon film in the form of islands by self-aligned. implantation techniques. In this way, lightly doped
regions 607 were formed, as shown inFIG. 6(A) . The dose was 1×1013 to 5×1014 atoms/cm2. The accelerating voltage was 10 to 90 kV. For example, the dose was 5×1013 atoms/cm2. The accelerating voltage was 80 kV (FIG. 6(A) ). - A
silicon oxide film 608 was deposited by plasma-assisted CVD. The thickness was 6000 Å. In this film formation step, the film thickness of planar portions is required to be uniform. In addition, the step coverage must be good (FIG. 6(B) ). - Then, an anisotropic dry etching step was conducted, using CHF3 to etch the
silicon oxide film 608. At this time, the etching can be performed until it goes to thesilicon nitride film 606. Preferably, as shown inFIG. 6(C) , the etching is stopped immediately before the etching reaches thesilicon nitride film 606 so that a slight amount of thesilicon oxide film 608 is left behind. Substantially triangular regions of insulator, orside walls FIG. 6(C) ). - Subsequently, a dry etching step was carried out, using CH4 and O2 to etch away the slight amount of silicon oxide film left on the silicon nitride film, as well as the silicon nitride film. Since this etching, step can be monitored with an endpoint monitor (plasma monitor), the gate electrode and the gate-insulating film are prevented from being overetched (
FIG. 6(D) ). - Then, phosphorus ions were implanted again by ion doping. In this case, the dose is preferably one to three orders of magnitude higher than the dose used in the step shown in
FIG. 6(A) . In the present example, the dose was 40 times as high as the dose of the initially implanted phosphorus, i.e., 2×1015 atoms/cm2. The accelerating voltage was 80 kV. As a result, source/drain regions 611 heavily doped with phosphorus were created. Lightly dopedregions 612 were left under the side walls. - Then, the laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 nsec to activate the introduced dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2 (
FIG. 6(E) ). - Finally, a silicon oxide film was deposited as an
interlayer insulator layer 613 to a thickness of 5000 Å over the whole surface by CVD. Contact holes were created in the source/drain regions of the TFT. The second aluminum layer formingaluminum wiring - A TFT having an N-channel offset region was completed by the manufacturing steps described thus far. In order to activate the doped regions, the laminate may be subsequently subjected to hydrogen annealing conducted at 200 to 400° C. In the same way as in Example 1, the presence of the
side wall 610 makes milder the step at which thesecond wiring 613 goes over thegate wiring 605. Therefore, almost no wiring breakages were observed irrespective of the fact that the thickness of the wiring of the second layer is approximate to that of the gate electrode/wiring (FIG. 6(F) ). - In the present example, the
silicon nitride film 606 was etched, and the gate-insulatingfilm 603 was exposed. This enabled contact holes to be formed in one operation, i.e., wet etching process. As can be seen fromFIG. 6(E) , as a result of the etching of the silicon nitride film, the silicon nitride film was left only between thegate electrode side walls film 603 and theside walls - The present example is illustrated in
FIGS. 7(A)-7(F) . In the present example, in the same way as in Example 2, an LDD N-channel TFT and an ordinary P-channel TFT are formed on the same substrate. The left sides ofFIGS. 7(A)-7(F) are cross sections of an N-channel TFT, illustrating the process sequence for fabricating the TFT. The right sides ofFIGS. 7(A)-7(F) are cross sections of a P-channel TFT, illustrating the process sequence for fabricating the TFT. First, anoxide film 702 acting as a buffer layer, a silicon semiconductor layer in the form of islands, and asilicon oxide film 703 acting as a gate oxide film were formed on asubstrate 701 made of Corning 7059 glass. Then,gate electrodes - Then, using the
gate electrode 704 as a mask, the gate oxide film in the portion of the N-channel TFT was selectively removed to expose the semiconductor layer. Subsequently, asilicon nitride film 706 having a thickness of 100 to 2000 Å, preferably 200 to 1000 Å, e.g., 400 Å, was formed by plasma-assisted CVD. - Using the gate electrode as a mask, phosphorus ions were implanted by ion doping to form lightly doped N-
type regions 707. The dose was 1×1013 atoms/cm2. The accelerating voltage was 20 keV. During this doping process, the accelerating voltage was low. Therefore, phosphorus ions were not implanted into theislands 708 of the P-channel TFT coated with the gate oxide film 703 (FIG. 7(A) ). - Then, the N-channel TFT regions was masked with
photoresist 709. Under this condition, boron ions were implanted at a high concentration by ion doping. The dose was 5×1014 atoms/cm2. The accelerating voltage was 65 kV. As a result, P-type dopedregions 710 were formed in the islands 708 (FIG. 7(B) ). - In the present example, after the whole surface was lightly doped with phosphorus, the surface was selectively heavily doped with boron. The sequence in which these two steps are carried out may be reversed.
- After removing the
photoresist mask 709, asilicon oxide film 711 having a thickness of 4000 to 8000 Å was formed by plasma-assisted CVD (FIG. 7(C) ). - Then,
side walls FIG. 7(D) ). - Then, phosphorus ions were introduced again by ion doping. In this case, the dose is preferably one to three orders of magnitude higher than the dose used in the step shown in
FIG. 7(A) . In the present example, the dose was 200 times as high as the dose of the initially implanted phosphorus, i.e., 2×1015 atoms/cm2. The accelerating voltage was 20 kV. As a result, source/drain regions 714 heavily doped with phosphorus were created. Lightly dopedregions 715 were left under the side walls. - On the other hand, the P-channel region was not doped with phosphorus ions because of the presence of the gate oxide film. In Example 2, the P-channel TFT was doped heavily with both phosphorus ions and boron ions and so the limitations are imposed on the their doses. In the present example, no limitations are placed on the doses. However, with respect to the accelerating voltage, it must be set low for phosphorus ions and set high for boron ions (
FIG. 7(E) ). - Then, the laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 nsec to activate the introduced dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2.
- Finally, as shown in
FIG. 7(F) , silicon oxide was deposited as aninterlayer insulator layer 716 to a thickness of 5000 Å over the whole surface by CVD. Contact holes were created in the source/drain regions of the TFTs. Aluminum electrodes andaluminum wiring - Compared with Example 2, the present example further needs a photolithography step and an etching step to remove the gate oxide film from the N-channel TFT portion. However, substantially no N-type impurity was implanted into the P-channel TFT and, therefore, the doses of the N-type and P-type impurities can be relatively arbitrarily changed.
- The phosphorus ions were implanted into the portions close to the surface of the
gate oxide film 703 of the P-channel TFT. The phosphorus ions will form phosphosilicate glass in the later laser irradiation step. - This is effective in preventing movable ions such as sodium ions from entering.
- The present example is illustrated in
FIGS. 8(A)-8(G) . The present example relates to a method of fabrication of an active matrix liquid crystal display. This method is now described by referring toFIGS. 8(A)-8(G) . Two TFTs located at the left sides ofFIGS. 8(A)-8(G) are composed of an LDD N-channel TFT and an ordinary P-channel TFT, respectively. These TFTs are logic circuits used in a peripheral circuit or the like. The TFT shown at the right is a switching transistor used in an active matrix array. The right TFT is an offset P-channel TFT. - First, an oxide film acting as a buffer layer, a silicon semiconductor region in the form of islands, and a
silicon oxide film 803 acting as a gate oxide film were formed on a substrate made of Corning 7059 glass. The silicon semiconductor region in the form of islands is composed of anisland region 801 for a peripheral circuit and anisland region 802 for an active matrix circuit.Gate electrodes gate electrode 806 for the active matrix circuit was formed out of the aluminum film. - Then, using the
gate electrodes silicon nitride film 808 having a thickness of 100 to 2000 Å, preferably 200 to 1000 Å, e.g., 600 Å, was formed by plasma-assisted CVD. - The active matrix circuit region was masked with
photoresist 807. Using thegate electrode 804 as a mask, phosphorus ions were implanted by ion doping to form heavily doped P-type regions 809. The dose was 1×1015 atoms/cm2. The accelerating voltage was 20 keV. During this doping process, the accelerating voltage was low. Therefore, phosphorus ions were not implanted into the N-channel TFT regions coated with the gate oxide film 803 (FIG. 8(A) ). - Then, phosphorus ions were implanted at a low concentration by ion doping. The dose was 1×1013 atoms/cm2. The accelerating voltage was 80 kV. As a result, lightly doped N-
type regions 810 were created in the regions of the N-channel TFTs (FIG. 8(B) ). - In the illustrated example, the ions were implanted after removing the
photoresist mask 807. The ion implantation may be made while leaving the photoresist. Since the phosphorus ions are accelerated at a high voltage, if ion implantation is done while leaving the photoresist, then the phosphorus ions are not implanted into the active matrix circuit regions. Therefore, ideal offset P-channel TFTs are obtained. However, as a result of the ion implantation, the photoresist is carbonized. It may be laborious to remove this carbonized photoresist. - Even if the photoresist is removed, the phosphorus concentration exhibits peaks under the semiconductor region in the form of islands, because the accelerating voltage for phosphorus is high. However, it is not assured that phosphorus ions are not implanted at all. Rather, a trace amount of phosphorus is introduced into the semiconductor region. Even if phosphorus is implanted in this way, the concentration is quite low. Furthermore, a structure given by P+ (source), N−, I (channel)/N−, P+ (drain) is formed. This is best suited for a TFT for an active matrix circuit that is required to reduce its leakage current.
- Then, a silicon oxide film was deposited to a thickness of 4000 to 8000 Å by plasma-assisted CVD.
Side walls FIG. 8(C) ). - Thereafter, boron ions were again implanted by ion doping. In this case, the dose is preferably approximate to the dose used in the step illustrated in
FIG. 8(A) . In the present example, the dose was 1×1015 atoms/cm2. The accelerating voltage was 20 keV. Since the accelerating voltage was low, the boron ions were not implanted into the N-channel TFT regions on which thegate oxide film 803 existed. The boron ions were chiefly implanted into the source/drain regions of the P-channel TFTs of the peripheral circuit and of the active matrix circuit. As a result, source/drain regions 814 of the TFT of the active matrix circuit were created. In each of these TFTs, the gate electrode is remote from the source/drain regions, i.e., the offset structure (FIG. 8(D) ). - Then, phosphorus ions were implanted. Preferably, the dose is one to three orders of magnitude higher than the dose used in the step illustrated in
FIG. 8(B) . In the present example, the dose was 50 times as high as the dose of the phosphorus ions first implanted, i.e., 5×1014 atoms/cm2. The accelerating voltage was 80 kV. As a result,regions 815 heavily doped with phosphorus were created. Lightly doped drain (LDD)regions 816 were formed under the side walls. - On the other hand, in the P-channel TFT regions, many of the phosphorus ions were implanted into the buffer layer. The conductivity type was not affected greatly (
FIG. 8(E) ). - After the ion implantation, the laminate was irradiated with KrF excimer laser light having a wavelength of 248 nm and a pulse width of 20 nsec to activate the implanted dopant. The energy density of the laser light was 200 to 400 mJ/cm2, preferably 250 to 300 mJ/cm2.
- Then, as shown in
FIG. 8(F) , silicon oxide was deposited as a firstinterlayer insulator layer 817 to a thickness of 5000 Å over the whole surface by CVD. Contact holes were created in the source/drain regions of the TFTs. Aluminum electrodes andaluminum wiring - Silicon oxide was deposited as a second
interlayer insulator layer 822 to a thickness of 3000 Å by CVD. This was etched, and contact holes were created.Pixel electrodes 823 were formed out of transparent conductive film in TFTs of an active matrix circuit. In this way, an active matrix liquid crystal display device was fabricated (FIG. 8(G) ). - In the present invention, the thickness of the second wiring can be made to approximate the thickness of the gate electrodes and gate wiring. More specifically, the thickness of the second wiring can be equal to the thickness of the gate electrodes and gate wiring ±1000 Å. This is well suited to an active matrix circuit for a liquid crystal display whose plates are required to be less uneven.
- While the preferred embodiments of the invention have been described, it is to be understood that various modifications may be made by those ordinary skilled in the art. For example, before forming a silicon nitride film on a gate electrode, it is possible to form an oxide layer on the gate electrode by anodic oxidation.
Claims (16)
1. A SOI integrated circuit comprising:
a first insulating film formed over a semiconductor substrate;
an n-channel transistor formed over the first insulating film, the n-channel transistor comprising:
a first semiconductor film including a first channel formation region, first source and drain regions, and lightly doped regions between the first channel formation region and the first source and drain regions formed over the first insulating film;
a first gate insulating film formed over the first semiconductor film;
a first gate electrode formed over the first gate insulating film;
first side walls formed adjacent to side surfaces of the first gate electrode; and
a second insulating film interposed between the first side walls and the side surfaces of the first gate electrode, and extending below the first side walls; and
a p-channel transistor formed over the first insulating film, the p-channel transistor and the second-type transistor comprising:
a second semiconductor film including a second channel formation region, and second source and drain regions formed over the first insulating film;
a second gate insulating film formed over the second semiconductor film;
a second gate electrode formed over the second gate insulating film; and
second side walls formed adjacent to side surfaces of the second gate electrode; and
a third insulating film interposed between the second side walls and the side surfaces of the second gate electrode, and extending below the second side walls,
wherein the lightly doped regions of the n-channel transistor overlaps with the first side walls of n-channel transistor.
2. A SOI integrated circuit comprising:
a first insulating film formed over a semiconductor substrate;
an n-channel transistor formed over the first insulating film, the n-channel transistor comprising:
a first semiconductor film including a first channel formation region, first source and drain regions, and first lightly doped regions between the first channel formation region and the first source and drain regions formed over the first insulating film;
a first gate insulating film formed over the first semiconductor film;
a first gate electrode formed over the first gate insulating film;
first side walls formed adjacent to side surfaces of the first gate electrode; and
a second insulating film interposed between the first side walls and the side surfaces of the first gate electrode, and extending below the first side walls; and
a p-channel transistor formed over the first insulating film, the p-channel transistor and the second-type transistor comprising:
a second semiconductor film including a second channel formation region, second source and drain regions, and second lightly doped regions between the second channel formation region and the second source and drain regions formed over the first insulating film;
a second gate insulating film formed over the second semiconductor film;
a second gate electrode formed over the second gate insulating film; and
second side walls formed adjacent to side surfaces of the second gate electrode; and
a third insulating film interposed between the second side walls and the side surfaces of the second gate electrode, and extending below the second side walls,
wherein the first lightly doped regions of the n-channel transistor overlaps with the first side walls of n-channel transistor, and
wherein the second lightly doped regions of the p-channel transistor overlaps with the second side walls of p-channel transistor.
3. A SOI integrated circuit according to claim 1 , wherein an impurity concentration of the lightly doped region of the n-channel transistor is smaller than that of the first source and drain regions of the n-channel transistor.
4. A SOI integrated circuit according to claim 2 ,
wherein an impurity concentration of the first lightly doped region of the n-channel transistor is smaller than that of the first source and drain regions of the n-channel transistor, and
wherein an impurity concentration of the second lightly doped region of the p-channel transistor is smaller than that of the second source and drain regions of the p-channel transistor.
5. A SOI integrated circuit according to claim 1 , wherein each of the second insulating film and the third insulating film is a silicon nitride film.
6. A SOI integrated circuit according to claim 2 , wherein each of the second insulating film and the third insulating film is a silicon nitride film.
7. A SOI integrated circuit according to claim 1 , wherein each of the first side walls and the second side walls is formed by a silicon oxide film.
8. A SOI integrated circuit according to claim 2 , wherein each of the first side walls and the second side walls is formed by a silicon oxide film.
9. A SOI integrated circuit according to claim 1 ,
wherein an etching rate of the second insulating film is different from that of the first side walls and,
wherein an etching rate of the third insulating film is different from that of the second side walls.
10. A SOI integrated circuit according to claim 2 ,
wherein an etching rate of the second insulating film is different from that of the first side walls and,
wherein an etching rate of the third insulating film is different from that of the second side walls.
11. A SOI integrated circuit according to claim 1 , wherein each of the second insulating film and the third insulating film is an etching stopper film.
12. A SOI integrated circuit according to claim 2 , wherein each of the second insulating film and the third insulating film is an etching stopper film.
13. A SOI integrated circuit according to claim 1 , further comprising:
a fourth insulating film formed over the n-channel transistor and p-channel transistor.
14. A SOI integrated circuit according to claim 2 , further comprising:
a fourth insulating film formed over the n-channel transistor and p-channel transistor.
15. A SOI integrated circuit according to claim 13 , wherein the fourth insulating film is a silicon oxide film.
16. A SOI integrated circuit according to claim 14 , wherein the fourth insulating film is a silicon oxide film.
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US08/450,953 US5914498A (en) | 1994-05-26 | 1995-05-23 | Semiconductor integrated circuit and method of fabricating same |
US09/291,292 US6559478B1 (en) | 1994-05-26 | 1999-04-14 | Semiconductor integrated circuit and method of fabricating same |
US10/424,665 US7122833B2 (en) | 1994-05-26 | 2003-04-29 | Semiconductor integrated circuit and method of fabricating same |
US11/526,794 US7528406B2 (en) | 1994-05-26 | 2006-09-26 | Semiconductor integrated circuit and method of fabricating same |
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US20110254089A1 (en) * | 1994-05-26 | 2011-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor integrated circuit and method of fabricating same |
US20080308830A1 (en) * | 1998-11-02 | 2008-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method therefor |
US7863622B2 (en) | 1998-11-02 | 2011-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method therefor |
US7952101B2 (en) | 2001-06-20 | 2011-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US7122833B2 (en) | 2006-10-17 |
US7968886B2 (en) | 2011-06-28 |
JPH07321338A (en) | 1995-12-08 |
US7528406B2 (en) | 2009-05-05 |
US20030183821A1 (en) | 2003-10-02 |
US20110254089A1 (en) | 2011-10-20 |
US6559478B1 (en) | 2003-05-06 |
US5914498A (en) | 1999-06-22 |
US20070018167A1 (en) | 2007-01-25 |
JP3256084B2 (en) | 2002-02-12 |
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