US20090021273A1 - On-wafer test structures - Google Patents
On-wafer test structures Download PDFInfo
- Publication number
- US20090021273A1 US20090021273A1 US12/283,984 US28398408A US2009021273A1 US 20090021273 A1 US20090021273 A1 US 20090021273A1 US 28398408 A US28398408 A US 28398408A US 2009021273 A1 US2009021273 A1 US 2009021273A1
- Authority
- US
- United States
- Prior art keywords
- signal
- differential
- probe pad
- probe
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
Definitions
- the present invention relates to integrated circuits and, more particularly to, test structures and methods for on-wafer inspection of integrated circuits and other microelectronic devices.
- Integrated circuits comprise an arrangement of basic passive and active circuit elements, such as transistors, resistors and capacitors that are fabricated on a substrate or wafer.
- ICs are fabricated by a process of successively depositing layers of semi-conductive, conductive or insulating materials on the wafer and selectively etching portions of the deposited material. Deposition of a semi-conductor, conductor or insulator is followed by deposition of a layer of photosensitive material. The photosensitive material is exposed to light, through a precisely aligned mask, causing portions of the material to be chemically altered. Portions of the exposed photosensitive material are removed producing a photoresist layer with a pattern corresponding to the mask.
- a chemical etchant applied to the surface, selectively removes the underlying semi-conductive, conductive or insulating layer except in those areas which are protected by the remaining photoresist.
- the remaining portions of the semi-conductor, conductor or insulator comprise a layer of one or more of the stratified, passive or active circuit elements.
- the photoresist layer is removed from the exposed surface of the wafer and the process is repeated until all of the strata of the circuit's elements have been laid down.
- a plurality of dies 22 are formed on the surface of a wafer or substrate 20 .
- the individual dies are separated or singulated, typically by sawing the wafer along scribe or saw streets (indicated by a bracket) 24 between the dies.
- Each die containing a marketable integrated circuit is encased in a package and electrical connections are provided between the exterior of the package and the integrated circuit on the enclosed die.
- the separation and packaging of a die comprises a significant portion of the cost of manufacturing an integrated circuit device.
- manufacturers commonly add electrical circuits or test structures 26 to the wafer that enable on-wafer inspection before the dies are singulated.
- a wafer typically includes a plurality of test structures 26 that are distributed about the surface of the wafer enabling a portion of the wafer containing a defect to be isolated and identified by the testing.
- a test structure 40 typically comprises a device under test (DUT) 42 , a plurality of bond or probe pads 44 and a plurality of vias 46 connecting the probe pads on the surface of the substrate 20 to the circuit elements of the DUT which are typically fabricated beneath the surface.
- a DUT typically comprises a simple circuit that includes a copy of one or more of the basic elements of the marketable integrated circuit, such as a single line of conducting material, a chain of vias or a single transistor.
- the circuit elements of the DUT are typically produced with the same process and in the same layers of the wafer as corresponding elements of the marketable ICs.
- the marketable ICs are typically characterized “on-wafer” by applying a test instrument generated signal to the test structure and measuring the response of the test structure to the signal. Since the circuit elements of the DUT are fabricated with the same process as the corresponding elements of the integrated circuit, the electrical properties of the DUT are expected to be representative of the electrical properties of the corresponding components of the marketable ICs.
- ground referenced signaling that is referenced a ground plane, typically, at the lower surface of the substrate on which the active and passive devices of the circuit are fabricated.
- parasitic interconnections exist between many of the parts of the individual devices and between parts of the devices and the wafer on which the devices are fabricated.
- These interconnections are commonly capacitive and/or inductive in nature and have frequency dependent impedances.
- the terminals of transistors fabricated on semi-conductive substrates or wafers are typically capacitively interconnected, through the substrate, to the ground plane.
- the impedance of this parasitic capacitive interconnection is frequency dependent and at higher frequencies the ground potential and the true nature of ground referenced signals becomes uncertain.
- a differential gain cell 50 is a balanced device comprising two nominally identical circuit halves 50 A, 50 B.
- the transistors 52 of the differential gain cell are biased with a dc voltage, for example from a current source 54 , and stimulated with a differential mode signal, comprising even (S i +1 ) and odd (S i ⁇ 1 ) mode components of equal amplitude and opposite phase, a virtual ground is established at the symmetrical axis 56 of the two circuit halves. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the stimulating signal.
- the quality of the virtual ground of a balanced device is independent of the physical ground path and, therefore, balanced or differential circuits can tolerate poor RF grounding better than circuits operated with single ended signals.
- the two waveforms of the differential output signal (S o +1 and S o ⁇ 1 ) are mutual references providing faster and more certain transitioning from one binary value to the other for digital devices and enabling operation with a reduced voltage swing for the signal.
- balanced or differential circuits have good immunity to noise, including noise at even-harmonic frequencies, because noise from external sources, such as adjacent conductors, tends to couple, electrically and electromagnetically, in the common mode and cancel in the differential mode and signals that are of opposite phase at the fundamental frequency are in phase at the even harmonics.
- a differential gain cell is a common elemental device of differential or balanced circuits and a test structure comprising a differential gain cell enables on wafer testing and characterization of differential devices included in marketable ICs fabricated on the wafer.
- test structures are often fabricated on areas of the wafer that could otherwise be occupied by one or more dies containing the marketable integrated circuits.
- manufacturers face continuous pressure to reduce the cost of IC devices by increasing the number of dies fabricated on a wafer. Since the test structures serve no purpose after the dies are singulated, manufacturers have sought to locate the test structures in the saw streets between dies and, at the same time, to reduce the width of the saw streets to maximize utilization of the substrate's surface area.
- test structures incorporating balanced devices typically require large areas of the wafer's surface because five probe pads 80 , 82 , 84 , 86 , 88 are required to sink and source the four differential signal components and bias the device.
- Two probes 60 , 62 are required to facilitate simultaneous engagement of five probe pads with five probe tips 70 , 72 , 74 , 76 , 78 .
- the probe pads of a differential test structure are typically arranged around the perimeter of the area in which the DUT is fabricated enabling a probe to be positioned on either side of the test structure.
- the size and separation of the individual probe pads are dictated by the need to co-locate the probe pads and the probe tips during testing and avoid interference between the adjacent conductors. Likewise, facilitating engagement of the probe pads with two probes and avoiding crosstalk between the two closely located probes dictates the separation between the rows of probe pads on either side of the test structure. However, locating two sets of interconnected probe pads in a saw street for simultaneous engagement by two probes that are relatively large compared to the features on the wafer has proven to be difficult.
- test structure including a DUT useful for testing integrated circuits comprising differential or balanced devices which can be fabricated in the saw streets between dies on a wafer or substrate.
- FIG. 1 is a top view of an exemplary wafer on which integrated circuits are fabricated.
- FIG. 2 is a perspective view of a portion of a substrate comprising a test structure including a differential gain cell and a fragmentary representation of two probes arranged to probe the test structure.
- FIG. 3 is a schematic illustration of a probe measurement system for testing a differential test structure.
- FIG. 4 is a perspective view of a portion of a substrate comprising a differential test structure including a linear array of probe pads.
- FIG. 5 is a schematic illustration of a second embodiment of a differential test structure including a linear array of probe pads .
- FIG. 6 is a schematic illustration of a third embodiment of a differential test structure including a linear array of probe pads .
- FIG. 7 is a schematic illustration of a fourth embodiment of a differential test structure including a linear array of probe pads.
- FIG. 8 is a schematic illustration of a Gilbert cell.
- FIG. 9 is a top view of a portion of wafer including a pair of differential test structures fabricated at an intersection of two saw streets.
- FIG. 10 is a top view of a portion of wafer including another pair of differential test structures fabricated at an intersection of two saw streets.
- FIG. 11 is a top view of a portion of wafer including an additional embodiment of a differential test structure fabricated at an intersection of two saw streets.
- the expected operation of integrated circuits is commonly predicted by on-wafer characterization.
- the characterization is commonly performed by stimulating a test structure with a signal generated by a test instrument and measuring the signal produced in response to the stimulation.
- the test structure typically comprises a device-under-test (DUT) conductively connected to a plurality of probe or bond pads located on the surface of the wafer on which the marketable ICs are fabricated.
- the DUT typically comprises a relatively simple circuit that includes one or more active or passive circuit elements that correspond to circuit elements included in the marketable ICs.
- Much of the circuitry of the DUT is typically fabricated below the surface of the wafer with the same process of successive deposition and etching of layers of conductive, semi-conductive and insulating materials that is used to fabricate the corresponding components of the marketable ICs. Since the components of the DUT are fabricated with the same process that is used to produce the components of the marketable ICs, it is anticipated that the operation of the DUT, when stimulated by the test signal, will be representative of the operation of the corresponding components of the ICs if stimulated by a similar signal.
- Interconnections between the test instrumentation and the DUT commonly exhibit frequency dependent electrical characteristics or parasitics which must be accounted for, particularly, at high frequencies, if the operation of the DUT is to be determined accurately.
- the probes that commonly enable temporary connection of the instrumentation to the test structure typically comprise a plurality of interconnected transmission lines of differing types and each transition can produce a frequency dependent effect on the signal.
- vias connecting the probe pads, deposited at the surface of the wafer, to the components of the DUT, located below the wafer's surface have a finite inductance. As a result, the admittances of the vias are frequency dependent and must be accounted for to enable accurate measurement of the DUT's operation.
- test instrumentation in which the test instrumentation is used to stimulate and measure the response of a plurality of known sample test structures is widely used to mathematically account for these effects so that the signals at the input and output terminals of the DUT can be accurately assessed.
- Integrated circuits are commonly unbalanced devices that utilize single ended (ground referenced) signals.
- the lower surface of the wafer serves as the ground plane for the circuit devices, including devices in a test structure, that are fabricated on the upper surface of the substrate.
- the terminals of circuit elements fabricated on semi-conductive substrates are capacitively interconnected through the substrate to the substrate's lower surface.
- the impedance of the capacitive interconnections to the circuit's ground plane varies with frequency producing uncertainty concerning the ground potential and, therefore, the true nature of the single ended signals at the terminals of the DUT particularly at higher frequencies, such as radio frequencies (RF).
- RF radio frequencies
- a differential gain cell 50 a balanced device, comprises two nominally identical circuit halves 50 A, 50 B.
- a source such as a current source 54 or another potential referenced to ground
- a differential mode signal comprising even (S i +1 ) and odd (S i ⁇ 1 ) mode components of equal amplitude and opposite phase
- a virtual ground is established at the symmetrical axis 56 of the two circuit halves.
- the potential at the operating frequency does not change with time regardless of the amplitude of the stimulating signal.
- the quality of the virtual ground of a balanced device is independent of the physical ground path and, therefore, balanced or differential circuits can tolerate poor radio frequency (RF) grounding better than circuits operated with single ended signals.
- RF radio frequency
- noise from external sources, such as adjacent conductors tends to couple, electrically and electromagnetically, in the common mode and cancel in the differential mode.
- balanced or differential circuits have good immunity to noise including noise at even-harmonic frequencies since signals that are of opposite phase at the fundamental frequency are in phase at the even harmonics.
- a test structure comprising a balanced device is typically relatively large to accommodate at least five probe pads 80 , 82 , 84 , 86 , 88 and probing with two probes.
- test structure comprising a balanced or differential device could be fabricated in a saw street between dies and probed with a single probe the area of the surface of the substrate that is useable for fabricating marketable ICs could be substantially increased, reducing the cost of fabricating and testing ICs that utilize differential signaling.
- the test structure 100 comprises a DUT 102 that includes a differential gain cell 104 that is responsive to a differential input signal.
- the differential input signal comprises an even mode component (S i +1 ) and an odd mode component (S i ⁇ 1 ) that has substantially the same amplitude as the even mode component but which is opposite in phase of the even mode component.
- the differential gain cell 104 comprises two substantially identical field effect (JFET) transistors 106 A and 106 B.
- JFET substantially identical field effect
- a DUT typically comprises components corresponding to the components utilized in the marketable integrated circuits fabricated on the wafer and, referring to FIGS.
- differential gain cells comprising pairs of transistors are common elementary devices used in differential circuitry and, referring to FIG. 8 , differential gain cells 402 comprising pairs of transistors are commonly used in more complex circuits such as a Gilbert cell 400 .
- the source terminals of the transistors 106 A and 106 B are interconnected as a bias terminal 110 of the differential gain cell.
- the bias terminal is interconnected to a centrally located bias probe pad 120 .
- the bias probe pad is interconnected, typically through a contact tip 130 of a probe, to a source of DC voltage, for example a ground 140 or a current mirror, which provides the DC bias for the transistors of the differential gain cell.
- the gates of the transistors comprise a first pair of signal terminals 116 , 118 of the DUT and are connected to respective signal probe pads 126 , 128 which are, in turn, connectible, typically through respective contact tips 136 , 138 of a probe, to a test instrument 146 , typically a network analyzer.
- the drains of the transistors of the differential gain cell comprise a second pair of signal terminals 112 , 114 of the DUT which are interconnected to respective probe pads 122 , 124 . These probe pads are connectible, typically, through contact tips 132 , 134 of a probe to the test instrument.
- the test instrument comprises, generally, a source 142 of a differential input signal to the DUT comprising an even mode component, S i +1 , and an odd mode component, S i ⁇ 1 ; a sink 144 for the differential output signal of the DUT comprising an even mode component, S o +1 , and an odd mode component, S o ⁇ 1 .
- a reversing switch 148 enables reversing the connections between the test instrument's differential signal source and sink and the respective pairs of signal probe pads.
- the components of the differential input signals (S i +1 and S i ⁇ 1 ) are applied to probe pads 126 and 128 and sunk at the terminals 116 and 118 of the DUT and the output signals (S o +1 and S o ⁇ 1 ) are sourced from the terminals 112 and 114 through the probe pads 122 and 124 .
- the input signals (S i +1 and S i ⁇ 1 ) can be applied to probe pads 122 and 124 sinking the input signals at terminals 112 and 114 .
- the output signal components (S o +1 and S o ⁇ 1 ) are sourced from terminals 116 and 118 and transmitted from probe pads 126 and 128 to the sink of the test instrument.
- the operation of the test structure is typically tested by launching a differential input signal to one pair of signal terminals of the differential gain cell and capturing the differential and common mode output signals transmitted, in response to the input signal, from the other pair of signal terminals.
- test structure 40 can be fabricated in an area that could otherwise be occupied by one or more marketable ICs, the area required for the probe pads is too large to make locating the test structure in a saw street practical.
- the inventors concluded that a differential test structure could be fabricated in a saw street between dies on a wafer by arranging the four signal probe pads of the structure in a linear array such that the probe pads could be contacted by respective probe tips of a movable probe.
- the probe tips have contact areas with centroids arranged in a substantially straight line.
- signal transmission for the test structure would benefit from a substantially symmetrical arrangement of signal probe pads in relation to one or more bias probe pads which may also be included in the linear array of probe pads. Referring to FIG.
- the test structure 150 can be fabricated in an area of the wafer that would otherwise be occupied by a die containing a marketable IC. However, advantageously, the test structure 150 may be fabricated in a saw street 24 (indicated by a bracket) bounded by dies 182 , 184 fabricated on a substrate 20 . Typically, the DUT 152 is relatively small and comprises circuit elements that are fabricated beneath the final surface of the wafer.
- probe pads 160 , 162 , 164 , 166 , and 168 through which the DUT is biased and through which the differential signals are communicated to and from the DUT are arranged in a linear array with each probe pad of the array located proximate at least one other probe pad of the array and with the centroids of the probe pads being arranged in a substantially straight line.
- the probe pads of the test structure comprise a linear array of two pairs of signal probe pads; a pair of input/output probe pads 166 , 168 and a pair of output/input probe pads 162 , 164 ; that are arranged substantially symmetrical with one or more bias probe pads.
- the linear array of probe pads enables placement of the test structure in a saw street only slightly wider than the probe pads.
- the probe pads are accessible with a single movable probe 188 having a plurality of contact tips 190 arranged to be co-locatable with respective probe pads and having contact points or areas with centroids arranged in a substantially straight line.
- the probe pads are conductively connected to respective terminals of the DUT by vias 186 that extend from the surface of the wafer to the subsurface strata in which the circuit elements of the DUT are fabricated.
- the modes of the input and output signals at adjacent probe pads are the same. For example, sinking the even mode input signal (S i +1 ) at the probe pad 126 causes the even mode output signal (S o +1 ) to be transmitted from probe pad 122 .
- the mode of the input and output signals at adjacent probe pads are inverted.
- the even mode output signal (S o ⁇ 1 ) is transmitted from probe pad 268 adjacent to probe pad 264 and the odd mode output signal (S o ⁇ 1 ) is transmitted from the probe pad 266 adjacent to probe pad 262 .
- the gates of the transistors 252 B, 252 A of the DUT 251 are connected, respectively, to the second signal terminal 272 and the third signal terminal 274 .
- the drain of the transistor 252 B is connected to the fourth signal terminal 278 which is interconnected to probe pad 268 and the drain of transistor 252 A is connected to the first signal terminal 276 and probe pad 266 .
- the modes of the input and output signals at adjacent probe pads are inverted.
- the additional embodiment comprises a DUT 302 including a differential gain cell comprising matched BJT transistors 304 A, 304 B.
- the gates of the transistors comprise the first and fourth differential signal terminals 326 , 328 of the DUT and are conductively interconnected to respective probe pads 316 , 318 through which a differential mode signal can be sunk or sourced.
- a differential signal can be respectively sourced or sunk through the probe pads 312 and 314 which are interconnected, respectively, to the second and third signal terminals 322 and 328 of the DUT comprising the respective collectors of the differential cell transistors.
- the interconnected emitters of the two transistors comprise the bias terminal 320 of the DUT.
- Bias is provided to the differential gain cell at a centrally located probe pad 310 that is interconnected to the bias terminal.
- the bias terminal is also conductively interconnected to a pair of probe pads 332 , 334 that are located at the respective ends of the linear array of probe pads and which are connectable, through respective probe tips 338 , to the source of DC bias 336 for the DUT.
- the additional DC biased probe pads at the respective ends of the linear array of probe pads improve the symmetry of the electromagnetic fields and reduce the crosstalk between the signal probe pads and the centrally located bias probe pad.
- an additional embodiment of the differential test structure 350 comprises a linear array of six probe pads 352 , 354 , 356 , 358 , 362 , 364 .
- the differential input and output signals are conducted to and from the signal probe pads 352 , 354 which are interconnected to the first pair of signal terminals 322 , 324 connected to the collectors of the transistors 304 A and 304 B of the DUT 351 and signal probe pads 356 , 358 which are interconnected to the second pair of signal terminals 326 , 328 connected to the bases of the transistors.
- the emitters of the transistors are connected to the bias terminal 320 of the cell which is in turn connected to bias probe pads 362 , 364 at the extremes of the linear array of probe pads.
- the DC biased probe pads at the respective ends of the linear array of probe pads provide symmetry in the electromagnetic fields and the centrally located bias probe pad is eliminated reducing the length of the linear array of probe pads.
- the test structures can be further concentrated by locating the linear arrays of probe pads at the intersections of saw streets 24 between dies 22 on a wafer 20 .
- the linear arrays 500 of probe pads comprise up to seven probe pads with a central bias probe pad 502 located between two pairs of signal probe pads 504 , 506 .
- the bias probe pad located in the intersection of the saw streets 24 can be common to a DUT 508 in the north-south saw street and a DUT 510 located in the east-west saw street because the probe tips 514 of the probe 512 are arranged supply signals to only one set of signal probe pads at a time.
- the probe pads of the test structures can include additional bias probe pads 516 at each end of each linear array of probe pads. Referring to FIG.
- linear arrays of six probe pads 550 comprising two pairs of signal probe pads 552 , 554 and a pair of bias probe pads 556 , 558 , one located at each end to the array, can be fabricated in the intersection of the east-west and north-south streets 24 .
- the bias probe pad 556 in the intersection can be connected to each of the four DUTs 570 , 572 , 574 , 576 in the streets leading to the intersection because the probe tips 562 of probe 560 will supply signals to the signal probe pads of only one array of probe pads at a time.
- FIG. 11 illustrates another embodiment of a compact differential test structure 600 fabricated at the intersection of saw streets 24 A and 24 B (indicated by brackets) separating a plurality of dies 22 on a substrate 20 .
- the test structure comprises a DUT 42 fabricated below the surface of the wafer and a plurality probe pads.
- Four signal probe pads comprising a pair of input/output probe pads 602 and 604 and a pair of output/input probe pads 606 and 608 , are arranged in a linear array in a first saw street 24 A.
- the four probe pads are co-locatable with respective contact areas of four probe tips 622 , 624 , 626 , 628 on a probe 620 .
- the contact areas of the four probe tips are arranged in a substantially straight line.
- the bias probe pad 610 is fabricated in the second saw street 24 B such that it is co-locatable with a bias probe tip 630 of the probe 620 .
- the probe pads of the pair of input/output signal probe pads 602 , 604 and the pair of output/input probe pads 606 , 608 are arranged substantially symmetrical with regard to the bias probe pad.
- a test structure comprising a balanced or differential device and having a plurality of probe pads arranged in a linear array enables fabrication of the test structure in a saw street between dies increasing the area of the substrate available for fabricating marketable integrated circuits reducing the cost of the marketable ICs and the cost of on wafer characterization of the ICs.
Abstract
A test structure for characterizing integrated circuits on a wafer includes a differential cell outputting a differential mode signal in response to a differential mode input signal. The probe pads of the test structure are arrayed linearly enabling placement of the test structure in a saw street between dies.
Description
- This application is a continuation of U.S. patent application Ser. No. 11/716,428, filed Mar. 9, 2007, which application claims the benefit of U.S. Provisional App. No. 60/813,099, filed Jun. 12, 2006.
- The present invention relates to integrated circuits and, more particularly to, test structures and methods for on-wafer inspection of integrated circuits and other microelectronic devices.
- Integrated circuits (ICs) comprise an arrangement of basic passive and active circuit elements, such as transistors, resistors and capacitors that are fabricated on a substrate or wafer. ICs are fabricated by a process of successively depositing layers of semi-conductive, conductive or insulating materials on the wafer and selectively etching portions of the deposited material. Deposition of a semi-conductor, conductor or insulator is followed by deposition of a layer of photosensitive material. The photosensitive material is exposed to light, through a precisely aligned mask, causing portions of the material to be chemically altered. Portions of the exposed photosensitive material are removed producing a photoresist layer with a pattern corresponding to the mask. A chemical etchant, applied to the surface, selectively removes the underlying semi-conductive, conductive or insulating layer except in those areas which are protected by the remaining photoresist. The remaining portions of the semi-conductor, conductor or insulator comprise a layer of one or more of the stratified, passive or active circuit elements. The photoresist layer is removed from the exposed surface of the wafer and the process is repeated until all of the strata of the circuit's elements have been laid down.
- Referring to
FIG. 1 , typically, a plurality ofdies 22, each comprising one or more integrated circuits, are formed on the surface of a wafer orsubstrate 20. Following fabrication, the individual dies are separated or singulated, typically by sawing the wafer along scribe or saw streets (indicated by a bracket) 24 between the dies. Each die containing a marketable integrated circuit is encased in a package and electrical connections are provided between the exterior of the package and the integrated circuit on the enclosed die. The separation and packaging of a die comprises a significant portion of the cost of manufacturing an integrated circuit device. To monitor and control the fabrication process and avoid the cost of packaging defective dies, manufacturers commonly add electrical circuits ortest structures 26 to the wafer that enable on-wafer inspection before the dies are singulated. - A wafer typically includes a plurality of
test structures 26 that are distributed about the surface of the wafer enabling a portion of the wafer containing a defect to be isolated and identified by the testing. Referring toFIG. 2 , atest structure 40 typically comprises a device under test (DUT) 42, a plurality of bond orprobe pads 44 and a plurality ofvias 46 connecting the probe pads on the surface of thesubstrate 20 to the circuit elements of the DUT which are typically fabricated beneath the surface. A DUT typically comprises a simple circuit that includes a copy of one or more of the basic elements of the marketable integrated circuit, such as a single line of conducting material, a chain of vias or a single transistor. The circuit elements of the DUT are typically produced with the same process and in the same layers of the wafer as corresponding elements of the marketable ICs. The marketable ICs are typically characterized “on-wafer” by applying a test instrument generated signal to the test structure and measuring the response of the test structure to the signal. Since the circuit elements of the DUT are fabricated with the same process as the corresponding elements of the integrated circuit, the electrical properties of the DUT are expected to be representative of the electrical properties of the corresponding components of the marketable ICs. - Many integrated circuits utilize single ended or ground referenced signaling that is referenced a ground plane, typically, at the lower surface of the substrate on which the active and passive devices of the circuit are fabricated. As a result of the physical make up of the devices of an integrated circuit, parasitic interconnections exist between many of the parts of the individual devices and between parts of the devices and the wafer on which the devices are fabricated. These interconnections are commonly capacitive and/or inductive in nature and have frequency dependent impedances. For example, the terminals of transistors fabricated on semi-conductive substrates or wafers are typically capacitively interconnected, through the substrate, to the ground plane. The impedance of this parasitic capacitive interconnection is frequency dependent and at higher frequencies the ground potential and the true nature of ground referenced signals becomes uncertain.
- Balanced or differential devices utilizing differential signals are more tolerant to poor radio frequency (RF) grounding than single ended devices making them attractive for high performance ICs. A
differential gain cell 50 is a balanced device comprising two nominallyidentical circuit halves transistors 52 of the differential gain cell are biased with a dc voltage, for example from acurrent source 54, and stimulated with a differential mode signal, comprising even (Si +1) and odd (Si −1) mode components of equal amplitude and opposite phase, a virtual ground is established at thesymmetrical axis 56 of the two circuit halves. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the stimulating signal. The quality of the virtual ground of a balanced device is independent of the physical ground path and, therefore, balanced or differential circuits can tolerate poor RF grounding better than circuits operated with single ended signals. In addition, the two waveforms of the differential output signal (So +1 and So −1) are mutual references providing faster and more certain transitioning from one binary value to the other for digital devices and enabling operation with a reduced voltage swing for the signal. Moreover, balanced or differential circuits have good immunity to noise, including noise at even-harmonic frequencies, because noise from external sources, such as adjacent conductors, tends to couple, electrically and electromagnetically, in the common mode and cancel in the differential mode and signals that are of opposite phase at the fundamental frequency are in phase at the even harmonics. Improved tolerance to poor RF grounding, increased resistance to noise and reduced power consumption make differential devices attractive for ICs that operate at higher frequencies. A differential gain cell is a common elemental device of differential or balanced circuits and a test structure comprising a differential gain cell enables on wafer testing and characterization of differential devices included in marketable ICs fabricated on the wafer. - As illustrated in
FIG. 1 , test structures are often fabricated on areas of the wafer that could otherwise be occupied by one or more dies containing the marketable integrated circuits. However, manufacturers face continuous pressure to reduce the cost of IC devices by increasing the number of dies fabricated on a wafer. Since the test structures serve no purpose after the dies are singulated, manufacturers have sought to locate the test structures in the saw streets between dies and, at the same time, to reduce the width of the saw streets to maximize utilization of the substrate's surface area. - While a DUT is usually small, the size of the test structure is typically determined by the area occupied by the probe pads. Test structures incorporating balanced devices typically require large areas of the wafer's surface because five
probe pads probes probe tips - What is desired, therefore, is a test structure including a DUT useful for testing integrated circuits comprising differential or balanced devices which can be fabricated in the saw streets between dies on a wafer or substrate.
-
FIG. 1 is a top view of an exemplary wafer on which integrated circuits are fabricated. -
FIG. 2 is a perspective view of a portion of a substrate comprising a test structure including a differential gain cell and a fragmentary representation of two probes arranged to probe the test structure. -
FIG. 3 is a schematic illustration of a probe measurement system for testing a differential test structure. -
FIG. 4 is a perspective view of a portion of a substrate comprising a differential test structure including a linear array of probe pads. -
FIG. 5 is a schematic illustration of a second embodiment of a differential test structure including a linear array of probe pads . -
FIG. 6 is a schematic illustration of a third embodiment of a differential test structure including a linear array of probe pads . -
FIG. 7 is a schematic illustration of a fourth embodiment of a differential test structure including a linear array of probe pads. -
FIG. 8 is a schematic illustration of a Gilbert cell. -
FIG. 9 is a top view of a portion of wafer including a pair of differential test structures fabricated at an intersection of two saw streets. -
FIG. 10 is a top view of a portion of wafer including another pair of differential test structures fabricated at an intersection of two saw streets. -
FIG. 11 is a top view of a portion of wafer including an additional embodiment of a differential test structure fabricated at an intersection of two saw streets. - The expected operation of integrated circuits (ICs) is commonly predicted by on-wafer characterization. The characterization is commonly performed by stimulating a test structure with a signal generated by a test instrument and measuring the signal produced in response to the stimulation. The test structure typically comprises a device-under-test (DUT) conductively connected to a plurality of probe or bond pads located on the surface of the wafer on which the marketable ICs are fabricated. The DUT typically comprises a relatively simple circuit that includes one or more active or passive circuit elements that correspond to circuit elements included in the marketable ICs. Much of the circuitry of the DUT is typically fabricated below the surface of the wafer with the same process of successive deposition and etching of layers of conductive, semi-conductive and insulating materials that is used to fabricate the corresponding components of the marketable ICs. Since the components of the DUT are fabricated with the same process that is used to produce the components of the marketable ICs, it is anticipated that the operation of the DUT, when stimulated by the test signal, will be representative of the operation of the corresponding components of the ICs if stimulated by a similar signal.
- Interconnections between the test instrumentation and the DUT commonly exhibit frequency dependent electrical characteristics or parasitics which must be accounted for, particularly, at high frequencies, if the operation of the DUT is to be determined accurately. For example, the probes that commonly enable temporary connection of the instrumentation to the test structure typically comprise a plurality of interconnected transmission lines of differing types and each transition can produce a frequency dependent effect on the signal. Within the test structure, vias connecting the probe pads, deposited at the surface of the wafer, to the components of the DUT, located below the wafer's surface, have a finite inductance. As a result, the admittances of the vias are frequency dependent and must be accounted for to enable accurate measurement of the DUT's operation. A process known as “de-embedding” in which the test instrumentation is used to stimulate and measure the response of a plurality of known sample test structures is widely used to mathematically account for these effects so that the signals at the input and output terminals of the DUT can be accurately assessed.
- However, some parasitics also arise internally in the DUT making de-embedding difficult or impossible and the frequency dependent effects of these parasitics may make assessment of the signal at the DUT's terminals unreliable. Integrated circuits are commonly unbalanced devices that utilize single ended (ground referenced) signals. Typically, the lower surface of the wafer serves as the ground plane for the circuit devices, including devices in a test structure, that are fabricated on the upper surface of the substrate. However, the terminals of circuit elements fabricated on semi-conductive substrates are capacitively interconnected through the substrate to the substrate's lower surface. The impedance of the capacitive interconnections to the circuit's ground plane varies with frequency producing uncertainty concerning the ground potential and, therefore, the true nature of the single ended signals at the terminals of the DUT particularly at higher frequencies, such as radio frequencies (RF).
- A balanced device, responsive to differential signals, is known to be more tolerant than an unbalanced device to ground potential variation such as that encountered during operation at higher frequencies. Referring in detail to the drawings where similar parts are identified by like reference numerals, and, more particularly to
FIG. 2 , adifferential gain cell 50, a balanced device, comprises two nominally identical circuit halves 50A, 50B. When biased with a DC voltage, from a source such as acurrent source 54 or another potential referenced to ground, and stimulated with a differential mode signal, comprising even (Si +1) and odd (Si −1) mode components of equal amplitude and opposite phase, a virtual ground is established at thesymmetrical axis 56 of the two circuit halves. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the stimulating signal. The quality of the virtual ground of a balanced device is independent of the physical ground path and, therefore, balanced or differential circuits can tolerate poor radio frequency (RF) grounding better than circuits operated with single ended signals. In addition, noise from external sources, such as adjacent conductors, tends to couple, electrically and electromagnetically, in the common mode and cancel in the differential mode. As a result, balanced or differential circuits have good immunity to noise including noise at even-harmonic frequencies since signals that are of opposite phase at the fundamental frequency are in phase at the even harmonics. - While balanced devices provide enhanced signal integrity at higher frequencies and reduced interference from external noise, the use of balanced devices in DUTs of test structures is limited. Two
probes probe pads - Referring to
FIG. 3 , thetest structure 100 comprises aDUT 102 that includes adifferential gain cell 104 that is responsive to a differential input signal. The differential input signal comprises an even mode component (Si +1) and an odd mode component (Si −1) that has substantially the same amplitude as the even mode component but which is opposite in phase of the even mode component. Thedifferential gain cell 104 comprises two substantially identical field effect (JFET)transistors FIGS. 5 and 6 other types of transistors, such asMOSFET transistors transistors FIG. 8 ,differential gain cells 402 comprising pairs of transistors are commonly used in more complex circuits such as aGilbert cell 400. - The source terminals of the
transistors bias terminal 110 of the differential gain cell. The bias terminal is interconnected to a centrally locatedbias probe pad 120. The bias probe pad is interconnected, typically through acontact tip 130 of a probe, to a source of DC voltage, for example aground 140 or a current mirror, which provides the DC bias for the transistors of the differential gain cell. - The gates of the transistors comprise a first pair of
signal terminals signal probe pads respective contact tips test instrument 146, typically a network analyzer. The drains of the transistors of the differential gain cell comprise a second pair ofsignal terminals respective probe pads contact tips source 142 of a differential input signal to the DUT comprising an even mode component, Si +1, and an odd mode component, Si −1; asink 144 for the differential output signal of the DUT comprising an even mode component, So +1, and an odd mode component, So −1. A reversingswitch 148 enables reversing the connections between the test instrument's differential signal source and sink and the respective pairs of signal probe pads. With the reversing switch in the illustrated position, the components of the differential input signals (Si +1 and Si −1) are applied to probepads terminals terminals probe pads pads terminals terminals probe pads - While the
test structure 40 can be fabricated in an area that could otherwise be occupied by one or more marketable ICs, the area required for the probe pads is too large to make locating the test structure in a saw street practical. The inventors concluded that a differential test structure could be fabricated in a saw street between dies on a wafer by arranging the four signal probe pads of the structure in a linear array such that the probe pads could be contacted by respective probe tips of a movable probe. The probe tips have contact areas with centroids arranged in a substantially straight line. Further, signal transmission for the test structure would benefit from a substantially symmetrical arrangement of signal probe pads in relation to one or more bias probe pads which may also be included in the linear array of probe pads. Referring toFIG. 4 , thetest structure 150 can be fabricated in an area of the wafer that would otherwise be occupied by a die containing a marketable IC. However, advantageously, thetest structure 150 may be fabricated in a saw street 24 (indicated by a bracket) bounded by dies 182, 184 fabricated on asubstrate 20. Typically, theDUT 152 is relatively small and comprises circuit elements that are fabricated beneath the final surface of the wafer. Fiveprobe pads output probe pads 166, 168 and a pair of output/input probe pads 162, 164; that are arranged substantially symmetrical with one or more bias probe pads. The linear array of probe pads enables placement of the test structure in a saw street only slightly wider than the probe pads. The probe pads are accessible with a singlemovable probe 188 having a plurality ofcontact tips 190 arranged to be co-locatable with respective probe pads and having contact points or areas with centroids arranged in a substantially straight line. The probe pads are conductively connected to respective terminals of the DUT byvias 186 that extend from the surface of the wafer to the subsurface strata in which the circuit elements of the DUT are fabricated. - In the
test structure 100, the modes of the input and output signals at adjacent probe pads are the same. For example, sinking the even mode input signal (Si +1) at theprobe pad 126 causes the even mode output signal (So +1) to be transmitted fromprobe pad 122. Referring toFIG. 5 , in a second embodiment of thetest structure 250 the mode of the input and output signals at adjacent probe pads are inverted. For example, when the odd mode input signal (Si −1) is applied to theprobe pad 264 and the even mode input signal (Si +1) is applied to probepad 262, the even mode output signal (So −1) is transmitted fromprobe pad 268 adjacent to probepad 264 and the odd mode output signal (So −1) is transmitted from theprobe pad 266 adjacent to probepad 262. The gates of thetransistors DUT 251 are connected, respectively, to thesecond signal terminal 272 and thethird signal terminal 274. The drain of thetransistor 252B is connected to thefourth signal terminal 278 which is interconnected to probepad 268 and the drain oftransistor 252A is connected to thefirst signal terminal 276 andprobe pad 266. As a result, the modes of the input and output signals at adjacent probe pads are inverted. - An additional alternative embodiment of the differential test structure 300 with linearly arrayed probe pads is illustrated in
FIG. 6 . The additional embodiment comprises aDUT 302 including a differential gain cell comprising matchedBJT transistors differential signal terminals respective probe pads probe pads third signal terminals bias terminal 320 of the DUT. Bias is provided to the differential gain cell at a centrally locatedprobe pad 310 that is interconnected to the bias terminal. The bias terminal is also conductively interconnected to a pair ofprobe pads respective probe tips 338, to the source of DC bias 336 for the DUT. The additional DC biased probe pads at the respective ends of the linear array of probe pads improve the symmetry of the electromagnetic fields and reduce the crosstalk between the signal probe pads and the centrally located bias probe pad. - Referring to
FIG. 7 , an additional embodiment of thedifferential test structure 350 comprises a linear array of sixprobe pads signal probe pads signal terminals transistors DUT 351 andsignal probe pads signal terminals bias terminal 320 of the cell which is in turn connected tobias probe pads - The test structures can be further concentrated by locating the linear arrays of probe pads at the intersections of
saw streets 24 between dies 22 on awafer 20. Referring toFIG. 9 , thelinear arrays 500 of probe pads comprise up to seven probe pads with a centralbias probe pad 502 located between two pairs ofsignal probe pads saw streets 24 can be common to aDUT 508 in the north-south saw street and aDUT 510 located in the east-west saw street because theprobe tips 514 of theprobe 512 are arranged supply signals to only one set of signal probe pads at a time. The probe pads of the test structures can include additionalbias probe pads 516 at each end of each linear array of probe pads. Referring toFIG. 10 , linear arrays of sixprobe pads 550 comprising two pairs ofsignal probe pads bias probe pads south streets 24. Thebias probe pad 556 in the intersection can be connected to each of the fourDUTs probe tips 562 ofprobe 560 will supply signals to the signal probe pads of only one array of probe pads at a time. -
FIG. 11 illustrates another embodiment of a compactdifferential test structure 600 fabricated at the intersection ofsaw streets substrate 20. The test structure comprises aDUT 42 fabricated below the surface of the wafer and a plurality probe pads. Four signal probe pads, comprising a pair of input/output probe pads input probe pads first saw street 24A. The four probe pads are co-locatable with respective contact areas of four probe tips 622, 624, 626, 628 on a probe 620. The contact areas of the four probe tips are arranged in a substantially straight line. The bias probe pad 610 is fabricated in thesecond saw street 24B such that it is co-locatable with a bias probe tip 630 of the probe 620. The probe pads of the pair of input/outputsignal probe pads input probe pads - A test structure comprising a balanced or differential device and having a plurality of probe pads arranged in a linear array enables fabrication of the test structure in a saw street between dies increasing the area of the substrate available for fabricating marketable integrated circuits reducing the cost of the marketable ICs and the cost of on wafer characterization of the ICs.
- The detailed description, above, sets forth numerous specific details to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuitry have not been described in detail to avoid obscuring the present invention.
- All the references cited herein are incorporated by reference.
- The terms and expressions that have been employed in the foregoing specification are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims that follow.
Claims (18)
1. A test structure for characterizing a circuit fabricated on die on a substrate, said test structure comprising:
(a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to a differential input signal applied to said first signal terminal and said second signal terminal application of a bias to a bias terminal of said differential cell;
(b) a first probe pad interconnected said third signal terminal;
(c) a second probe pad adjacent to said first probe pad and interconnected with said first signal terminal;
(d) a third probe pad adjacent to said second probe pad and interconnected with said bias terminal;
(e) a fourth probe pad adjacent to said third probe pad and interconnected to said second signal terminal; and
(f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said fourth signal terminal.
2. The test structure of claim 1 wherein said first, said second, said third, said fourth and said fifth probe pads are located within a saw street bounded by a first die and a second die.
3. The test structure of claim 1 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said first probe pad is inverted relative to said phase of said signal at said second probe pad.
4. The test structure of claim 1 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first input signal, and said phase of said signal at said first probe pad is the same as said phase of said signal at said second probe pad.
5. The test structure of claim 1 wherein said first, said second, said third, said fourth and said fifth probe pads are arrayed substantially linearly on said wafer.
6. The test structure of claim 5 wherein said probe pads of said linear array are located within a saw street bounded a first die and a second die fabricated on said substrate.
7. A test structure for characterizing a circuit fabricated on die on a substrate, said test structure comprising:
(a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to a differential input signal applied to said first signal terminal and said second signal terminal application of a bias to a bias terminal of said differential cell;
(b) a first probe pad interconnected to said bias terminal
(c) a second probe pad adjacent to said first probe pad and interconnected with said third signal terminal;
(d) a third probe pad adjacent to said second probe pad and interconnected with said first signal terminal;
(e) a fourth probe pad adjacent to said third probe pad and interconnected with said bias terminal;
(f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said second signal terminal; and
(g) a sixth probe pad adjacent to said fifth probe pad and interconnected to said fourth signal terminal.
(h) a seventh probe pad adjacent said sixth probe pad and interconnected to said bias terminal.
8. The test structure of claim 7 wherein said first, said second, said third, said fourth, said fifth, said sixth and said seventh probe pads are located within a saw street bounded by a first die and a second die.
9. The test structure of claim 7 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said second probe pad is inverted relative to said phase of said signal at said third probe pad.
10. The test structure of claim 7 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said second probe pad is the same as said phase of said signal at said third probe pad.
11. The test structure of claim 7 wherein said first, said second, said third, said fourth and said fifth, said sixth and said seventh probe pads are arrayed substantially linearly on said wafer.
12. The test structure of claim 11 wherein said probe pads of said linear array are located within a saw street bounded a first die and a second die fabricated on said substrate.
13. A test structure for characterizing a circuit fabricated on die on a substrate, said test structure comprising:
(a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to a differential input signal applied to said first signal terminal and said second signal terminal application of a bias to a bias terminal of said differential cell;
(b) a first probe pad interconnected to said bias terminal
(c) a second probe pad adjacent to said first probe pad and interconnected with said third signal terminal;
(d) a third probe pad adjacent to said second probe pad and interconnected with said first signal terminal;
(e) a fourth probe pad adjacent to said third probe pad and interconnected to said second signal terminal; and
(f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said fourth signal terminal; and
(g) a sixth probe pad proximate said fifth probe pad and interconnected to said bias terminal.
14. The test structure of claim 13 wherein said first, said second, said third, said fourth, said fifth and said sixth probe pads are located within a saw street bounded by a first die and a second die.
15. The test structure of claim 13 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said second probe pad is inverted relative to said phase of said signal at said third probe pad.
16. The test structure of claim 13 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said second probe pad is the same as said phase of said signal at said third probe pad.
17. The test structure of claim 13 wherein said first, said second, said third, said fourth and said fifth and said sixth probe pads are arrayed substantially linearly on said wafer.
18. The test structure of claim 13 wherein said probe pads of said linear array are located within a saw street bounded a first die and a second die fabricated on said substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/283,984 US20090021273A1 (en) | 2006-06-12 | 2008-09-16 | On-wafer test structures |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US81309906P | 2006-06-12 | 2006-06-12 | |
US11/716,428 US7443186B2 (en) | 2006-06-12 | 2007-03-09 | On-wafer test structures for differential signals |
US12/283,984 US20090021273A1 (en) | 2006-06-12 | 2008-09-16 | On-wafer test structures |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/716,428 Continuation US7443186B2 (en) | 2006-06-12 | 2007-03-09 | On-wafer test structures for differential signals |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090021273A1 true US20090021273A1 (en) | 2009-01-22 |
Family
ID=38821250
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/716,428 Expired - Fee Related US7443186B2 (en) | 2006-06-12 | 2007-03-09 | On-wafer test structures for differential signals |
US12/283,984 Abandoned US20090021273A1 (en) | 2006-06-12 | 2008-09-16 | On-wafer test structures |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/716,428 Expired - Fee Related US7443186B2 (en) | 2006-06-12 | 2007-03-09 | On-wafer test structures for differential signals |
Country Status (2)
Country | Link |
---|---|
US (2) | US7443186B2 (en) |
WO (1) | WO2007145729A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180131054A1 (en) * | 2014-06-11 | 2018-05-10 | Enovate Medical Llc | Shielding receptacle for battery cells |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2093580B1 (en) * | 2008-02-25 | 2012-08-15 | Dialog Semiconductor GmbH | Supply current based testing of CMOS output stages |
US7772867B2 (en) * | 2008-02-26 | 2010-08-10 | Texas Instruments Incorporated | Structures for testing and locating defects in integrated circuits |
KR101202020B1 (en) * | 2008-11-14 | 2012-11-16 | 한국전자통신연구원 | System and method for wafer level tuning of integrated circuit chips |
DE102010046214A1 (en) | 2010-09-21 | 2012-03-22 | Infineon Technologies Ag | Wafer test structure has interface that is connected to integrated test circuit, for receiving and outputting test data |
US8622752B2 (en) * | 2011-04-13 | 2014-01-07 | Teradyne, Inc. | Probe-card interposer constructed using hexagonal modules |
KR20130126337A (en) * | 2012-05-11 | 2013-11-20 | 에스케이하이닉스 주식회사 | Test device of semiconductor device, test system of semiconductor device and method for testing semiconductor device |
US9435855B2 (en) | 2013-11-19 | 2016-09-06 | Teradyne, Inc. | Interconnect for transmitting signals between a device and a tester |
US9594114B2 (en) | 2014-06-26 | 2017-03-14 | Teradyne, Inc. | Structure for transmitting signals in an application space between a device under test and test electronics |
US20170338184A1 (en) * | 2016-05-19 | 2017-11-23 | Texas Instruments Incorporated | Method of dicing integrated circuit wafers |
US9977052B2 (en) | 2016-10-04 | 2018-05-22 | Teradyne, Inc. | Test fixture |
US10677815B2 (en) | 2018-06-08 | 2020-06-09 | Teradyne, Inc. | Test system having distributed resources |
US11363746B2 (en) | 2019-09-06 | 2022-06-14 | Teradyne, Inc. | EMI shielding for a signal trace |
US11862901B2 (en) | 2020-12-15 | 2024-01-02 | Teradyne, Inc. | Interposer |
Citations (98)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US491783A (en) * | 1893-02-14 | Bolster-plate | ||
US2143625A (en) * | 1931-08-25 | 1939-01-10 | Archie M Bovier | Manifolding record |
US2921276A (en) * | 1955-08-30 | 1960-01-12 | Cutler Hammer Inc | Microwave circuits |
US3230299A (en) * | 1962-07-18 | 1966-01-18 | Gen Cable Corp | Electrical cable with chemically bonded rubber layers |
US3429040A (en) * | 1965-06-18 | 1969-02-25 | Ibm | Method of joining a component to a substrate |
US3561280A (en) * | 1968-08-22 | 1971-02-09 | American Mach & Foundry | Three axis strain gage control device |
US3634807A (en) * | 1969-03-28 | 1972-01-11 | Siemens Ag | Detachable electrical contact arrangement |
US3710251A (en) * | 1971-04-07 | 1973-01-09 | Collins Radio Co | Microelectric heat exchanger pedestal |
US3714572A (en) * | 1970-08-21 | 1973-01-30 | Rca Corp | Alignment and test fixture apparatus |
US3862790A (en) * | 1971-07-22 | 1975-01-28 | Plessey Handel Investment Ag | Electrical interconnectors and connector assemblies |
US3866093A (en) * | 1972-09-18 | 1975-02-11 | Norbert L Kusters | Low leakage electrical power input circuit for electromedical and other similar apparatus |
US3867698A (en) * | 1973-03-01 | 1975-02-18 | Western Electric Co | Test probe for integrated circuit chips |
US3930809A (en) * | 1973-08-21 | 1976-01-06 | Wentworth Laboratories, Inc. | Assembly fixture for fixed point probe card |
US3936743A (en) * | 1974-03-05 | 1976-02-03 | Electroglas, Inc. | High speed precision chuck assembly |
US4001685A (en) * | 1974-03-04 | 1977-01-04 | Electroglas, Inc. | Micro-circuit test probe |
US4008900A (en) * | 1976-03-15 | 1977-02-22 | John Freedom | Indexing chuck |
US4009456A (en) * | 1970-10-07 | 1977-02-22 | General Microwave Corporation | Variable microwave attenuator |
US4072576A (en) * | 1975-10-06 | 1978-02-07 | Ab Kabi | Method for studying enzymatic and other biochemical reactions |
US4074201A (en) * | 1976-07-26 | 1978-02-14 | Gte Sylvania Incorporated | Signal analyzer with noise estimation and signal to noise readout |
US4135131A (en) * | 1977-10-14 | 1979-01-16 | The United States Of America As Represented By The Secretary Of The Army | Microwave time delay spectroscopic methods and apparatus for remote interrogation of biological targets |
US4184133A (en) * | 1977-11-28 | 1980-01-15 | Rockwell International Corporation | Assembly of microwave integrated circuits having a structurally continuous ground plane |
US4184729A (en) * | 1977-10-13 | 1980-01-22 | Bunker Ramo Corporation | Flexible connector cable |
US4251772A (en) * | 1978-12-26 | 1981-02-17 | Pacific Western Systems Inc. | Probe head for an automatic semiconductive wafer prober |
US4312117A (en) * | 1977-09-01 | 1982-01-26 | Raytheon Company | Integrated test and assembly device |
US4425395A (en) * | 1981-04-30 | 1984-01-10 | Fujikura Rubber Works, Ltd. | Base fabrics for polyurethane-coated fabrics, polyurethane-coated fabrics and processes for their production |
US4491783A (en) * | 1981-04-25 | 1985-01-01 | Tokyo Shibaura Denki Kabushiki Kaisha | Apparatus for measuring noise factor and available gain |
US4502028A (en) * | 1982-06-15 | 1985-02-26 | Raytheon Company | Programmable two-port microwave network |
US4563640A (en) * | 1981-06-03 | 1986-01-07 | Yoshiei Hasegawa | Fixed probe board |
US4567436A (en) * | 1982-01-21 | 1986-01-28 | Linda Koch | Magnetic thickness gauge with adjustable probe |
US4567321A (en) * | 1984-02-20 | 1986-01-28 | Junkosha Co., Ltd. | Flexible flat cable |
US4568890A (en) * | 1982-12-23 | 1986-02-04 | U.S. Philips Corporation | Microwave oscillator injection locked at its fundamental frequency for producing a harmonic frequency output |
US4636722A (en) * | 1984-05-21 | 1987-01-13 | Probe-Rite, Inc. | High density probe-head with isolated and shielded transmission lines |
US4636772A (en) * | 1985-01-17 | 1987-01-13 | Riken Denshi Co. Ltd. | Multiple function type D/A converter |
US4642417A (en) * | 1984-07-30 | 1987-02-10 | Kraftwerk Union Aktiengesellschaft | Concentric three-conductor cable |
US4641659A (en) * | 1979-06-01 | 1987-02-10 | Sepponen Raimo E | Medical diagnostic microwave scanning apparatus |
US4646005A (en) * | 1984-03-16 | 1987-02-24 | Motorola, Inc. | Signal probe |
US4722846A (en) * | 1984-04-18 | 1988-02-02 | Kikkoman Corporation | Novel variant and process for producing light colored soy sauce using such variant |
US4725793A (en) * | 1985-09-30 | 1988-02-16 | Alps Electric Co., Ltd. | Waveguide-microstrip line converter |
US4795962A (en) * | 1986-09-04 | 1989-01-03 | Hewlett-Packard Company | Floating driver circuit and a device for measuring impedances of electrical components |
US4891584A (en) * | 1988-03-21 | 1990-01-02 | Semitest, Inc. | Apparatus for making surface photovoltage measurements of a semiconductor |
US4894612A (en) * | 1987-08-13 | 1990-01-16 | Hypres, Incorporated | Soft probe for providing high speed on-wafer connections to a circuit |
US4983910A (en) * | 1988-05-20 | 1991-01-08 | Stanford University | Millimeter-wave active probe |
US4987100A (en) * | 1988-05-26 | 1991-01-22 | International Business Machines Corporation | Flexible carrier for an electronic device |
US4988062A (en) * | 1988-03-10 | 1991-01-29 | London Robert A | Apparatus, system and method for organizing and maintaining a plurality of medical catheters and the like |
US5082627A (en) * | 1987-05-01 | 1992-01-21 | Biotronic Systems Corporation | Three dimensional binding site array for interfering with an electrical field |
US5084671A (en) * | 1987-09-02 | 1992-01-28 | Tokyo Electron Limited | Electric probing-test machine having a cooling system |
US5177438A (en) * | 1991-08-02 | 1993-01-05 | Motorola, Inc. | Low resistance probe for semiconductor |
US5180977A (en) * | 1991-12-02 | 1993-01-19 | Hoya Corporation Usa | Membrane probe contact bump compliancy system |
US5280156A (en) * | 1990-12-25 | 1994-01-18 | Ngk Insulators, Ltd. | Wafer heating apparatus and with ceramic substrate and dielectric layer having electrostatic chucking means |
US5281364A (en) * | 1992-05-22 | 1994-01-25 | Finch Limited | Liquid metal electrical contact compositions |
US5383787A (en) * | 1993-04-27 | 1995-01-24 | Aptix Corporation | Integrated circuit package with direct access to internal signals |
US5481196A (en) * | 1994-11-08 | 1996-01-02 | Nebraska Electronics, Inc. | Process and apparatus for microwave diagnostics and therapy |
US5481936A (en) * | 1993-06-29 | 1996-01-09 | Yugen Kaisha Sozoan | Rotary drive positioning system for an indexing table |
US5487999A (en) * | 1991-06-04 | 1996-01-30 | Micron Technology, Inc. | Method for fabricating a penetration limited contact having a rough textured surface |
US5594358A (en) * | 1993-09-02 | 1997-01-14 | Matsushita Electric Industrial Co., Ltd. | Radio frequency probe and probe card including a signal needle and grounding needle coupled to a microstrip transmission line |
US5704355A (en) * | 1994-07-01 | 1998-01-06 | Bridges; Jack E. | Non-invasive system for breast cancer detection |
US6013586A (en) * | 1997-10-09 | 2000-01-11 | Dimension Polyant Sailcloth, Inc. | Tent material product and method of making tent material product |
US6168974B1 (en) * | 1993-11-16 | 2001-01-02 | Formfactor, Inc. | Process of mounting spring contacts to semiconductor devices |
US6169410B1 (en) * | 1998-11-09 | 2001-01-02 | Anritsu Company | Wafer probe with built in RF frequency conversion module |
US6172337B1 (en) * | 1995-07-10 | 2001-01-09 | Mattson Technology, Inc. | System and method for thermal processing of a semiconductor substrate |
US6175228B1 (en) * | 1998-10-30 | 2001-01-16 | Agilent Technologies | Electronic probe for measuring high impedance tri-state logic circuits |
US6176091B1 (en) * | 1998-10-01 | 2001-01-23 | Nkk Corporation | Method and apparatus for preventing snow from melting and for packing snow in artificial ski facility |
US6181149B1 (en) * | 1996-09-26 | 2001-01-30 | Delaware Capital Formation, Inc. | Grid array package test contactor |
US6181416B1 (en) * | 1998-04-14 | 2001-01-30 | Optometrix, Inc. | Schlieren method for imaging semiconductor device properties |
US6181297B1 (en) * | 1994-08-25 | 2001-01-30 | Symmetricom, Inc. | Antenna |
US6181144B1 (en) * | 1998-02-25 | 2001-01-30 | Micron Technology, Inc. | Semiconductor probe card having resistance measuring circuitry and method fabrication |
US6334247B1 (en) * | 1992-10-19 | 2002-01-01 | International Business Machines Corporation | High density integrated circuit apparatus, test probe and methods of use thereof |
US6335625B1 (en) * | 1999-02-22 | 2002-01-01 | Paul Bryant | Programmable active microwave ultrafine resonance spectrometer (PAMURS) method and systems |
US6339338B1 (en) * | 2000-01-18 | 2002-01-15 | Formfactor, Inc. | Apparatus for reducing power supply noise in an integrated circuit |
US20020005728A1 (en) * | 1999-04-15 | 2002-01-17 | Gordon M. Babson | Micro probe and method of fabricating same |
US6340895B1 (en) * | 1999-07-14 | 2002-01-22 | Aehr Test Systems, Inc. | Wafer-level burn-in and test cartridge |
US6340568B2 (en) * | 1998-02-02 | 2002-01-22 | Signature Bioscience, Inc. | Method for detecting and classifying nucleic acid hybridization |
US20020009378A1 (en) * | 2000-07-21 | 2002-01-24 | Rikuro Obara | Blower |
US20020009377A1 (en) * | 2000-06-09 | 2002-01-24 | Shafer Ronny A. | Motor cover retention |
US20020008533A1 (en) * | 2000-07-05 | 2002-01-24 | Ando Electric Co., Ltd | Electro-optic probe and magneto-optic probe |
US20020011863A1 (en) * | 1998-06-09 | 2002-01-31 | Advantest Corporation | IC chip tester with heating element for preventing condensation |
US20020011859A1 (en) * | 1993-12-23 | 2002-01-31 | Kenneth R. Smith | Method for forming conductive bumps for the purpose of contrructing a fine pitch test device |
US20030010877A1 (en) * | 2001-07-12 | 2003-01-16 | Jean-Luc Landreville | Anti-vibration and anti-tilt structure |
US6509751B1 (en) * | 2000-03-17 | 2003-01-21 | Formfactor, Inc. | Planarizer for a semiconductor contactor |
US6512482B1 (en) * | 2001-03-20 | 2003-01-28 | Xilinx, Inc. | Method and apparatus using a semiconductor die integrated antenna structure |
US6672875B1 (en) * | 1998-12-02 | 2004-01-06 | Formfactor, Inc. | Spring interconnect structures |
US6678850B2 (en) * | 1999-03-01 | 2004-01-13 | Formfactor, Inc. | Distributed interface for parallel testing of multiple devices using a single tester channel |
US6677744B1 (en) * | 2000-04-13 | 2004-01-13 | Formfactor, Inc. | System for measuring signal path resistance for an integrated circuit tester interconnect structure |
US6678876B2 (en) * | 2001-08-24 | 2004-01-13 | Formfactor, Inc. | Process and apparatus for finding paths through a routing space |
US6680659B2 (en) * | 1999-02-25 | 2004-01-20 | Formfactor, Inc. | Integrated circuit interconnect system |
US20040015060A1 (en) * | 2002-06-21 | 2004-01-22 | James Samsoondar | Measurement of body compounds |
US6838885B2 (en) * | 2003-03-05 | 2005-01-04 | Murata Manufacturing Co., Ltd. | Method of correcting measurement error and electronic component characteristic measurement apparatus |
US6838893B2 (en) * | 1993-11-16 | 2005-01-04 | Formfactor, Inc. | Probe card assembly |
US6836962B2 (en) * | 1993-11-16 | 2005-01-04 | Formfactor, Inc. | Method and apparatus for shaping spring elements |
US6839964B2 (en) * | 1998-04-14 | 2005-01-11 | Formfactor, Inc. | Method for manufacturing a multi-layer printed circuit board |
US6845491B2 (en) * | 1999-02-25 | 2005-01-18 | Formfactor, Inc. | Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes |
US6987483B2 (en) * | 2003-02-21 | 2006-01-17 | Kyocera Wireless Corp. | Effectively balanced dipole microstrip antenna |
US7161363B2 (en) * | 2002-05-23 | 2007-01-09 | Cascade Microtech, Inc. | Probe for testing a device under test |
US7315175B2 (en) * | 2001-01-30 | 2008-01-01 | Teraview Limited | Probe apparatus and method for examining a sample |
US7319335B2 (en) * | 2004-02-12 | 2008-01-15 | Applied Materials, Inc. | Configurable prober for TFT LCD array testing |
US7319337B2 (en) * | 2005-02-25 | 2008-01-15 | Elpida Memory, Inc. | Method and apparatus for pad aligned multiprobe wafer testing |
US7323680B2 (en) * | 2005-04-12 | 2008-01-29 | Santec Corporation | Optical deflection probe and optical deflection probe device |
US7323899B2 (en) * | 2004-06-10 | 2008-01-29 | Texas Instruments Incorporated | System and method for resumed probing of a wafer |
Family Cites Families (97)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1337866A (en) | 1917-09-27 | 1920-04-20 | Griffiths Ethel Grace | System for protecting electric cables |
US2142625A (en) | 1932-07-06 | 1939-01-03 | Hollandsche Draad En Kabelfab | High tension cable |
US2376101A (en) | 1942-04-01 | 1945-05-15 | Ferris Instr Corp | Electrical energy transmission |
US2389668A (en) | 1943-03-04 | 1945-11-27 | Barnes Drill Co | Indexing mechanism for machine tables |
US2545258A (en) | 1945-03-22 | 1951-03-13 | Marcel L Cailloux | Device for telecontrol of spatial movement |
US2762234A (en) | 1952-09-08 | 1956-09-11 | Dodd Roy Frank | Search-track radar control |
US2901696A (en) | 1953-11-25 | 1959-08-25 | Ingeniors N Magnetic Ab Fa | Arrangement for automatic and continuous measuring of the noise factor of an electric device |
US3193712A (en) | 1962-03-21 | 1965-07-06 | Clarence A Harris | High voltage cable |
US3262593A (en) | 1963-07-10 | 1966-07-26 | Gen Mills Inc | Wall-mounted support structure |
GB1031068A (en) | 1963-09-23 | 1966-05-25 | George Vincent Grispo | Improvements in or relating to motion reduction mechanisms |
US3218584A (en) | 1964-01-02 | 1965-11-16 | Sanders Associates Inc | Strip line connection |
US3401126A (en) | 1965-06-18 | 1968-09-10 | Ibm | Method of rendering noble metal conductive composition non-wettable by solder |
US3445770A (en) | 1965-12-27 | 1969-05-20 | Philco Ford Corp | Microelectronic test probe with defect marker access |
US3484679A (en) | 1966-10-03 | 1969-12-16 | North American Rockwell | Electrical apparatus for changing the effective capacitance of a cable |
US3573617A (en) | 1967-10-27 | 1971-04-06 | Aai Corp | Method and apparatus for testing packaged integrated circuits |
US3609539A (en) | 1968-09-28 | 1971-09-28 | Ibm | Self-aligning kelvin probe |
US3541222A (en) | 1969-01-13 | 1970-11-17 | Bunker Ramo | Connector screen for interconnecting adjacent surfaces of laminar circuits and method of making |
JPS497756B1 (en) | 1969-01-24 | 1974-02-22 | ||
US3648169A (en) | 1969-05-26 | 1972-03-07 | Teledyne Inc | Probe and head assembly |
US3596228A (en) | 1969-05-29 | 1971-07-27 | Ibm | Fluid actuated contactor |
US3611199A (en) | 1969-09-30 | 1971-10-05 | Emerson Electric Co | Digital electromagnetic wave phase shifter comprising switchable reflectively terminated power-dividing means |
US3686624A (en) | 1969-12-15 | 1972-08-22 | Rca Corp | Coax line to strip line end launcher |
US3654585A (en) | 1970-03-11 | 1972-04-04 | Brooks Research And Mfg Inc | Coordinate conversion for the testing of printed circuit boards |
US3622915A (en) | 1970-03-16 | 1971-11-23 | Meca Electronics Inc | Electrical coupler |
US3740900A (en) | 1970-07-01 | 1973-06-26 | Signetics Corp | Vacuum chuck assembly for semiconductor manufacture |
US3700998A (en) | 1970-08-20 | 1972-10-24 | Computer Test Corp | Sample and hold circuit with switching isolation |
US3680037A (en) | 1970-11-05 | 1972-07-25 | Tech Wire Prod Inc | Electrical interconnector |
US3662318A (en) | 1970-12-23 | 1972-05-09 | Comp Generale Electricite | Transition device between coaxial and microstrip lines |
US3705379A (en) | 1971-05-14 | 1972-12-05 | Amp Inc | Connector for interconnection of symmetrical and asymmetrical transmission lines |
US3766470A (en) | 1971-05-24 | 1973-10-16 | Unit Process Assemblies | Apparatus for testing the integrity of a thru-hole plating in circuit board workpieces or the like by measuring the effective thickness thereof |
US3725829A (en) | 1971-07-14 | 1973-04-03 | Itek Corp | Electrical connector |
US3810016A (en) | 1971-12-17 | 1974-05-07 | Western Electric Co | Test probe for semiconductor devices |
US3829076A (en) | 1972-06-08 | 1974-08-13 | H Sofy | Dial index machine |
US3858212A (en) | 1972-08-29 | 1974-12-31 | L Tompkins | Multi-purpose information gathering and distribution system |
US3952156A (en) | 1972-09-07 | 1976-04-20 | Xerox Corporation | Signal processing system |
US3806801A (en) | 1972-12-26 | 1974-04-23 | Ibm | Probe contactor having buckling beam probes |
US3839672A (en) | 1973-02-05 | 1974-10-01 | Belden Corp | Method and apparatus for measuring the effectiveness of the shield in a coaxial cable |
US3833852A (en) | 1973-08-16 | 1974-09-03 | Owens Illinois Inc | Inspection head mounting apparatus |
US3849728A (en) | 1973-08-21 | 1974-11-19 | Wentworth Labor Inc | Fixed point probe card and an assembly and repair fixture therefor |
US3971610A (en) | 1974-05-10 | 1976-07-27 | Technical Wire Products, Inc. | Conductive elastomeric contacts and connectors |
US3976959A (en) | 1974-07-22 | 1976-08-24 | Gaspari Russell A | Planar balun |
US3970934A (en) | 1974-08-12 | 1976-07-20 | Akin Aksu | Printed circuit board testing means |
US4038599A (en) | 1974-12-30 | 1977-07-26 | International Business Machines Corporation | High density wafer contacting and test system |
US4123706A (en) | 1975-03-03 | 1978-10-31 | Electroglas, Inc. | Probe construction |
US4038894A (en) | 1975-07-18 | 1977-08-02 | Springfield Tool And Die, Inc. | Piercing apparatus |
US4035723A (en) | 1975-10-16 | 1977-07-12 | Xynetics, Inc. | Probe arm |
US3992073A (en) | 1975-11-24 | 1976-11-16 | Technical Wire Products, Inc. | Multi-conductor probe |
US4116523A (en) | 1976-01-23 | 1978-09-26 | James M. Foster | High frequency probe |
US4049252A (en) | 1976-02-04 | 1977-09-20 | Bell Theodore F | Index table |
US4063195A (en) | 1976-03-26 | 1977-12-13 | Hughes Aircraft Company | Parametric frequency converter |
US4099120A (en) | 1976-04-19 | 1978-07-04 | Akin Aksu | Probe head for testing printed circuit boards |
US4027935A (en) | 1976-06-21 | 1977-06-07 | International Business Machines Corporation | Contact for an electrical contactor assembly |
US4115735A (en) | 1976-10-14 | 1978-09-19 | Faultfinders, Inc. | Test fixture employing plural platens for advancing some or all of the probes of the test fixture |
US4093988A (en) | 1976-11-08 | 1978-06-06 | General Electric Company | High speed frequency response measurement |
US4124787A (en) | 1977-03-11 | 1978-11-07 | Atari, Inc. | Joystick controller mechanism operating one or plural switches sequentially or simultaneously |
US4151465A (en) | 1977-05-16 | 1979-04-24 | Lenz Seymour S | Variable flexure test probe for microelectronic circuits |
US4161692A (en) | 1977-07-18 | 1979-07-17 | Cerprobe Corporation | Probe device for integrated circuit wafers |
US4216467A (en) | 1977-12-22 | 1980-08-05 | Westinghouse Electric Corp. | Hand controller |
US4232398A (en) | 1978-02-09 | 1980-11-04 | Motorola, Inc. | Radio receiver alignment indicator |
US4177421A (en) | 1978-02-27 | 1979-12-04 | Xerox Corporation | Capacitive transducer |
US4302146A (en) | 1978-08-23 | 1981-11-24 | Westinghouse Electric Corp. | Probe positioner |
US4225819A (en) | 1978-10-12 | 1980-09-30 | Bell Telephone Laboratories, Incorporated | Circuit board contact contamination probe |
US4306235A (en) | 1978-11-02 | 1981-12-15 | Cbc Corporation | Multiple frequency microwave antenna |
DE2849119A1 (en) | 1978-11-13 | 1980-05-14 | Siemens Ag | METHOD AND CIRCUIT FOR DAMPING MEASUREMENT, ESPECIALLY FOR DETERMINING THE DAMPING AND / OR GROUP DISTANCE DISTORTION OF A MEASURED OBJECT |
US4280112A (en) | 1979-02-21 | 1981-07-21 | Eisenhart Robert L | Electrical coupler |
US4287473A (en) | 1979-05-25 | 1981-09-01 | The United States Of America As Represented By The United States Department Of Energy | Nondestructive method for detecting defects in photodetector and solar cell devices |
US4277741A (en) | 1979-06-25 | 1981-07-07 | General Motors Corporation | Microwave acoustic spectrometer |
US4327180A (en) | 1979-09-14 | 1982-04-27 | Board Of Governors, Wayne State Univ. | Method and apparatus for electromagnetic radiation of biological material |
US4284033A (en) | 1979-10-31 | 1981-08-18 | Rca Corporation | Means to orbit and rotate target wafers supported on planet member |
US4330783A (en) | 1979-11-23 | 1982-05-18 | Toia Michael J | Coaxially fed dipole antenna |
US4284682A (en) | 1980-04-30 | 1981-08-18 | Nasa | Heat sealable, flame and abrasion resistant coated fabric |
US4340860A (en) | 1980-05-19 | 1982-07-20 | Trigon | Integrated circuit carrier package test probe |
US4357575A (en) | 1980-06-17 | 1982-11-02 | Dit-Mco International Corporation | Apparatus for use in testing printed circuit process boards having means for positioning such boards in proper juxtaposition with electrical contacting assemblies |
US4346355A (en) | 1980-11-17 | 1982-08-24 | Raytheon Company | Radio frequency energy launcher |
DE3531893A1 (en) * | 1985-09-06 | 1987-03-19 | Siemens Ag | METHOD FOR DETERMINING THE DISTRIBUTION OF DIELECTRICITY CONSTANTS IN AN EXAMINATION BODY, AND MEASURING ARRANGEMENT FOR IMPLEMENTING THE METHOD |
US4727319A (en) * | 1985-12-24 | 1988-02-23 | Hughes Aircraft Company | Apparatus for on-wafer testing of electrical circuits |
EP0442543B1 (en) * | 1986-01-24 | 1997-11-19 | Fuji Photo Film Co., Ltd. | Device for loading sheet films |
US4904933A (en) * | 1986-09-08 | 1990-02-27 | Tektronix, Inc. | Integrated circuit probe station |
FR2606887B1 (en) * | 1986-11-18 | 1989-01-13 | Thomson Semiconducteurs | CIRCUIT FOR MEASURING THE DYNAMIC CHARACTERISTICS OF A BOX FOR A FAST INTEGRATED CIRCUIT, AND METHOD FOR MEASURING THESE DYNAMIC CHARACTERISTICS |
JP2554669Y2 (en) * | 1987-11-10 | 1997-11-17 | 博 寺町 | Rotary positioning device |
JPH01133701U (en) * | 1988-03-07 | 1989-09-12 | ||
US4991290A (en) * | 1988-07-21 | 1991-02-12 | Microelectronics And Computer Technology | Flexible electrical interconnect and method of making |
US4893914A (en) * | 1988-10-12 | 1990-01-16 | The Micromanipulator Company, Inc. | Test station |
US4904935A (en) * | 1988-11-14 | 1990-02-27 | Eaton Corporation | Electrical circuit board text fixture having movable platens |
US5089774A (en) * | 1989-12-26 | 1992-02-18 | Sharp Kabushiki Kaisha | Apparatus and a method for checking a semiconductor |
JPH03209737A (en) * | 1990-01-11 | 1991-09-12 | Tokyo Electron Ltd | Probe equipment |
US5091732A (en) * | 1990-09-07 | 1992-02-25 | The United States Of America As Represented By The Secretary Of The Navy | Lightweight deployable antenna system |
JP3838381B2 (en) * | 1995-11-22 | 2006-10-25 | 株式会社アドバンテスト | Probe card |
US5889410A (en) * | 1996-05-22 | 1999-03-30 | International Business Machines Corporation | Floating gate interlevel defect monitor and method |
JPH1130649A (en) * | 1997-07-10 | 1999-02-02 | Mitsubishi Electric Corp | Semiconductor circuit testing method and testing device |
US5977813A (en) * | 1997-10-03 | 1999-11-02 | International Business Machines Corporation | Temperature monitor/compensation circuit for integrated circuits |
FR2775832B1 (en) * | 1998-03-05 | 2000-05-05 | St Microelectronics Sa | SEMICONDUCTOR TEST SYSTEM CARRIED OUT IN A CUTTING PATH OF A SEMICONDUCTOR WAFER |
US6121836A (en) * | 1998-05-08 | 2000-09-19 | Lucent Technologies | Differential amplifier |
DE10028145C2 (en) * | 2000-06-07 | 2002-04-18 | Infineon Technologies Ag | Integrated circuit arrangement for testing transistors and semiconductor wafer with such a circuit arrangement |
US7259043B2 (en) * | 2002-05-14 | 2007-08-21 | Texas Instruments Incorporated | Circular test pads on scribe street area |
US20050229053A1 (en) * | 2003-07-25 | 2005-10-13 | Logicvision, Inc., 101 Metro Drive, 3Rd Floor, San Jose, Ca, 95110 | Circuit and method for low frequency testing of high frequency signal waveforms |
TWI228597B (en) * | 2004-02-25 | 2005-03-01 | Nat Applied Res Laboratories | Device monitor for RF and DC measurements |
-
2007
- 2007-03-09 US US11/716,428 patent/US7443186B2/en not_active Expired - Fee Related
- 2007-05-03 WO PCT/US2007/010802 patent/WO2007145729A2/en active Application Filing
-
2008
- 2008-09-16 US US12/283,984 patent/US20090021273A1/en not_active Abandoned
Patent Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US491783A (en) * | 1893-02-14 | Bolster-plate | ||
US2143625A (en) * | 1931-08-25 | 1939-01-10 | Archie M Bovier | Manifolding record |
US2921276A (en) * | 1955-08-30 | 1960-01-12 | Cutler Hammer Inc | Microwave circuits |
US3230299A (en) * | 1962-07-18 | 1966-01-18 | Gen Cable Corp | Electrical cable with chemically bonded rubber layers |
US3429040A (en) * | 1965-06-18 | 1969-02-25 | Ibm | Method of joining a component to a substrate |
US3561280A (en) * | 1968-08-22 | 1971-02-09 | American Mach & Foundry | Three axis strain gage control device |
US3634807A (en) * | 1969-03-28 | 1972-01-11 | Siemens Ag | Detachable electrical contact arrangement |
US3714572A (en) * | 1970-08-21 | 1973-01-30 | Rca Corp | Alignment and test fixture apparatus |
US4009456A (en) * | 1970-10-07 | 1977-02-22 | General Microwave Corporation | Variable microwave attenuator |
US3710251A (en) * | 1971-04-07 | 1973-01-09 | Collins Radio Co | Microelectric heat exchanger pedestal |
US3862790A (en) * | 1971-07-22 | 1975-01-28 | Plessey Handel Investment Ag | Electrical interconnectors and connector assemblies |
US3866093A (en) * | 1972-09-18 | 1975-02-11 | Norbert L Kusters | Low leakage electrical power input circuit for electromedical and other similar apparatus |
US3867698A (en) * | 1973-03-01 | 1975-02-18 | Western Electric Co | Test probe for integrated circuit chips |
US3930809A (en) * | 1973-08-21 | 1976-01-06 | Wentworth Laboratories, Inc. | Assembly fixture for fixed point probe card |
US4001685A (en) * | 1974-03-04 | 1977-01-04 | Electroglas, Inc. | Micro-circuit test probe |
US3936743A (en) * | 1974-03-05 | 1976-02-03 | Electroglas, Inc. | High speed precision chuck assembly |
US4066943A (en) * | 1974-03-05 | 1978-01-03 | Electroglas, Inc. | High speed precision chuck assembly |
US4072576A (en) * | 1975-10-06 | 1978-02-07 | Ab Kabi | Method for studying enzymatic and other biochemical reactions |
US4008900A (en) * | 1976-03-15 | 1977-02-22 | John Freedom | Indexing chuck |
US4074201A (en) * | 1976-07-26 | 1978-02-14 | Gte Sylvania Incorporated | Signal analyzer with noise estimation and signal to noise readout |
US4312117A (en) * | 1977-09-01 | 1982-01-26 | Raytheon Company | Integrated test and assembly device |
US4184729A (en) * | 1977-10-13 | 1980-01-22 | Bunker Ramo Corporation | Flexible connector cable |
US4135131A (en) * | 1977-10-14 | 1979-01-16 | The United States Of America As Represented By The Secretary Of The Army | Microwave time delay spectroscopic methods and apparatus for remote interrogation of biological targets |
US4184133A (en) * | 1977-11-28 | 1980-01-15 | Rockwell International Corporation | Assembly of microwave integrated circuits having a structurally continuous ground plane |
US4251772A (en) * | 1978-12-26 | 1981-02-17 | Pacific Western Systems Inc. | Probe head for an automatic semiconductive wafer prober |
US4641659A (en) * | 1979-06-01 | 1987-02-10 | Sepponen Raimo E | Medical diagnostic microwave scanning apparatus |
US4491783A (en) * | 1981-04-25 | 1985-01-01 | Tokyo Shibaura Denki Kabushiki Kaisha | Apparatus for measuring noise factor and available gain |
US4425395A (en) * | 1981-04-30 | 1984-01-10 | Fujikura Rubber Works, Ltd. | Base fabrics for polyurethane-coated fabrics, polyurethane-coated fabrics and processes for their production |
US4563640A (en) * | 1981-06-03 | 1986-01-07 | Yoshiei Hasegawa | Fixed probe board |
US4567436A (en) * | 1982-01-21 | 1986-01-28 | Linda Koch | Magnetic thickness gauge with adjustable probe |
US4502028A (en) * | 1982-06-15 | 1985-02-26 | Raytheon Company | Programmable two-port microwave network |
US4568890A (en) * | 1982-12-23 | 1986-02-04 | U.S. Philips Corporation | Microwave oscillator injection locked at its fundamental frequency for producing a harmonic frequency output |
US4567321A (en) * | 1984-02-20 | 1986-01-28 | Junkosha Co., Ltd. | Flexible flat cable |
US4646005A (en) * | 1984-03-16 | 1987-02-24 | Motorola, Inc. | Signal probe |
US4722846A (en) * | 1984-04-18 | 1988-02-02 | Kikkoman Corporation | Novel variant and process for producing light colored soy sauce using such variant |
US4636722A (en) * | 1984-05-21 | 1987-01-13 | Probe-Rite, Inc. | High density probe-head with isolated and shielded transmission lines |
US4642417A (en) * | 1984-07-30 | 1987-02-10 | Kraftwerk Union Aktiengesellschaft | Concentric three-conductor cable |
US4636772A (en) * | 1985-01-17 | 1987-01-13 | Riken Denshi Co. Ltd. | Multiple function type D/A converter |
US4725793A (en) * | 1985-09-30 | 1988-02-16 | Alps Electric Co., Ltd. | Waveguide-microstrip line converter |
US4795962A (en) * | 1986-09-04 | 1989-01-03 | Hewlett-Packard Company | Floating driver circuit and a device for measuring impedances of electrical components |
US5082627A (en) * | 1987-05-01 | 1992-01-21 | Biotronic Systems Corporation | Three dimensional binding site array for interfering with an electrical field |
US4894612A (en) * | 1987-08-13 | 1990-01-16 | Hypres, Incorporated | Soft probe for providing high speed on-wafer connections to a circuit |
US5084671A (en) * | 1987-09-02 | 1992-01-28 | Tokyo Electron Limited | Electric probing-test machine having a cooling system |
US4988062A (en) * | 1988-03-10 | 1991-01-29 | London Robert A | Apparatus, system and method for organizing and maintaining a plurality of medical catheters and the like |
US4891584A (en) * | 1988-03-21 | 1990-01-02 | Semitest, Inc. | Apparatus for making surface photovoltage measurements of a semiconductor |
US4983910A (en) * | 1988-05-20 | 1991-01-08 | Stanford University | Millimeter-wave active probe |
US4987100A (en) * | 1988-05-26 | 1991-01-22 | International Business Machines Corporation | Flexible carrier for an electronic device |
US5280156A (en) * | 1990-12-25 | 1994-01-18 | Ngk Insulators, Ltd. | Wafer heating apparatus and with ceramic substrate and dielectric layer having electrostatic chucking means |
US5487999A (en) * | 1991-06-04 | 1996-01-30 | Micron Technology, Inc. | Method for fabricating a penetration limited contact having a rough textured surface |
US5177438A (en) * | 1991-08-02 | 1993-01-05 | Motorola, Inc. | Low resistance probe for semiconductor |
US5180977A (en) * | 1991-12-02 | 1993-01-19 | Hoya Corporation Usa | Membrane probe contact bump compliancy system |
US5281364A (en) * | 1992-05-22 | 1994-01-25 | Finch Limited | Liquid metal electrical contact compositions |
US6334247B1 (en) * | 1992-10-19 | 2002-01-01 | International Business Machines Corporation | High density integrated circuit apparatus, test probe and methods of use thereof |
US5383787A (en) * | 1993-04-27 | 1995-01-24 | Aptix Corporation | Integrated circuit package with direct access to internal signals |
US5481936A (en) * | 1993-06-29 | 1996-01-09 | Yugen Kaisha Sozoan | Rotary drive positioning system for an indexing table |
US5594358A (en) * | 1993-09-02 | 1997-01-14 | Matsushita Electric Industrial Co., Ltd. | Radio frequency probe and probe card including a signal needle and grounding needle coupled to a microstrip transmission line |
US6168974B1 (en) * | 1993-11-16 | 2001-01-02 | Formfactor, Inc. | Process of mounting spring contacts to semiconductor devices |
US6838893B2 (en) * | 1993-11-16 | 2005-01-04 | Formfactor, Inc. | Probe card assembly |
US6836962B2 (en) * | 1993-11-16 | 2005-01-04 | Formfactor, Inc. | Method and apparatus for shaping spring elements |
US20020011859A1 (en) * | 1993-12-23 | 2002-01-31 | Kenneth R. Smith | Method for forming conductive bumps for the purpose of contrructing a fine pitch test device |
US5704355A (en) * | 1994-07-01 | 1998-01-06 | Bridges; Jack E. | Non-invasive system for breast cancer detection |
US6181297B1 (en) * | 1994-08-25 | 2001-01-30 | Symmetricom, Inc. | Antenna |
US5481196A (en) * | 1994-11-08 | 1996-01-02 | Nebraska Electronics, Inc. | Process and apparatus for microwave diagnostics and therapy |
US6172337B1 (en) * | 1995-07-10 | 2001-01-09 | Mattson Technology, Inc. | System and method for thermal processing of a semiconductor substrate |
US6181149B1 (en) * | 1996-09-26 | 2001-01-30 | Delaware Capital Formation, Inc. | Grid array package test contactor |
US6013586A (en) * | 1997-10-09 | 2000-01-11 | Dimension Polyant Sailcloth, Inc. | Tent material product and method of making tent material product |
US6340568B2 (en) * | 1998-02-02 | 2002-01-22 | Signature Bioscience, Inc. | Method for detecting and classifying nucleic acid hybridization |
US6181144B1 (en) * | 1998-02-25 | 2001-01-30 | Micron Technology, Inc. | Semiconductor probe card having resistance measuring circuitry and method fabrication |
US6839964B2 (en) * | 1998-04-14 | 2005-01-11 | Formfactor, Inc. | Method for manufacturing a multi-layer printed circuit board |
US6181416B1 (en) * | 1998-04-14 | 2001-01-30 | Optometrix, Inc. | Schlieren method for imaging semiconductor device properties |
US20020011863A1 (en) * | 1998-06-09 | 2002-01-31 | Advantest Corporation | IC chip tester with heating element for preventing condensation |
US6176091B1 (en) * | 1998-10-01 | 2001-01-23 | Nkk Corporation | Method and apparatus for preventing snow from melting and for packing snow in artificial ski facility |
US6175228B1 (en) * | 1998-10-30 | 2001-01-16 | Agilent Technologies | Electronic probe for measuring high impedance tri-state logic circuits |
US6169410B1 (en) * | 1998-11-09 | 2001-01-02 | Anritsu Company | Wafer probe with built in RF frequency conversion module |
US6672875B1 (en) * | 1998-12-02 | 2004-01-06 | Formfactor, Inc. | Spring interconnect structures |
US6335625B1 (en) * | 1999-02-22 | 2002-01-01 | Paul Bryant | Programmable active microwave ultrafine resonance spectrometer (PAMURS) method and systems |
US6845491B2 (en) * | 1999-02-25 | 2005-01-18 | Formfactor, Inc. | Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes |
US6680659B2 (en) * | 1999-02-25 | 2004-01-20 | Formfactor, Inc. | Integrated circuit interconnect system |
US6678850B2 (en) * | 1999-03-01 | 2004-01-13 | Formfactor, Inc. | Distributed interface for parallel testing of multiple devices using a single tester channel |
US20020005728A1 (en) * | 1999-04-15 | 2002-01-17 | Gordon M. Babson | Micro probe and method of fabricating same |
US6340895B1 (en) * | 1999-07-14 | 2002-01-22 | Aehr Test Systems, Inc. | Wafer-level burn-in and test cartridge |
US6339338B1 (en) * | 2000-01-18 | 2002-01-15 | Formfactor, Inc. | Apparatus for reducing power supply noise in an integrated circuit |
US6509751B1 (en) * | 2000-03-17 | 2003-01-21 | Formfactor, Inc. | Planarizer for a semiconductor contactor |
US6677744B1 (en) * | 2000-04-13 | 2004-01-13 | Formfactor, Inc. | System for measuring signal path resistance for an integrated circuit tester interconnect structure |
US20020009377A1 (en) * | 2000-06-09 | 2002-01-24 | Shafer Ronny A. | Motor cover retention |
US20020008533A1 (en) * | 2000-07-05 | 2002-01-24 | Ando Electric Co., Ltd | Electro-optic probe and magneto-optic probe |
US20020009378A1 (en) * | 2000-07-21 | 2002-01-24 | Rikuro Obara | Blower |
US7315175B2 (en) * | 2001-01-30 | 2008-01-01 | Teraview Limited | Probe apparatus and method for examining a sample |
US6512482B1 (en) * | 2001-03-20 | 2003-01-28 | Xilinx, Inc. | Method and apparatus using a semiconductor die integrated antenna structure |
US20030010877A1 (en) * | 2001-07-12 | 2003-01-16 | Jean-Luc Landreville | Anti-vibration and anti-tilt structure |
US6678876B2 (en) * | 2001-08-24 | 2004-01-13 | Formfactor, Inc. | Process and apparatus for finding paths through a routing space |
US7161363B2 (en) * | 2002-05-23 | 2007-01-09 | Cascade Microtech, Inc. | Probe for testing a device under test |
US20040015060A1 (en) * | 2002-06-21 | 2004-01-22 | James Samsoondar | Measurement of body compounds |
US6987483B2 (en) * | 2003-02-21 | 2006-01-17 | Kyocera Wireless Corp. | Effectively balanced dipole microstrip antenna |
US6838885B2 (en) * | 2003-03-05 | 2005-01-04 | Murata Manufacturing Co., Ltd. | Method of correcting measurement error and electronic component characteristic measurement apparatus |
US7319335B2 (en) * | 2004-02-12 | 2008-01-15 | Applied Materials, Inc. | Configurable prober for TFT LCD array testing |
US7323899B2 (en) * | 2004-06-10 | 2008-01-29 | Texas Instruments Incorporated | System and method for resumed probing of a wafer |
US7319337B2 (en) * | 2005-02-25 | 2008-01-15 | Elpida Memory, Inc. | Method and apparatus for pad aligned multiprobe wafer testing |
US7323680B2 (en) * | 2005-04-12 | 2008-01-29 | Santec Corporation | Optical deflection probe and optical deflection probe device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180131054A1 (en) * | 2014-06-11 | 2018-05-10 | Enovate Medical Llc | Shielding receptacle for battery cells |
Also Published As
Publication number | Publication date |
---|---|
WO2007145729A2 (en) | 2007-12-21 |
US20070285112A1 (en) | 2007-12-13 |
US7443186B2 (en) | 2008-10-28 |
WO2007145729A3 (en) | 2008-05-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7443186B2 (en) | On-wafer test structures for differential signals | |
US7750652B2 (en) | Test structure and probe for differential signals | |
US7764072B2 (en) | Differential signal probing system | |
US6194739B1 (en) | Inline ground-signal-ground (GSG) RF tester | |
US7952375B2 (en) | AC coupled parameteric test probe | |
US4764723A (en) | Wafer probe | |
US7609077B2 (en) | Differential signal probe with integral balun | |
US7397259B1 (en) | Method and apparatus for statistical CMOS device characterization | |
US7723999B2 (en) | Calibration structures for differential signal probing | |
US7126359B2 (en) | Device monitor for RF and DC measurement | |
US6737879B2 (en) | Method and apparatus for wafer scale testing | |
US7388424B2 (en) | Apparatus for providing a high frequency loop back with a DC path for a parametric test | |
JP3318671B2 (en) | Multi-chip module and test chip manufacturing method | |
JP4870211B2 (en) | Differential signal test structure and probe | |
JP2003050262A (en) | High-frequency ic socket, semiconductor testing device, semiconductor test method and manufacturing method of semiconductor device | |
CN206920483U (en) | Probe card and semiconductor test apparatus | |
JPH01318245A (en) | Probe card inspection jig | |
CN105203852B (en) | Test board and testing scheme for integrated passive devices | |
JPH03205843A (en) | Probe card device | |
Schaper et al. | Design of the Interconnected Mesh Power System (IMPS) MCM Topology | |
JPH08330369A (en) | Interface card for prober | |
CN115707981A (en) | Method for testing electrical performance of device | |
Yin et al. | Wireless system for microwave test signal generation | |
Rodriguez-Tellez | Microwave probe for circuit/device testing | |
JPH03284861A (en) | Probe card |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CASCADE MICROTECH, INC., OREGON Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STRID, ERIC;CAMPBELL, RICHARD;REEL/FRAME:021898/0712;SIGNING DATES FROM 20070302 TO 20070307 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |