US20080262767A1

US20080262767A1 - Apparatus for a test and measurement instrument

Info

Publication number: US20080262767A1
Application number: US12/051,187
Authority: US
Inventors: Mehrab S. Sedeh
Original assignee: Tektronix Inc
Current assignee: Tektronix Inc
Priority date: 2007-04-23
Filing date: 2008-03-19
Publication date: 2008-10-23
Also published as: US20080263253A1; US20080262764A1; US7734442B2; US20080262766A1; US7574319B2; US7571067B2; US20080262763A1; US20080262765A1

Abstract

Apparatuses for a test and measurement instrument provide a scalable test and measurement instrument capable of handling the acquisition, transfer, analysis, and display of large quantities of waveform data as well as complex waveforms. The apparatus for a test and measurement instrument consists of multiple processors with memory connected to the processors. There are multiple bridges with each processor being connected to its own bridge. There are multiple system buses with each bridge been connected to its own system bus. There are multiple acquisition modules having signal bus interfaces with each system bus being connected to its own acquisition module and having its own acquisition hardware. Each piece of acquisition hardware is a direct memory access machine that can transfer data to any portion of the memory. There are multiple signal sources with each signal source being connected to its own signal bus interface.

Description

CLAIM FOR PRIORITY

The subject application claims priority from U.S. Patent Application Ser. No. 60/913,525, entitled, APPARATUS AND METHODS FOR A TEST AND MEASUREMENT INSTRUMENT EMPLOYING A MULTI-CORE HOST PROCESSOR (Sedeh, et al.), filed 23 Apr. 2007, and assigned to the same assignee as the subject invention.

CROSS-REFERENCE TO RELATED CASES

The subject application is related to the following U.S. patent applications, bearing attorney docket numbers 8361-US0, 8287-US2, 8287-US3, and 8287-US4, all claiming priority from U.S. Patent Application Ser. No. 60/913,525, entitled, APPARATUS AND METHODS FOR A TEST AND MEASUREMENT INSTRUMENT EMPLOYING A MULTI-CORE HOST PROCESSOR (Sedeh, et al.), filed 23 Apr. 2007, and all assigned to the same assignee as the subject invention.

FIELD OF THE INVENTION

The present invention relates to an apparatus for a test and measurement instrument for use in connection with analyzing waveforms. The apparatus for a test and measurement instrument has particular utility in connection with providing a scalable test and measurement instrument capable of handling the acquisition, transfer, analysis, and display of large quantities of waveform data as well as complex waveforms.

BACKGROUND OF THE INVENTION

Apparatuses for a test and measurement instrument are desirable for providing a scalable test and measurement instrument capable of handling the acquisition, transfer, analysis, and display of large quantities of waveform data as well as complex waveforms. Demand for new oscilloscope application features is growing, especially the ability to process ever-greater quantities of waveform data, because signals are becoming increasingly complex. Analyzing complex waveforms generates more intermediate data, which in turn requires more system memory access instances.
Most software applications have enjoyed regular performance gains for several decades, even without significant modifications, merely because of increases in computer hardware performance. Historically, Central Processing Unit (CPU) manufacturers have reliably increased processing speeds. However, performance gains through increasing CPU clock speeds are seriously inhibited presently by heat generation, electron leakage, and other physical limitations.
Since major processor manufacturers and architectures can no longer easily boost straight-line instruction throughput, performance gains in test and measurement instruments, such as oscilloscopes, will have to be accomplished in fundamentally different ways. Because CPU manufacturers have adopted dual core and multicore processors to increase performance, oscilloscope applications will have to enable concurrent processing in order to exploit the CPU performance gains that are becoming available. What is therefore needed is a practical apparatus that provides a scalable test and measurement instrument capable of handling large quantities of waveform data as well as complex waveforms.
The use of oscilloscopes is known in the prior art. For example, oscilloscopes currently manufactured by Tektronix, Inc. of Beaverton, Oreg. ship with a single core 3.42 GHz Pentium® processor from Intel. These prior art oscilloscopes cannot have their performance boosted through use of a faster single CPU because CPUs with higher clock speeds do not presently exist. Furthermore, mere replacement of the single core CPU with a dual core or multicore CPU offers minimal benefit because many of the important operations of an oscilloscope application are not CPU constrained. In an instrument that moves and processes a large quantity of data, system bus performance often is the instrument's performance bottleneck.
The addition of a multicore processor to existing oscilloscope architectures provides minimal benefit because the system bus cannot provide data as fast as the processors can process it. Furthermore, the data acquisition process is an inherently sequential four-step process, presenting additional challenges to the adoption of multicore CPU technology in oscilloscope applications. FIG. 1 depicts a single core processor prior art oscilloscope architecture that acquires and combines waveform data from four channels 120-126 into a single data record in the system memory 114. Conventionally, waveforms are stored in the local memory 130 of the acquisition hardware 118 in a first step and subsequently transferred serially to the system memory 114 via a Peripheral Component Interconnect (PCI) or Peripheral Component Interconnect Express (PCIe) system bus 116 and bridge 112 in a second step. The CPU 110 then analyzes the waveform data in a third step and causes the results to be shown on a display screen 128 in a fourth and final step. The acquisition hardware 118 may be embodied in a peripheral device attached to the system bus 116 that is operable by the operating system.
This four-step process is not easily amenable to parallelization. These four subtasks cannot be run at the same time on four CPU cores with this prior art architecture because each must be completed before the next can begin. Therefore, the inherently sequential nature of the data acquisition process prevents taking full advantage of multicore processor technology. The architecture's data transfer rate and system bandwidth pose limiting factors, which are likely to worsen. Next-generation real-time data acquisition hardware will have very large record lengths per channel. Existing oscilloscope architectures cannot transfer, analyze, and display that much data in real-time.
FIG. 2 shows a prior art oscilloscope system architecture employing a quad core CPU 300 developed by the inventors of the current invention to try to address some of these problems. A quad core CPU 310, 328, 330, and 332 is the dominant high-performance computer architecture in industry, known as Symmetric Multiprocessor (SMP) architecture. While the SMP architecture performs adequately in many respects, it unfortunately exhibits architectural limitations. In an SMP-based system, the use of a single system bus 316 for direct memory access (DMA) transfer of waveform data from the acquisition hardware's 318 local memory 334 to the system memory 314 provides minimal benefit because the system bus cannot provide data as fast as the processors can process it.
Preliminary performance testing on dual core and quad core high performance oscilloscopes using the architectures depicted in depicted in FIGS. 2 and 3 showed no significant performance gains over single core instruments. The lack of performance gains was not surprising because the prior art data acquisition process is sequential in nature. All processor cores must share the system bus. Because the system bus cannot provide data as fast as the application needs it to keep all of the processor cores busy simultaneously, very little parallel processing can occur, making the additional processor cores only marginally utilized.
Therefore, a need exists for a new and improved apparatus for a test and measurement instrument that can be used for providing a scalable test and measurement instrument capable of handling the acquisition, transfer, analysis, and display of large quantities of waveform data as well as complex waveforms. In this regard, the various embodiments of the present invention substantially fulfill at least some of these needs. In this respect, the apparatus for a test and measurement instrument according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in doing so provides an apparatus primarily developed for the purpose of providing a scalable test and measurement instrument capable of handling the acquisition, transfer, analysis, and display of large quantities of waveform data as well as complex waveforms.

SUMMARY OF THE INVENTION

The present invention provides an improved apparatus for a test and measurement instrument, and overcomes the above-mentioned disadvantages and drawbacks of the prior art. As such, the general purpose of the present invention, which will be described subsequently in greater detail, is to provide an improved apparatus for a test and measurement instrument that has all the advantages of the prior art mentioned above.
To attain this, the preferred embodiment of the present invention essentially comprises multiple processors with memory connected to the processors. There are multiple bridges with each processor being connected to its own bridge. There are multiple system buses with each bridge being connected to its own system bus. There are multiple acquisition modules having signal bus interfaces with each system bus being connected to its own acquisition module and having its own acquisition hardware. Each piece of acquisition hardware is a direct memory access machine that can transfer data to any portion of the memory. There are multiple signal sources with each signal source being connected to its own signal bus interface. There are, of course, additional features of the invention that will be described hereinafter and which will form the subject matter of the claims attached.
There has thus been outlined, rather broadly, the more important features of the invention in order that the detailed description thereof that follows may be better understood and in order that the present contribution to the art may be better appreciated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram view of a prior art single CPU oscilloscope architecture;

FIG. 2 is a block diagram view of a quad core CPU oscilloscope architecture; and

FIG. 3 is a block diagram view of the current embodiment of the apparatus for a test and measurement instrument constructed in accordance with the principles of the present invention.

The same reference numerals refer to the same parts throughout the various figures.

DESCRIPTION OF THE CURRENT EMBODIMENT

A preferred embodiment of the apparatus for a test and measurement instrument of the present invention is shown and generally designated by the reference numeral 10.
The principles of the present invention are applicable to a variety of computer hardware and software configurations. The term “computer hardware” or “hardware,” as used herein, refers to any machine or apparatus that is capable of accepting, performing logic operations on, storing, or displaying data, and includes without limitation processors and memory; the term “computer software” or “software,” refers to any set of instructions operable to cause computer hardware to perform an operation. A “computer,” as that term is used herein, includes without limitation any useful combination of hardware and software, and a “computer program” or “program” includes without limitation any software operable to cause computer hardware to accept, perform logic operations on, store, or display data. A computer program may, and often is, comprised of a plurality of smaller programming units, including without limitation subroutines, modules, functions, methods, and procedures. Thus, the functions of the present invention may be distributed among a plurality of computers and computer programs. The invention is described best, though, as a single computer program that configures and enables one or more general-purpose computers to implement the novel aspects of the invention.
FIG. 3 illustrates improved apparatus for a test and measurement instrument 10 of the present invention. More particularly, an architecture for the apparatus for a test and measurement instrument 10 is depicted with every oscilloscope channel 22, 34, 46, and 58 coupled to its own single or multicore CPU 12, 24, 36, and 48, creating acquisition pipes 60, 62, 64, and 66. For example, oscilloscope channel 22 is connected to acquisition pipe 60 by acquisition module 20. Acquisition module 20 collects data from oscilloscope channel 22 via a signal source bus 68 and includes a demux ring 76 that separates the collected data into separate files, each one containing at least one element of the original file. System bus 18 connects acquisition module 20 to bridge 16. Bridge 16 integrates the data from the system bus to the single or multicore CPU 12. Bridge 16 is connected to single or multicore CPU 12, which is in turn connected to system memory 14. System memory 14 stores incoming data from system bus 18 as well as intermediate and final calculations generated by single or multicore CPU 12. Each acquisition pipe has its own system bus 18, 30, 42, 54, single or multicore CPU 12, 24, 36, and 48, acquisition module 20, 32, 44, and 56 with local memory 84, 86, 88, and 90, signal source bus 68, 70, 72, and 74, and demux ring 76, 78, 80, and 82. Therefore, all of the acquisition pipes can operate simultaneously and converge in the display subsystem 68, with each bridge being directly connected to the display subsystem 69. This enables the collected data to be observed much faster than is the case with prior art oscilloscope architectures.
This architecture enables system I/O bandwidth to scale linearly with the number of acquisition pipes. A four-channel oscilloscope with this architecture has a system data transfer rate that is four times that of a conventional four-channel of oscilloscope because data can be transferred at the same time from all four channels using all four acquisition pipes simultaneously. The oscilloscope's processing capability also scales upward as the number of acquisition pipes increases because the number of CPUs increases.
While current embodiments of the apparatus for a test and measurement instrument have been described in detail, it should be apparent that modifications and variations thereto are possible, all of which fall within the true spirit and scope of the invention. With respect to the above description then, it is to be realized that the optimum dimensional relationships for the parts of the invention, to include variations in size, materials, shape, form, function and manner of operation, assembly and use, are deemed readily apparent and obvious to one skilled in the art, and all equivalent relationships to those illustrated in the drawings and described in the specification are intended to be encompassed by the present invention. For example, any suitable specialized processor such as Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), and Field Programmable Gate Arrays (FPGAs) may be used instead of the general-purpose single or multicore CPUs described. And although providing a scalable test and measurement instrument capable of handling the acquisition, transfer, analysis, and display of large quantities of waveform data as well as complex waveforms has been described, it should be appreciated that the apparatus for a test and measurement instrument herein described is also suitable for use as a logic analyzer, signal source instrument, real-time spectrum analyzer, or any other analytical instrument requiring multiple channels for data collection. Furthermore, any other suitable types of memory in addition to dynamic random access memory (DRAM) could be utilized.
Therefore, the foregoing is considered as illustrative only of the principles of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation shown and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

Claims

1. An apparatus for a test and measurement instrument, the instrument comprising:

a plurality of processors;

memory connected to the processors;

a plurality of bridges, wherein each processor is connected to its own bridge;

a plurality of system buses, wherein each bridge is connected to its own system bus;

a plurality of acquisition modules each having its own signal bus interface and acquisition memory, wherein each system bus is connected to its own acquisition module and has its own acquisition hardware, and wherein each piece of acquisition hardware comprises a direct memory access machine that can transfer data to any portion of the memory; and

a plurality of signal sources, wherein each signal source is connected to its own signal bus interface.

2. The apparatus for a test and measurement instrument as defined in claim 1, wherein at least one of the plurality of processors is a specialized processor selected from the group comprising graphics processing units, digital signal processors, and field-programmable gate arrays.

3. The apparatus for a test and measurement instrument as defined in claim 1, wherein each processor is a multicore processor.

4. The apparatus for a test and measurement instrument as defined in claim 1, including a display connected to each of the processors for displaying images based on signals acquired by the instrument.

5. The apparatus for a test and measurement instrument as defined in claim 1, wherein the display is connected to each of the processors by way of the bridges.

6. An apparatus for a test and measurement instrument, the instrument comprising:

memory;

a plurality of processors connected to the memory, each processor having a connected acquisition pipe;

each acquisition pipe including a bridge connected to the processor;

each acquisition pipe including a system bus connected to the bridge;

each acquisition pipe including a signal bus interface connected to the signal bus, wherein each system bus is connected to its own acquisition module and has its own acquisition hardware, and wherein each piece of acquisition hardware comprises a direct memory access machine that can transfer data to any portion of the memory; and

7. The apparatus for a test and measurement instrument as defined in claim 6, wherein at least one of the plurality of processors is a specialized processor selected from the group comprising graphics processing units, digital signal processors, and field-programmable gate arrays.

8. The apparatus for a test and measurement instrument as defined in claim 6, wherein each processor is a multicore processor.

9. The apparatus for a test and measurement instrument as defined in claim 6, including a display connected to each of the processors for displaying images based on signals acquired by the instrument.

10. The apparatus for a test and measurement instrument as defined in claim 6, wherein the display is connected to each of the processors by way of the bridges.